1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <sys/apic.h> 42 #include <io/pciex/pcie_nvidia.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 46 #define pci_getb (*pci_getb_func) 47 #define pci_getw (*pci_getw_func) 48 #define pci_getl (*pci_getl_func) 49 #define pci_putb (*pci_putb_func) 50 #define pci_putw (*pci_putw_func) 51 #define pci_putl (*pci_putl_func) 52 #define dcmn_err if (pci_boot_debug) cmn_err 53 54 #define CONFIG_INFO 0 55 #define CONFIG_UPDATE 1 56 #define CONFIG_NEW 2 57 #define CONFIG_FIX 3 58 #define COMPAT_BUFSIZE 512 59 60 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 61 #define LPC_IO_CONTROL_REG_1 0x40 62 #define AMD8111_ENABLENMI (uint8_t)0x80 63 #define DEVID_AMD8111_LPC 0x7468 64 65 struct pci_fixundo { 66 uint8_t bus; 67 uint8_t dev; 68 uint8_t fn; 69 void (*undofn)(uint8_t, uint8_t, uint8_t); 70 struct pci_fixundo *next; 71 }; 72 73 extern int pci_bios_nbus; 74 static uchar_t max_dev_pci = 32; /* PCI standard */ 75 int pci_boot_debug = 0; 76 extern struct memlist *find_bus_res(int, int); 77 static struct pci_fixundo *undolist = NULL; 78 79 /* 80 * Module prototypes 81 */ 82 static void enumerate_bus_devs(uchar_t bus, int config_op); 83 static void create_root_bus_dip(uchar_t bus); 84 static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 85 ushort_t, int); 86 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 87 ushort_t, ushort_t, uchar_t, uint_t, int); 88 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 89 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 90 static void add_model_prop(dev_info_t *, uint_t); 91 static void add_bus_range_prop(int); 92 static void add_bus_slot_names_prop(int); 93 static void add_ppb_ranges_prop(int); 94 static void add_bus_available_prop(int); 95 static void alloc_res_array(); 96 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 97 ushort_t deviceid); 98 99 extern int pci_slot_names_prop(int, char *, int); 100 101 /* set non-zero to force PCI peer-bus renumbering */ 102 int pci_bus_always_renumber = 0; 103 104 /* get the subordinate bus # for a root/peer bus */ 105 static int 106 pci_root_subbus(int bus, uchar_t *subbus) 107 { 108 ACPI_HANDLE hdl; 109 ACPI_BUFFER rb; 110 ACPI_RESOURCE *rp; 111 int rv; 112 113 if (pci_bus_res[bus].dip == NULL) { 114 /* non-used bus # */ 115 return (AE_ERROR); 116 } 117 if (acpica_find_pciobj(pci_bus_res[bus].dip, &hdl) != AE_OK) { 118 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 119 return (AE_ERROR); 120 } 121 122 rb.Length = ACPI_ALLOCATE_BUFFER; 123 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 124 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 125 return (AE_ERROR); 126 } 127 128 rv = AE_ERROR; 129 130 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 131 rp = ACPI_NEXT_RESOURCE(rp)) { 132 133 switch (rp->Type) { 134 case ACPI_RESOURCE_TYPE_ADDRESS16: 135 if (rp->Data.Address.ResourceType 136 != ACPI_BUS_NUMBER_RANGE) 137 continue; 138 *subbus = (uchar_t)rp->Data.Address16.Maximum; 139 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 140 break; 141 case ACPI_RESOURCE_TYPE_ADDRESS32: 142 if (rp->Data.Address.ResourceType 143 != ACPI_BUS_NUMBER_RANGE) 144 continue; 145 *subbus = (uchar_t)rp->Data.Address32.Maximum; 146 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 147 break; 148 case ACPI_RESOURCE_TYPE_ADDRESS64: 149 if (rp->Data.Address.ResourceType 150 != ACPI_BUS_NUMBER_RANGE) 151 continue; 152 *subbus = (uchar_t)rp->Data.Address64.Maximum; 153 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 154 break; 155 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 156 if (rp->Data.Address.ResourceType 157 != ACPI_BUS_NUMBER_RANGE) 158 continue; 159 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 160 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 161 break; 162 default: 163 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 164 continue; 165 } 166 167 /* found the bus-range resource */ 168 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 169 rv = AE_OK; 170 171 /* This breaks out of the resource scanning loop */ 172 break; 173 } 174 175 AcpiOsFree(rb.Pointer); 176 if (rv != AE_OK) 177 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 178 179 return (rv); 180 181 } 182 183 /* 184 * Enumerate all PCI devices 185 */ 186 void 187 pci_setup_tree() 188 { 189 uchar_t i, root_bus_addr = 0; 190 191 alloc_res_array(); 192 for (i = 0; i <= pci_bios_nbus; i++) { 193 pci_bus_res[i].par_bus = (uchar_t)-1; 194 pci_bus_res[i].root_addr = (uchar_t)-1; 195 pci_bus_res[i].sub_bus = i; 196 } 197 198 pci_bus_res[0].root_addr = root_bus_addr++; 199 create_root_bus_dip(0); 200 enumerate_bus_devs(0, CONFIG_INFO); 201 202 /* 203 * Now enumerate peer busses 204 * 205 * We loop till pci_bios_nbus. On most systems, there is 206 * one more bus at the high end, which implements the ISA 207 * compatibility bus. We don't care about that. 208 * 209 * Note: In the old (bootconf) enumeration, the peer bus 210 * address did not use the bus number, and there were 211 * too many peer busses created. The root_bus_addr is 212 * used to maintain the old peer bus address assignment. 213 * However, we stop enumerating phantom peers with no 214 * device below. 215 */ 216 for (i = 1; i <= pci_bios_nbus; i++) { 217 if (pci_bus_res[i].dip == NULL) { 218 pci_bus_res[i].root_addr = root_bus_addr++; 219 } 220 enumerate_bus_devs(i, CONFIG_INFO); 221 222 /* add slot-names property for named pci hot-plug slots */ 223 add_bus_slot_names_prop(i); 224 } 225 226 } 227 228 /* 229 * >0 = present, 0 = not present, <0 = error 230 */ 231 static int 232 pci_bbn_present(int bus) 233 { 234 ACPI_HANDLE hdl; 235 ACPI_BUFFER rb; 236 int rv; 237 238 /* no dip means no _BBN */ 239 if (pci_bus_res[bus].dip == NULL) 240 return (0); 241 242 rv = acpica_find_pciobj(pci_bus_res[bus].dip, &hdl); 243 if (rv != AE_OK) 244 return (-1); 245 246 rb.Length = ACPI_ALLOCATE_BUFFER; 247 248 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 249 250 if (rb.Length > 0) 251 AcpiOsFree(rb.Pointer); 252 253 if (rv == AE_OK) 254 return (1); 255 else if (rv == AE_NOT_FOUND) 256 return (0); 257 else 258 return (-1); 259 } 260 261 /* 262 * Return non-zero if any PCI bus in the system has an associated 263 * _BBN object, 0 otherwise. 264 */ 265 static int 266 pci_roots_have_bbn(void) 267 { 268 int i; 269 270 /* 271 * Scan the PCI busses and look for at least 1 _BBN 272 */ 273 for (i = 0; i <= pci_bios_nbus; i++) { 274 /* skip non-root (peer) PCI busses */ 275 if (pci_bus_res[i].par_bus != (uchar_t)-1) 276 continue; 277 278 if (pci_bbn_present(i) > 0) 279 return (1); 280 } 281 return (0); 282 283 } 284 285 /* 286 * return non-zero if the machine is one on which we renumber 287 * the internal pci unit-addresses 288 */ 289 static int 290 pci_bus_renumber() 291 { 292 ACPI_TABLE_HEADER *fadt; 293 294 if (pci_bus_always_renumber) 295 return (1); 296 297 /* get the FADT */ 298 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 299 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 300 return (0); 301 302 /* compare OEM Table ID to "SUNm31" */ 303 if (strncmp("SUNm31", fadt->OemId, 6)) 304 return (0); 305 else 306 return (1); 307 } 308 309 /* 310 * Initial enumeration of the physical PCI bus hierarchy can 311 * leave 'gaps' in the order of peer PCI bus unit-addresses. 312 * Systems with more than one peer PCI bus *must* have an ACPI 313 * _BBN object associated with each peer bus; use the presence 314 * of this object to remove gaps in the numbering of the peer 315 * PCI bus unit-addresses - only peer busses with an associated 316 * _BBN are counted. 317 */ 318 static void 319 pci_renumber_root_busses(void) 320 { 321 int pci_regs[] = {0, 0, 0}; 322 int i, root_addr = 0; 323 324 /* 325 * Currently, we only enable the re-numbering on specific 326 * Sun machines; this is a work-around for the more complicated 327 * issue of upgrade changing physical device paths 328 */ 329 if (!pci_bus_renumber()) 330 return; 331 332 /* 333 * If we find no _BBN objects at all, we either don't need 334 * to do anything or can't do anything anyway 335 */ 336 if (!pci_roots_have_bbn()) 337 return; 338 339 for (i = 0; i <= pci_bios_nbus; i++) { 340 /* skip non-root (peer) PCI busses */ 341 if (pci_bus_res[i].par_bus != (uchar_t)-1) 342 continue; 343 344 if (pci_bbn_present(i) < 1) { 345 pci_bus_res[i].root_addr = (uchar_t)-1; 346 continue; 347 } 348 349 ASSERT(pci_bus_res[i].dip != NULL); 350 if (pci_bus_res[i].root_addr != root_addr) { 351 /* update reg property for node */ 352 pci_bus_res[i].root_addr = root_addr; 353 pci_regs[0] = pci_bus_res[i].root_addr; 354 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 355 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 356 } 357 root_addr++; 358 } 359 } 360 361 static void 362 remove_resource_range(struct memlist **list, int *ranges, int range_count) 363 { 364 struct range { 365 uint32_t base; 366 uint32_t len; 367 }; 368 int index; 369 370 for (index = 0; index < range_count; index++) { 371 /* all done if list is or has become empty */ 372 if (*list == NULL) 373 break; 374 (void) memlist_remove(list, 375 (uint64_t)((struct range *)ranges)[index].base, 376 (uint64_t)((struct range *)ranges)[index].len); 377 } 378 } 379 380 static void 381 remove_used_resources() 382 { 383 dev_info_t *used; 384 int *narray; 385 uint_t ncount; 386 int status; 387 int bus; 388 389 used = ddi_find_devinfo("used-resources", -1, 0); 390 if (used == NULL) 391 return; 392 393 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 394 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 395 if (status == DDI_PROP_SUCCESS) { 396 for (bus = 0; bus <= pci_bios_nbus; bus++) 397 remove_resource_range(&pci_bus_res[bus].io_ports, 398 narray, ncount / 2); 399 ddi_prop_free(narray); 400 } 401 402 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 403 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 404 if (status == DDI_PROP_SUCCESS) { 405 for (bus = 0; bus <= pci_bios_nbus; bus++) 406 remove_resource_range(&pci_bus_res[bus].mem_space, 407 narray, ncount / 2); 408 ddi_prop_free(narray); 409 } 410 } 411 412 void 413 pci_reprogram(void) 414 { 415 int i, pci_reconfig = 1; 416 char *onoff; 417 418 /* 419 * Excise phantom roots if possible 420 */ 421 pci_renumber_root_busses(); 422 423 /* add bus-range property for root/peer bus nodes */ 424 for (i = 0; i <= pci_bios_nbus; i++) { 425 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 426 uchar_t subbus; 427 if (pci_root_subbus(i, &subbus) == AE_OK) 428 pci_bus_res[i].sub_bus = subbus; 429 add_bus_range_prop(i); 430 } 431 } 432 433 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 434 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 435 if (strcmp(onoff, "off") == 0) { 436 pci_reconfig = 0; 437 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 438 } 439 ddi_prop_free(onoff); 440 } 441 442 /* remove used-resources from PCI resource maps */ 443 remove_used_resources(); 444 445 for (i = 0; i <= pci_bios_nbus; i++) { 446 /* configure devices not configured by bios */ 447 if (pci_reconfig) 448 enumerate_bus_devs(i, CONFIG_NEW); 449 /* All dev programmed, so we can create available prop */ 450 add_bus_available_prop(i); 451 } 452 } 453 454 /* 455 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 456 */ 457 static void 458 create_root_bus_dip(uchar_t bus) 459 { 460 int pci_regs[] = {0, 0, 0}; 461 dev_info_t *dip; 462 463 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 464 465 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 466 (pnode_t)DEVI_SID_NODEID, &dip); 467 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 468 "#address-cells", 3); 469 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 470 "#size-cells", 2); 471 pci_regs[0] = pci_bus_res[bus].root_addr; 472 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 473 "reg", (int *)pci_regs, 3); 474 475 /* 476 * If system has PCIe bus, then create different properties 477 */ 478 if (create_pcie_root_bus(bus, dip) == B_FALSE) 479 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 480 "device_type", "pci"); 481 482 (void) ndi_devi_bind_driver(dip, 0); 483 pci_bus_res[bus].dip = dip; 484 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 485 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 486 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 487 488 if (bus != 0) 489 return; 490 491 /* 492 * Special treatment of bus 0: 493 * If no resource from MPSPEC/HRT, copy pcimem from boot 494 * and make I/O space the entire range starting at 0x100. There 495 * is no difference between prefetchable memory or not. 496 */ 497 if (pci_bus_res[0].mem_space == NULL) 498 pci_bus_res[0].mem_space = 499 memlist_dup(bootops->boot_mem->pcimem); 500 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 501 if (pci_bus_res[0].io_ports == NULL) 502 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xff00); 503 } 504 505 /* 506 * For any fixed configuration (often compatability) pci devices 507 * and those with their own expansion rom, create device nodes 508 * to hold the already configured device details. 509 */ 510 void 511 enumerate_bus_devs(uchar_t bus, int config_op) 512 { 513 uchar_t dev, func, nfunc, header; 514 ushort_t venid; 515 dev_info_t *dip; 516 struct pci_devfunc { 517 struct pci_devfunc *next; 518 dev_info_t *dip; 519 uchar_t bus; 520 uchar_t dev; 521 uchar_t func; 522 } *devlist = NULL, *entry; 523 524 if (config_op == CONFIG_NEW) { 525 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 526 } else if (config_op == CONFIG_FIX) { 527 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 528 } else 529 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 530 531 for (dev = 0; dev < max_dev_pci; dev++) { 532 nfunc = 1; 533 for (func = 0; func < nfunc; func++) { 534 535 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 536 dev, func); 537 538 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 539 540 if ((venid == 0xffff) || (venid == 0)) { 541 /* no function at this address */ 542 continue; 543 } 544 545 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 546 if (header == 0xff) { 547 continue; /* illegal value */ 548 } 549 550 /* 551 * according to some mail from Microsoft posted 552 * to the pci-drivers alias, their only requirement 553 * for a multifunction device is for the 1st 554 * function to have to PCI_HEADER_MULTI bit set. 555 */ 556 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 557 nfunc = 8; 558 } 559 560 if (config_op == CONFIG_FIX) { 561 /* 562 * If we're processing PCI fixes, no dip 563 * will be returned. 564 */ 565 (void) process_devfunc(bus, dev, func, header, 566 venid, config_op); 567 568 } else if (config_op == CONFIG_INFO) { 569 /* 570 * Create the node, unconditionally, on the 571 * first pass only. It may still need 572 * resource assignment, which will be 573 * done on the second, CONFIG_NEW, pass. 574 */ 575 dip = process_devfunc(bus, dev, func, header, 576 venid, config_op); 577 /* 578 * If dip isn't null, put on a list to 579 * save for reprogramming when config_op 580 * is CONFIG_NEW. 581 */ 582 583 if (dip) { 584 entry = kmem_alloc(sizeof (*entry), 585 KM_SLEEP); 586 entry->dip = dip; 587 entry->dev = dev; 588 entry->func = func; 589 entry->next = devlist; 590 devlist = entry; 591 } 592 } 593 } 594 } 595 596 if (config_op == CONFIG_NEW) { 597 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 598 while (devlist) { 599 entry = devlist; 600 devlist = entry->next; 601 cmn_err(CE_NOTE, 602 "!reprogram pci device [%d/%d/%d] (%s)", 603 bus, entry->dev, entry->func, 604 ddi_driver_name(entry->dip)); 605 (void) add_reg_props(entry->dip, bus, entry->dev, 606 entry->func, CONFIG_UPDATE, 0); 607 kmem_free(entry, sizeof (*entry)); 608 } 609 pci_bus_res[bus].privdata = NULL; 610 } else if (config_op != CONFIG_FIX) { 611 pci_bus_res[bus].privdata = devlist; 612 } 613 } 614 615 static int 616 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 617 ushort_t subvenid, ushort_t subdevid) 618 { 619 static int prop_exist = -1; 620 static char *pciide_str; 621 char compat[32]; 622 623 if (prop_exist == -1) { 624 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 625 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 626 &pciide_str) == DDI_SUCCESS); 627 } 628 629 if (!prop_exist) 630 return (0); 631 632 /* compare property value against various forms of compatible */ 633 if (subvenid) { 634 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 635 venid, devid, subvenid, subdevid, revid); 636 if (strcmp(pciide_str, compat) == 0) 637 return (1); 638 639 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 640 venid, devid, subvenid, subdevid); 641 if (strcmp(pciide_str, compat) == 0) 642 return (1); 643 644 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 645 subvenid, subdevid); 646 if (strcmp(pciide_str, compat) == 0) 647 return (1); 648 } 649 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 650 venid, devid, revid); 651 if (strcmp(pciide_str, compat) == 0) 652 return (1); 653 654 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 655 if (strcmp(pciide_str, compat) == 0) 656 return (1); 657 658 return (0); 659 } 660 661 static int 662 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 663 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 664 { 665 struct ide_table { /* table for PCI_MASS_OTHER */ 666 ushort_t venid; 667 ushort_t devid; 668 } *entry; 669 670 /* XXX SATA devices: need a way to add dynamically */ 671 static struct ide_table ide_other[] = { 672 {0x1095, 0x3112}, 673 {0x1095, 0x3114}, 674 {0x1095, 0x3512}, 675 {0, 0} 676 }; 677 678 if (basecl != PCI_CLASS_MASS) 679 return (0); 680 681 if (subcl == PCI_MASS_IDE) { 682 return (1); 683 } 684 685 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 686 return (0); 687 } 688 689 entry = &ide_other[0]; 690 while (entry->venid) { 691 if (entry->venid == venid && entry->devid == devid) 692 return (1); 693 entry++; 694 } 695 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 696 } 697 698 static int 699 is_display(uint_t classcode) 700 { 701 static uint_t disp_classes[] = { 702 0x000100, 703 0x030000, 704 0x030001 705 }; 706 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 707 708 for (i = 0; i < nclasses; i++) { 709 if (classcode == disp_classes[i]) 710 return (1); 711 } 712 return (0); 713 } 714 715 static void 716 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 717 void (*undofn)(uint8_t, uint8_t, uint8_t)) 718 { 719 struct pci_fixundo *newundo; 720 721 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 722 723 /* 724 * Adding an item to this list means that we must turn its NMIENABLE 725 * bit back on at a later time. 726 */ 727 newundo->bus = bus; 728 newundo->dev = dev; 729 newundo->fn = fn; 730 newundo->undofn = undofn; 731 newundo->next = undolist; 732 733 /* add to the undo list in LIFO order */ 734 undolist = newundo; 735 } 736 737 void 738 add_pci_fixes(void) 739 { 740 int i; 741 742 for (i = 0; i <= pci_bios_nbus; i++) { 743 /* 744 * For each bus, apply needed fixes to the appropriate devices. 745 * This must be done before the main enumeration loop because 746 * some fixes must be applied to devices normally encountered 747 * later in the pci scan (e.g. if a fix to device 7 must be 748 * applied before scanning device 6, applying fixes in the 749 * normal enumeration loop would obviously be too late). 750 */ 751 enumerate_bus_devs(i, CONFIG_FIX); 752 } 753 } 754 755 void 756 undo_pci_fixes(void) 757 { 758 struct pci_fixundo *nextundo; 759 uint8_t bus, dev, fn; 760 761 /* 762 * All fixes in the undo list are performed unconditionally. Future 763 * fixes may require selective undo. 764 */ 765 while (undolist != NULL) { 766 767 bus = undolist->bus; 768 dev = undolist->dev; 769 fn = undolist->fn; 770 771 (*(undolist->undofn))(bus, dev, fn); 772 773 nextundo = undolist->next; 774 kmem_free(undolist, sizeof (struct pci_fixundo)); 775 undolist = nextundo; 776 } 777 } 778 779 static void 780 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 781 { 782 uint8_t val8; 783 784 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 785 /* 786 * The NMIONERR bit is turned back on to allow the SMM BIOS 787 * to handle more critical PCI errors (e.g. PERR#). 788 */ 789 val8 |= AMD8111_ENABLENMI; 790 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 791 } 792 793 static void 794 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 795 { 796 uint8_t val8; 797 798 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 799 800 if ((val8 & AMD8111_ENABLENMI) == 0) 801 return; 802 803 /* 804 * We reset NMIONERR in the LPC because master-abort on the PCI 805 * bridge side of the 8111 will cause NMI, which might cause SMI, 806 * which sometimes prevents all devices from being enumerated. 807 */ 808 val8 &= ~AMD8111_ENABLENMI; 809 810 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 811 812 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 813 } 814 815 static dev_info_t * 816 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 817 ushort_t vendorid, int config_op) 818 { 819 char nodename[32], unitaddr[5]; 820 dev_info_t *dip; 821 uchar_t basecl, subcl, progcl, intr, revid; 822 ushort_t subvenid, subdevid, status; 823 ushort_t slot_num; 824 uint_t classcode, revclass; 825 int reprogram = 0, pciide; 826 int power[2] = {1, 1}; 827 int pciex = 0; 828 ushort_t is_pci_bridge = 0; 829 830 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 831 832 switch (header & PCI_HEADER_TYPE_M) { 833 case PCI_HEADER_ZERO: 834 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 835 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 836 break; 837 case PCI_HEADER_CARDBUS: 838 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 839 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 840 break; 841 default: 842 subvenid = 0; 843 subdevid = 0; 844 break; 845 } 846 847 if (config_op == CONFIG_FIX) { 848 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 849 pci_fix_amd8111(bus, dev, func); 850 } 851 return (NULL); 852 } 853 854 /* XXX should be use generic names? derive from class? */ 855 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 856 classcode = revclass >> 8; 857 revid = revclass & 0xff; 858 859 /* figure out if this is pci-ide */ 860 basecl = classcode >> 16; 861 subcl = (classcode >> 8) & 0xff; 862 progcl = classcode & 0xff; 863 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 864 subvenid, subdevid); 865 866 if (pciide) 867 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 868 else if (is_display(classcode)) 869 (void) snprintf(nodename, sizeof (nodename), "display"); 870 else if (subvenid != 0) 871 (void) snprintf(nodename, sizeof (nodename), 872 "pci%x,%x", subvenid, subdevid); 873 else 874 (void) snprintf(nodename, sizeof (nodename), 875 "pci%x,%x", vendorid, deviceid); 876 877 /* make sure parent bus dip has been created */ 878 if (pci_bus_res[bus].dip == NULL) { 879 create_root_bus_dip(bus); 880 } 881 882 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 883 DEVI_SID_NODEID, &dip); 884 885 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 886 &is_pci_bridge) == B_TRUE) 887 pciex = 1; 888 889 /* add properties */ 890 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 891 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 892 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 893 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 894 "class-code", classcode); 895 if (func == 0) 896 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 897 else 898 (void) snprintf(unitaddr, sizeof (unitaddr), 899 "%x,%x", dev, func); 900 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 901 "unit-address", unitaddr); 902 903 /* add device_type for display nodes */ 904 if (is_display(classcode)) { 905 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 906 "device_type", "display"); 907 } 908 /* add special stuff for header type */ 909 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 910 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 911 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 912 913 if (subvenid != 0) { 914 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 915 "subsystem-id", subdevid); 916 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 917 "subsystem-vendor-id", subvenid); 918 } 919 if (!pciex) 920 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 921 "min-grant", mingrant); 922 if (!pciex) 923 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 924 "max-latency", maxlatency); 925 } 926 927 /* interrupt, record if not 0 */ 928 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 929 if (intr != 0) 930 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 931 "interrupts", intr); 932 933 /* 934 * Add support for 133 mhz pci eventually 935 */ 936 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 937 938 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 939 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 940 if (!pciex && (status & PCI_STAT_FBBC)) 941 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 942 "fast-back-to-back"); 943 if (!pciex && (status & PCI_STAT_66MHZ)) 944 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 945 "66mhz-capable"); 946 if (status & PCI_STAT_UDF) 947 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 948 "udf-supported"); 949 if (pciex && slot_num) 950 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 951 "physical-slot#", slot_num); 952 953 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 954 "power-consumption", power, 2); 955 956 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 957 add_ppb_props(dip, bus, dev, func, pciex); 958 959 if (config_op == CONFIG_INFO && 960 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 961 create_ioapic_node(bus, dev, func, vendorid, deviceid); 962 } 963 964 /* check for ck8-04 based PCI ISA bridge only */ 965 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 966 (func == 0)) 967 add_nvidia_isa_bridge_props(dip, bus, dev, func); 968 969 if (pciex && is_pci_bridge) 970 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 971 (char *)"PCIe-PCI bridge"); 972 else 973 add_model_prop(dip, classcode); 974 975 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 976 revid, classcode, pciex); 977 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 978 (void) ndi_devi_bind_driver(dip, 0); 979 980 /* special handling for pci-ide */ 981 if (pciide) { 982 dev_info_t *cdip; 983 984 /* 985 * Create properties specified by P1275 Working Group 986 * Proposal #414 Version 1 987 */ 988 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 989 "device_type", "pci-ide"); 990 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 991 "#address-cells", 1); 992 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 993 "#size-cells", 0); 994 995 /* allocate two child nodes */ 996 ndi_devi_alloc_sleep(dip, "ide", 997 (pnode_t)DEVI_SID_NODEID, &cdip); 998 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 999 "reg", 0); 1000 (void) ndi_devi_bind_driver(cdip, 0); 1001 ndi_devi_alloc_sleep(dip, "ide", 1002 (pnode_t)DEVI_SID_NODEID, &cdip); 1003 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1004 "reg", 1); 1005 (void) ndi_devi_bind_driver(cdip, 0); 1006 1007 reprogram = 0; /* don't reprogram pci-ide bridge */ 1008 } 1009 1010 1011 if (reprogram) 1012 return (dip); 1013 return (NULL); 1014 } 1015 1016 /* 1017 * Set the compatible property to a value compliant with 1018 * rev 2.1 of the IEEE1275 PCI binding. 1019 * (Also used for PCI-Express devices). 1020 * 1021 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1022 * pciVVVV,DDDD.SSSS.ssss (1) 1023 * pciSSSS,ssss (2) 1024 * pciVVVV,DDDD.RR (3) 1025 * pciVVVV,DDDD (4) 1026 * pciclass,CCSSPP (5) 1027 * pciclass,CCSS (6) 1028 * 1029 * The Subsystem (SSSS) forms are not inserted if 1030 * subsystem-vendor-id is 0. 1031 * 1032 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1033 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1034 * 1035 * Set with setprop and \x00 between each 1036 * to generate the encoded string array form. 1037 */ 1038 void 1039 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1040 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1041 int pciex) 1042 { 1043 int i = 0; 1044 int size = COMPAT_BUFSIZE; 1045 char *compat[13]; 1046 char *buf, *curr; 1047 1048 curr = buf = kmem_alloc(size, KM_SLEEP); 1049 1050 if (pciex) { 1051 if (subvenid) { 1052 compat[i++] = curr; /* form 0 */ 1053 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1054 vendorid, deviceid, subvenid, subdevid, revid); 1055 size -= strlen(curr) + 1; 1056 curr += strlen(curr) + 1; 1057 1058 compat[i++] = curr; /* form 1 */ 1059 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1060 vendorid, deviceid, subvenid, subdevid); 1061 size -= strlen(curr) + 1; 1062 curr += strlen(curr) + 1; 1063 1064 } 1065 compat[i++] = curr; /* form 3 */ 1066 (void) snprintf(curr, size, "pciex%x,%x.%x", 1067 vendorid, deviceid, revid); 1068 size -= strlen(curr) + 1; 1069 curr += strlen(curr) + 1; 1070 1071 compat[i++] = curr; /* form 4 */ 1072 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1073 size -= strlen(curr) + 1; 1074 curr += strlen(curr) + 1; 1075 1076 compat[i++] = curr; /* form 5 */ 1077 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1078 size -= strlen(curr) + 1; 1079 curr += strlen(curr) + 1; 1080 1081 compat[i++] = curr; /* form 6 */ 1082 (void) snprintf(curr, size, "pciexclass,%04x", 1083 (classcode >> 8)); 1084 size -= strlen(curr) + 1; 1085 curr += strlen(curr) + 1; 1086 } 1087 1088 if (subvenid) { 1089 compat[i++] = curr; /* form 0 */ 1090 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1091 vendorid, deviceid, subvenid, subdevid, revid); 1092 size -= strlen(curr) + 1; 1093 curr += strlen(curr) + 1; 1094 1095 compat[i++] = curr; /* form 1 */ 1096 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1097 vendorid, deviceid, subvenid, subdevid); 1098 size -= strlen(curr) + 1; 1099 curr += strlen(curr) + 1; 1100 1101 compat[i++] = curr; /* form 2 */ 1102 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1103 size -= strlen(curr) + 1; 1104 curr += strlen(curr) + 1; 1105 } 1106 compat[i++] = curr; /* form 3 */ 1107 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1108 size -= strlen(curr) + 1; 1109 curr += strlen(curr) + 1; 1110 1111 compat[i++] = curr; /* form 4 */ 1112 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1113 size -= strlen(curr) + 1; 1114 curr += strlen(curr) + 1; 1115 1116 compat[i++] = curr; /* form 5 */ 1117 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1118 size -= strlen(curr) + 1; 1119 curr += strlen(curr) + 1; 1120 1121 compat[i++] = curr; /* form 6 */ 1122 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1123 size -= strlen(curr) + 1; 1124 curr += strlen(curr) + 1; 1125 1126 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1127 "compatible", compat, i); 1128 kmem_free(buf, COMPAT_BUFSIZE); 1129 } 1130 1131 /* 1132 * Adjust the reg properties for a dual channel PCI-IDE device. 1133 * 1134 * NOTE: don't do anything that changes the order of the hard-decodes 1135 * and programmed BARs. The kernel driver depends on these values 1136 * being in this order regardless of whether they're for a 'native' 1137 * mode BAR or not. 1138 */ 1139 /* 1140 * config info for pci-ide devices 1141 */ 1142 static struct { 1143 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1144 uchar_t bar_offset; /* offset for alt status register */ 1145 ushort_t addr; /* compatibility mode base address */ 1146 ushort_t length; /* number of ports for this BAR */ 1147 } pciide_bar[] = { 1148 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1149 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1150 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1151 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1152 }; 1153 1154 static int 1155 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1156 { 1157 int hard_decode = 0; 1158 1159 /* 1160 * Adjust the base and len for the BARs of the PCI-IDE 1161 * device's primary and secondary controllers. The first 1162 * two BARs are for the primary controller and the next 1163 * two BARs are for the secondary controller. The fifth 1164 * and sixth bars are never adjusted. 1165 */ 1166 if (index >= 0 && index <= 3) { 1167 *lenp = pciide_bar[index].length; 1168 1169 if (progcl & pciide_bar[index].native_mask) { 1170 *basep += pciide_bar[index].bar_offset; 1171 } else { 1172 *basep = pciide_bar[index].addr; 1173 hard_decode = 1; 1174 } 1175 } 1176 1177 /* 1178 * if either base or len is zero make certain both are zero 1179 */ 1180 if (*basep == 0 || *lenp == 0) { 1181 *basep = 0; 1182 *lenp = 0; 1183 hard_decode = 0; 1184 } 1185 1186 return (hard_decode); 1187 } 1188 1189 1190 /* 1191 * Add the "reg" and "assigned-addresses" property 1192 */ 1193 static int 1194 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1195 int config_op, int pciide) 1196 { 1197 uchar_t baseclass, subclass, progclass, header; 1198 ushort_t bar_sz; 1199 uint_t value = 0, len, devloc; 1200 uint_t base, base_hi, type; 1201 ushort_t offset, end; 1202 int max_basereg, j, reprogram = 0; 1203 uint_t phys_hi; 1204 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1205 uint16_t cmd_reg; 1206 1207 pci_regspec_t regs[16] = {{0}}; 1208 pci_regspec_t assigned[15] = {{0}}; 1209 int nreg, nasgn, enable = 0; 1210 1211 io_res = &pci_bus_res[bus].io_ports; 1212 mem_res = &pci_bus_res[bus].mem_space; 1213 if (bus == 0) /* for bus 0, there is only mem_space */ 1214 pmem_res = mem_res; 1215 else 1216 pmem_res = &pci_bus_res[bus].pmem_space; 1217 1218 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1219 regs[0].pci_phys_hi = devloc; 1220 nreg = 1; /* rest of regs[0] is all zero */ 1221 nasgn = 0; 1222 1223 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1224 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1225 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1226 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1227 1228 switch (header) { 1229 case PCI_HEADER_ZERO: 1230 max_basereg = PCI_BASE_NUM; 1231 break; 1232 case PCI_HEADER_PPB: 1233 max_basereg = PCI_BCNF_BASE_NUM; 1234 break; 1235 case PCI_HEADER_CARDBUS: 1236 max_basereg = PCI_CBUS_BASE_NUM; 1237 break; 1238 default: 1239 max_basereg = 0; 1240 break; 1241 } 1242 1243 /* 1244 * Create the register property by saving the current 1245 * value of the base register. Write 0xffffffff to the 1246 * base register. Read the value back to determine the 1247 * required size of the address space. Restore the base 1248 * register contents. 1249 * 1250 * Do not disable I/O and memory access; this isn't necessary 1251 * since no driver is yet attached to this device, and disabling 1252 * I/O and memory access has the side-effect of disabling PCI-PCI 1253 * bridge mappings, which makes the bridge transparent to secondary- 1254 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1255 * Spec V1.2). 1256 */ 1257 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1258 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1259 j++, offset += bar_sz) { 1260 int hard_decode = 0; 1261 1262 /* determine the size of the address space */ 1263 base = pci_getl(bus, dev, func, offset); 1264 pci_putl(bus, dev, func, offset, 0xffffffff); 1265 value = pci_getl(bus, dev, func, offset); 1266 pci_putl(bus, dev, func, offset, base); 1267 1268 /* construct phys hi,med.lo, size hi, lo */ 1269 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1270 /* i/o space */ 1271 bar_sz = PCI_BAR_SZ_32; 1272 value &= PCI_BASE_IO_ADDR_M; 1273 len = ((value ^ (value-1)) + 1) >> 1; 1274 1275 /* XXX Adjust first 4 IDE registers */ 1276 if (pciide) { 1277 if (subclass != PCI_MASS_IDE) 1278 progclass = (PCI_IDE_IF_NATIVE_PRI | 1279 PCI_IDE_IF_NATIVE_SEC); 1280 hard_decode = pciIdeAdjustBAR(progclass, j, 1281 &base, &len); 1282 } else if (value == 0) { 1283 /* skip base regs with size of 0 */ 1284 continue; 1285 } 1286 1287 regs[nreg].pci_size_low = 1288 assigned[nasgn].pci_size_low = len; 1289 if (!hard_decode) { 1290 regs[nreg].pci_phys_hi = 1291 (PCI_ADDR_IO | devloc) + offset; 1292 } else { 1293 regs[nreg].pci_phys_hi = 1294 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1295 offset; 1296 regs[nreg].pci_phys_low = 1297 base & PCI_BASE_IO_ADDR_M; 1298 } 1299 assigned[nasgn].pci_phys_hi = 1300 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1301 type = base & (~PCI_BASE_IO_ADDR_M); 1302 base &= PCI_BASE_IO_ADDR_M; 1303 1304 /* 1305 * first pass - gather what's there 1306 * update/second pass - adjust/allocate regions 1307 * config - allocate regions 1308 */ 1309 if (config_op == CONFIG_INFO) { /* first pass */ 1310 /* take out of the resource map of the bus */ 1311 if (*io_res && base != 0) 1312 (void) memlist_remove(io_res, 1313 (uint64_t)base, (uint64_t)len); 1314 else if (*io_res) 1315 reprogram = 1; 1316 } else if (*io_res && base == 0) { 1317 base = (uint_t)memlist_find(io_res, 1318 (uint64_t)len, (uint64_t)0x4); 1319 if (base != 0) { 1320 /* XXX need to worry about 64-bit? */ 1321 pci_putl(bus, dev, func, offset, 1322 base | type); 1323 base = pci_getl(bus, dev, func, offset); 1324 base &= PCI_BASE_IO_ADDR_M; 1325 } 1326 if (base == 0) { 1327 cmn_err(CE_WARN, "failed to program" 1328 " IO space [%d/%d/%d] BAR@0x%x" 1329 " length 0x%x", 1330 bus, dev, func, offset, len); 1331 } else 1332 enable |= PCI_COMM_IO; 1333 } 1334 assigned[nasgn].pci_phys_low = base; 1335 nreg++, nasgn++; 1336 1337 } else { 1338 /* memory space */ 1339 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1340 bar_sz = PCI_BAR_SZ_64; 1341 base_hi = pci_getl(bus, dev, func, offset + 4); 1342 phys_hi = PCI_ADDR_MEM64; 1343 } else { 1344 bar_sz = PCI_BAR_SZ_32; 1345 base_hi = 0; 1346 phys_hi = PCI_ADDR_MEM32; 1347 } 1348 1349 /* skip base regs with size of 0 */ 1350 value &= PCI_BASE_M_ADDR_M; 1351 1352 if (value == 0) { 1353 continue; 1354 } 1355 len = ((value ^ (value-1)) + 1) >> 1; 1356 regs[nreg].pci_size_low = 1357 assigned[nasgn].pci_size_low = len; 1358 1359 phys_hi |= (devloc | offset); 1360 if (base & PCI_BASE_PREF_M) { 1361 mres = pmem_res; 1362 phys_hi |= PCI_PREFETCH_B; 1363 } else { 1364 mres = mem_res; 1365 } 1366 regs[nreg].pci_phys_hi = 1367 assigned[nasgn].pci_phys_hi = phys_hi; 1368 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1369 assigned[nasgn].pci_phys_mid = base_hi; 1370 type = base & ~PCI_BASE_M_ADDR_M; 1371 base &= PCI_BASE_M_ADDR_M; 1372 1373 if (config_op == CONFIG_INFO) { 1374 /* take out of the resource map of the bus */ 1375 if (*mres && base != 0) { 1376 (void) memlist_remove(mres, 1377 (uint64_t)base, (uint64_t)len); 1378 } else if (*mres) 1379 reprogram = 1; 1380 } else if (*mres && base == 0) { 1381 base = (uint_t)memlist_find(mres, 1382 (uint64_t)len, (uint64_t)0x1000); 1383 if (base != NULL) { 1384 pci_putl(bus, dev, func, offset, 1385 base | type); 1386 base = pci_getl(bus, dev, func, offset); 1387 base &= PCI_BASE_M_ADDR_M; 1388 } 1389 1390 if (base == 0) { 1391 cmn_err(CE_WARN, "failed to program " 1392 "mem space [%d/%d/%d] BAR@0x%x" 1393 " length 0x%x", 1394 bus, dev, func, offset, len); 1395 } else 1396 enable |= PCI_COMM_MAE; 1397 } 1398 assigned[nasgn].pci_phys_low = base; 1399 nreg++, nasgn++; 1400 } 1401 } 1402 switch (header) { 1403 case PCI_HEADER_ZERO: 1404 offset = PCI_CONF_ROM; 1405 break; 1406 case PCI_HEADER_PPB: 1407 offset = PCI_BCNF_ROM; 1408 break; 1409 default: /* including PCI_HEADER_CARDBUS */ 1410 goto done; 1411 } 1412 1413 /* 1414 * Add the expansion rom memory space 1415 * Determine the size of the ROM base reg; don't write reserved bits 1416 * ROM isn't in the PCI memory space. 1417 */ 1418 base = pci_getl(bus, dev, func, offset); 1419 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1420 value = pci_getl(bus, dev, func, offset); 1421 pci_putl(bus, dev, func, offset, base); 1422 if (value & PCI_BASE_ROM_ENABLE) 1423 value &= PCI_BASE_ROM_ADDR_M; 1424 else 1425 value = 0; 1426 1427 if (value != 0) { 1428 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1429 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1430 PCI_ADDR_MEM32 | devloc) + offset; 1431 base &= PCI_BASE_ROM_ADDR_M; 1432 assigned[nasgn].pci_phys_low = base; 1433 len = ((value ^ (value-1)) + 1) >> 1; 1434 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1435 nreg++, nasgn++; 1436 /* take it out of the memory resource */ 1437 if (*mem_res && base != 0) 1438 (void) memlist_remove(mem_res, 1439 (uint64_t)base, (uint64_t)len); 1440 } 1441 1442 /* 1443 * The following are ISA resources. There are not part 1444 * of the PCI local bus resources. So don't attempt to 1445 * do resource accounting against PCI. 1446 */ 1447 1448 /* add the three hard-decode, aliased address spaces for VGA */ 1449 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1450 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1451 1452 /* VGA hard decode 0x3b0-0x3bb */ 1453 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1454 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1455 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1456 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1457 nreg++, nasgn++; 1458 1459 /* VGA hard decode 0x3c0-0x3df */ 1460 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1461 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1462 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1463 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1464 nreg++, nasgn++; 1465 1466 /* Video memory */ 1467 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1468 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1469 regs[nreg].pci_phys_low = 1470 assigned[nasgn].pci_phys_low = 0xa0000; 1471 regs[nreg].pci_size_low = 1472 assigned[nasgn].pci_size_low = 0x20000; 1473 nreg++, nasgn++; 1474 } 1475 1476 /* add the hard-decode, aliased address spaces for 8514 */ 1477 if ((baseclass == PCI_CLASS_DISPLAY) && 1478 (subclass == PCI_DISPLAY_VGA) && 1479 (progclass & PCI_DISPLAY_IF_8514)) { 1480 1481 /* hard decode 0x2e8 */ 1482 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1483 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1484 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1485 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1486 nreg++, nasgn++; 1487 1488 /* hard decode 0x2ea-0x2ef */ 1489 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1490 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1491 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1492 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1493 nreg++, nasgn++; 1494 } 1495 1496 done: 1497 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1498 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1499 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1500 "assigned-addresses", 1501 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1502 if (config_op == CONFIG_NEW && enable) { 1503 cmn_err(CE_NOTE, 1504 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1505 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1506 cmd_reg |= (enable | PCI_COMM_ME); 1507 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1508 } 1509 return (reprogram); 1510 } 1511 1512 static void 1513 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1514 int pciex) 1515 { 1516 char *dev_type; 1517 int i; 1518 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1519 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1520 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1521 ASSERT(secbus <= subbus); 1522 1523 /* 1524 * Some BIOSes lie about max pci busses, we allow for 1525 * such mistakes here 1526 */ 1527 if (subbus > pci_bios_nbus) { 1528 pci_bios_nbus = subbus; 1529 alloc_res_array(); 1530 } 1531 1532 ASSERT(pci_bus_res[secbus].dip == NULL); 1533 pci_bus_res[secbus].dip = dip; 1534 pci_bus_res[secbus].par_bus = bus; 1535 1536 dev_type = pciex ? "pciex" : "pci"; 1537 1538 /* setup bus number hierarchy */ 1539 pci_bus_res[secbus].sub_bus = subbus; 1540 /* 1541 * Keep track of the largest subordinate bus number (this is essential 1542 * for peer busses because there is no other way of determining its 1543 * subordinate bus number). 1544 */ 1545 if (subbus > pci_bus_res[bus].sub_bus) 1546 pci_bus_res[bus].sub_bus = subbus; 1547 /* 1548 * Loop through subordinate busses, initializing their parent bus 1549 * field to this bridge's parent. The subordinate busses' parent 1550 * fields may very well be further refined later, as child bridges 1551 * are enumerated. (The value is to note that the subordinate busses 1552 * are not peer busses by changing their par_bus fields to anything 1553 * other than -1.) 1554 */ 1555 for (i = secbus + 1; i <= subbus; i++) 1556 pci_bus_res[i].par_bus = bus; 1557 1558 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1559 "device_type", dev_type); 1560 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1561 "#address-cells", 3); 1562 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1563 "#size-cells", 2); 1564 1565 /* 1566 * According to PPB spec, the base register should be programmed 1567 * with a value bigger than the limit register when there are 1568 * no resources available. This applies to io, memory, and 1569 * prefetchable memory. 1570 */ 1571 /* io range */ 1572 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1573 io_range[0] = ((val & 0xf0) << 8); 1574 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1575 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1576 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1577 memlist_insert(&pci_bus_res[secbus].io_ports, 1578 (uint64_t)io_range[0], 1579 (uint64_t)(io_range[1] - io_range[0] + 1)); 1580 if (pci_bus_res[bus].io_ports != NULL) { 1581 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1582 (uint64_t)io_range[0], 1583 (uint64_t)(io_range[1] - io_range[0] + 1)); 1584 } 1585 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1586 secbus, io_range[0], io_range[1]); 1587 /* if 32-bit supported, make sure upper bits are not set */ 1588 if ((val & 0xf) == 1 && 1589 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1590 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1591 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1592 } 1593 } 1594 1595 /* mem range */ 1596 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1597 mem_range[0] = ((val & 0xFFF0) << 16); 1598 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1599 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1600 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1601 memlist_insert(&pci_bus_res[secbus].mem_space, 1602 (uint64_t)mem_range[0], 1603 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1604 /* remove from parent resouce list */ 1605 if (pci_bus_res[bus].mem_space != NULL) { 1606 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1607 (uint64_t)mem_range[0], 1608 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1609 } 1610 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1611 secbus, mem_range[0], mem_range[1]); 1612 } 1613 1614 /* prefetchable memory range */ 1615 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1616 pmem_range[0] = ((val & 0xFFF0) << 16); 1617 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1618 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1619 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1620 memlist_insert(&pci_bus_res[secbus].pmem_space, 1621 (uint64_t)pmem_range[0], 1622 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1623 if (pci_bus_res[bus].pmem_space != NULL) { 1624 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1625 (uint64_t)pmem_range[0], 1626 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1627 } 1628 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1629 secbus, pmem_range[0], pmem_range[1]); 1630 /* if 64-bit supported, make sure upper bits are not set */ 1631 if ((val & 0xf) == 1 && 1632 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1633 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1634 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1635 } 1636 } 1637 1638 add_bus_range_prop(secbus); 1639 add_ppb_ranges_prop(secbus); 1640 } 1641 1642 extern const struct pci_class_strings_s class_pci[]; 1643 extern int class_pci_items; 1644 1645 static void 1646 add_model_prop(dev_info_t *dip, uint_t classcode) 1647 { 1648 const char *desc; 1649 int i; 1650 uchar_t baseclass = classcode >> 16; 1651 uchar_t subclass = (classcode >> 8) & 0xff; 1652 uchar_t progclass = classcode & 0xff; 1653 1654 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1655 desc = "IDE controller"; 1656 } else { 1657 for (desc = 0, i = 0; i < class_pci_items; i++) { 1658 if ((baseclass == class_pci[i].base_class) && 1659 (subclass == class_pci[i].sub_class) && 1660 (progclass == class_pci[i].prog_class)) { 1661 desc = class_pci[i].actual_desc; 1662 break; 1663 } 1664 } 1665 if (i == class_pci_items) 1666 desc = "Unknown class of pci/pnpbios device"; 1667 } 1668 1669 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1670 (char *)desc); 1671 } 1672 1673 static void 1674 add_bus_range_prop(int bus) 1675 { 1676 int bus_range[2]; 1677 1678 if (pci_bus_res[bus].dip == NULL) 1679 return; 1680 bus_range[0] = bus; 1681 bus_range[1] = pci_bus_res[bus].sub_bus; 1682 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1683 "bus-range", (int *)bus_range, 2); 1684 } 1685 1686 /* 1687 * Add slot-names property for any named pci hot-plug slots 1688 */ 1689 static void 1690 add_bus_slot_names_prop(int bus) 1691 { 1692 char slotprop[256]; 1693 int len; 1694 1695 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1696 if (len > 0) { 1697 /* 1698 * Only create a peer bus node if this bus may be a peer bus. 1699 * It may be a peer bus if the dip is NULL and if par_bus is 1700 * -1 (par_bus is -1 if this bus was not found to be 1701 * subordinate to any PCI-PCI bridge). 1702 * If it's not a peer bus, then the ACPI BBN-handling code 1703 * will remove it later. 1704 */ 1705 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 1706 pci_bus_res[bus].dip == NULL) { 1707 1708 create_root_bus_dip(bus); 1709 } 1710 if (pci_bus_res[bus].dip != NULL) { 1711 ASSERT((len % sizeof (int)) == 0); 1712 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1713 pci_bus_res[bus].dip, "slot-names", 1714 (int *)slotprop, len / sizeof (int)); 1715 } else { 1716 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 1717 "IRQ routing table; Not adding slot-names " 1718 "property for incorrect bus %d", bus); 1719 } 1720 } 1721 } 1722 1723 static int 1724 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1725 { 1726 if (entry == NULL) 1727 return (0); 1728 1729 /* assume 32-bit addresses */ 1730 rp->child_high = rp->parent_high = type; 1731 rp->child_mid = rp->parent_mid = 0; 1732 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1733 rp->size_high = 0; 1734 rp->size_low = (uint32_t)entry->size; 1735 return (1); 1736 } 1737 1738 static void 1739 add_ppb_ranges_prop(int bus) 1740 { 1741 int i = 0; 1742 ppb_ranges_t *rp; 1743 1744 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1745 1746 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1747 PCI_ADDR_IO | PCI_REG_REL_M); 1748 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1749 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1750 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1751 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1752 1753 if (i != 0) 1754 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1755 pci_bus_res[bus].dip, "ranges", (int *)rp, 1756 i * sizeof (ppb_ranges_t) / sizeof (int)); 1757 kmem_free(rp, 3 * sizeof (*rp)); 1758 } 1759 1760 static int 1761 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1762 { 1763 int i = 0; 1764 1765 while (list) { 1766 /* assume 32-bit addresses */ 1767 sp->pci_phys_hi = type; 1768 sp->pci_phys_mid = 0; 1769 sp->pci_phys_low = (uint32_t)list->address; 1770 sp->pci_size_hi = 0; 1771 sp->pci_size_low = (uint32_t)list->size; 1772 1773 list = list->next; 1774 sp++, i++; 1775 } 1776 return (i); 1777 } 1778 1779 static void 1780 add_bus_available_prop(int bus) 1781 { 1782 int i, count; 1783 struct pci_phys_spec *sp; 1784 1785 count = memlist_count(pci_bus_res[bus].io_ports) + 1786 memlist_count(pci_bus_res[bus].mem_space) + 1787 memlist_count(pci_bus_res[bus].pmem_space); 1788 1789 if (count == 0) /* nothing available */ 1790 return; 1791 1792 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1793 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1794 PCI_ADDR_IO | PCI_REG_REL_M); 1795 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1796 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1797 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1798 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1799 ASSERT(i == count); 1800 1801 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1802 "available", (int *)sp, 1803 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1804 kmem_free(sp, count * sizeof (*sp)); 1805 } 1806 1807 static void 1808 alloc_res_array(void) 1809 { 1810 static int array_max = 0; 1811 int old_max; 1812 void *old_res; 1813 1814 if (array_max > pci_bios_nbus + 1) 1815 return; /* array is big enough */ 1816 1817 old_max = array_max; 1818 old_res = pci_bus_res; 1819 1820 if (array_max == 0) 1821 array_max = 16; /* start with a reasonable number */ 1822 1823 while (array_max < pci_bios_nbus + 1) 1824 array_max <<= 1; 1825 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1826 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1827 1828 if (old_res) { /* copy content and free old array */ 1829 bcopy(old_res, pci_bus_res, 1830 old_max * sizeof (struct pci_bus_resource)); 1831 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1832 } 1833 } 1834 1835 static void 1836 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 1837 ushort_t deviceid) 1838 { 1839 static dev_info_t *ioapicsnode = NULL; 1840 static int numioapics = 0; 1841 dev_info_t *ioapic_node; 1842 uint64_t physaddr; 1843 uint32_t lobase, hibase = 0; 1844 1845 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 1846 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 1847 1848 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 1849 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 1850 return; 1851 1852 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 1853 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 1854 1855 lobase &= PCI_BASE_M_ADDR_M; 1856 1857 physaddr = (((uint64_t)hibase) << 32) | lobase; 1858 1859 /* 1860 * Create a nexus node for all IOAPICs under the root node. 1861 */ 1862 if (ioapicsnode == NULL) { 1863 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 1864 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 1865 return; 1866 } 1867 (void) ndi_devi_online(ioapicsnode, 0); 1868 } 1869 1870 /* 1871 * Create a child node for this IOAPIC 1872 */ 1873 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 1874 DEVI_SID_NODEID, numioapics++); 1875 if (ioapic_node == NULL) { 1876 return; 1877 } 1878 1879 /* Vendor and Device ID */ 1880 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1881 IOAPICS_PROP_VENID, vendorid); 1882 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1883 IOAPICS_PROP_DEVID, deviceid); 1884 1885 /* device_type */ 1886 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 1887 "device_type", IOAPICS_DEV_TYPE); 1888 1889 /* reg */ 1890 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 1891 "reg", physaddr); 1892 } 1893