1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <io/pciex/pcie_nvidia.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 45 #define pci_getb (*pci_getb_func) 46 #define pci_getw (*pci_getw_func) 47 #define pci_getl (*pci_getl_func) 48 #define pci_putb (*pci_putb_func) 49 #define pci_putw (*pci_putw_func) 50 #define pci_putl (*pci_putl_func) 51 #define dcmn_err if (pci_boot_debug) cmn_err 52 53 #define CONFIG_INFO 0 54 #define CONFIG_UPDATE 1 55 #define CONFIG_NEW 2 56 #define CONFIG_FIX 3 57 #define COMPAT_BUFSIZE 512 58 59 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 60 #define LPC_IO_CONTROL_REG_1 0x40 61 #define AMD8111_ENABLENMI (uint8_t)0x80 62 #define VENID_AMD 0x1022 63 #define DEVID_AMD8111_LPC 0x7468 64 65 struct pci_fixundo { 66 uint8_t bus; 67 uint8_t dev; 68 uint8_t fn; 69 void (*undofn)(uint8_t, uint8_t, uint8_t); 70 struct pci_fixundo *next; 71 }; 72 73 extern int pci_bios_nbus; 74 static uchar_t max_dev_pci = 32; /* PCI standard */ 75 int pci_boot_debug = 0; 76 extern struct memlist *find_bus_res(int, int); 77 static struct pci_fixundo *undolist = NULL; 78 79 /* 80 * Module prototypes 81 */ 82 static void enumerate_bus_devs(uchar_t bus, int config_op); 83 static void create_root_bus_dip(uchar_t bus); 84 static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 85 ushort_t, int); 86 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 87 ushort_t, ushort_t, uchar_t, uint_t, int); 88 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 89 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 90 static void add_model_prop(dev_info_t *, uint_t); 91 static void add_bus_range_prop(int); 92 static void add_bus_slot_names_prop(int); 93 static void add_ppb_ranges_prop(int); 94 static void add_bus_available_prop(int); 95 static void alloc_res_array(); 96 97 extern int pci_slot_names_prop(int, char *, int); 98 99 /* set non-zero to force PCI peer-bus renumbering */ 100 int pci_bus_always_renumber = 0; 101 102 /* get the subordinate bus # for a root/peer bus */ 103 static int 104 pci_root_subbus(int bus, uchar_t *subbus) 105 { 106 ACPI_HANDLE hdl; 107 ACPI_BUFFER rb; 108 ACPI_RESOURCE *rp; 109 int rv; 110 111 if (pci_bus_res[bus].dip == NULL) { 112 /* non-used bus # */ 113 return (AE_ERROR); 114 } 115 if (acpica_find_pciobj(pci_bus_res[bus].dip, &hdl) != AE_OK) { 116 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 117 return (AE_ERROR); 118 } 119 120 rb.Length = ACPI_ALLOCATE_BUFFER; 121 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 122 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 123 return (AE_ERROR); 124 } 125 126 rv = AE_ERROR; 127 128 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 129 rp = ACPI_NEXT_RESOURCE(rp)) { 130 131 switch (rp->Type) { 132 case ACPI_RESOURCE_TYPE_ADDRESS16: 133 if (rp->Data.Address.ResourceType 134 != ACPI_BUS_NUMBER_RANGE) 135 continue; 136 *subbus = (uchar_t)rp->Data.Address16.Maximum; 137 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 138 break; 139 case ACPI_RESOURCE_TYPE_ADDRESS32: 140 if (rp->Data.Address.ResourceType 141 != ACPI_BUS_NUMBER_RANGE) 142 continue; 143 *subbus = (uchar_t)rp->Data.Address32.Maximum; 144 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 145 break; 146 case ACPI_RESOURCE_TYPE_ADDRESS64: 147 if (rp->Data.Address.ResourceType 148 != ACPI_BUS_NUMBER_RANGE) 149 continue; 150 *subbus = (uchar_t)rp->Data.Address64.Maximum; 151 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 152 break; 153 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 154 if (rp->Data.Address.ResourceType 155 != ACPI_BUS_NUMBER_RANGE) 156 continue; 157 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 158 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 159 break; 160 default: 161 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 162 continue; 163 } 164 165 /* found the bus-range resource */ 166 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 167 rv = AE_OK; 168 169 /* This breaks out of the resource scanning loop */ 170 break; 171 } 172 173 AcpiOsFree(rb.Pointer); 174 if (rv != AE_OK) 175 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 176 177 return (rv); 178 179 } 180 181 /* 182 * Enumerate all PCI devices 183 */ 184 void 185 pci_setup_tree() 186 { 187 uchar_t i, root_bus_addr = 0; 188 189 alloc_res_array(); 190 for (i = 0; i <= pci_bios_nbus; i++) { 191 pci_bus_res[i].par_bus = (uchar_t)-1; 192 pci_bus_res[i].root_addr = (uchar_t)-1; 193 pci_bus_res[i].sub_bus = i; 194 } 195 196 pci_bus_res[0].root_addr = root_bus_addr++; 197 create_root_bus_dip(0); 198 enumerate_bus_devs(0, CONFIG_INFO); 199 200 /* 201 * Now enumerate peer busses 202 * 203 * We loop till pci_bios_nbus. On most systems, there is 204 * one more bus at the high end, which implements the ISA 205 * compatibility bus. We don't care about that. 206 * 207 * Note: In the old (bootconf) enumeration, the peer bus 208 * address did not use the bus number, and there were 209 * too many peer busses created. The root_bus_addr is 210 * used to maintain the old peer bus address assignment. 211 * However, we stop enumerating phantom peers with no 212 * device below. 213 */ 214 for (i = 1; i <= pci_bios_nbus; i++) { 215 if (pci_bus_res[i].dip == NULL) { 216 pci_bus_res[i].root_addr = root_bus_addr++; 217 } 218 enumerate_bus_devs(i, CONFIG_INFO); 219 220 /* add slot-names property for named pci hot-plug slots */ 221 add_bus_slot_names_prop(i); 222 } 223 224 } 225 226 /* 227 * >0 = present, 0 = not present, <0 = error 228 */ 229 static int 230 pci_bbn_present(int bus) 231 { 232 ACPI_HANDLE hdl; 233 ACPI_BUFFER rb; 234 int rv; 235 236 /* no dip means no _BBN */ 237 if (pci_bus_res[bus].dip == NULL) 238 return (0); 239 240 rv = acpica_find_pciobj(pci_bus_res[bus].dip, &hdl); 241 if (rv != AE_OK) 242 return (-1); 243 244 rb.Length = ACPI_ALLOCATE_BUFFER; 245 246 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 247 248 if (rb.Length > 0) 249 AcpiOsFree(rb.Pointer); 250 251 if (rv == AE_OK) 252 return (1); 253 else if (rv == AE_NOT_FOUND) 254 return (0); 255 else 256 return (-1); 257 } 258 259 /* 260 * Return non-zero if any PCI bus in the system has an associated 261 * _BBN object, 0 otherwise. 262 */ 263 static int 264 pci_roots_have_bbn(void) 265 { 266 int i; 267 268 /* 269 * Scan the PCI busses and look for at least 1 _BBN 270 */ 271 for (i = 0; i <= pci_bios_nbus; i++) { 272 /* skip non-root (peer) PCI busses */ 273 if (pci_bus_res[i].par_bus != (uchar_t)-1) 274 continue; 275 276 if (pci_bbn_present(i) > 0) 277 return (1); 278 } 279 return (0); 280 281 } 282 283 /* 284 * return non-zero if the machine is one on which we renumber 285 * the internal pci unit-addresses 286 */ 287 static int 288 pci_bus_renumber() 289 { 290 ACPI_TABLE_HEADER *fadt; 291 292 if (pci_bus_always_renumber) 293 return (1); 294 295 /* get the FADT */ 296 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 297 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 298 return (0); 299 300 /* compare OEM Table ID to "SUNm31" */ 301 if (strncmp("SUNm31", fadt->OemId, 6)) 302 return (0); 303 else 304 return (1); 305 } 306 307 /* 308 * Initial enumeration of the physical PCI bus hierarchy can 309 * leave 'gaps' in the order of peer PCI bus unit-addresses. 310 * Systems with more than one peer PCI bus *must* have an ACPI 311 * _BBN object associated with each peer bus; use the presence 312 * of this object to remove gaps in the numbering of the peer 313 * PCI bus unit-addresses - only peer busses with an associated 314 * _BBN are counted. 315 */ 316 static void 317 pci_renumber_root_busses(void) 318 { 319 int pci_regs[] = {0, 0, 0}; 320 int i, root_addr = 0; 321 322 /* 323 * Currently, we only enable the re-numbering on specific 324 * Sun machines; this is a work-around for the more complicated 325 * issue of upgrade changing physical device paths 326 */ 327 if (!pci_bus_renumber()) 328 return; 329 330 /* 331 * If we find no _BBN objects at all, we either don't need 332 * to do anything or can't do anything anyway 333 */ 334 if (!pci_roots_have_bbn()) 335 return; 336 337 for (i = 0; i <= pci_bios_nbus; i++) { 338 /* skip non-root (peer) PCI busses */ 339 if (pci_bus_res[i].par_bus != (uchar_t)-1) 340 continue; 341 342 if (pci_bbn_present(i) < 1) { 343 pci_bus_res[i].root_addr = (uchar_t)-1; 344 continue; 345 } 346 347 ASSERT(pci_bus_res[i].dip != NULL); 348 if (pci_bus_res[i].root_addr != root_addr) { 349 /* update reg property for node */ 350 pci_bus_res[i].root_addr = root_addr; 351 pci_regs[0] = pci_bus_res[i].root_addr; 352 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 353 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 354 } 355 root_addr++; 356 } 357 } 358 359 static void 360 remove_resource_range(struct memlist **list, int *ranges, int range_count) 361 { 362 struct range { 363 uint32_t base; 364 uint32_t len; 365 }; 366 int index; 367 368 for (index = 0; index < range_count; index++) { 369 /* all done if list is or has become empty */ 370 if (*list == NULL) 371 break; 372 (void) memlist_remove(list, 373 (uint64_t)((struct range *)ranges)[index].base, 374 (uint64_t)((struct range *)ranges)[index].len); 375 } 376 } 377 378 static void 379 remove_used_resources() 380 { 381 dev_info_t *used; 382 int *narray; 383 uint_t ncount; 384 int status; 385 int bus; 386 387 used = ddi_find_devinfo("used-resources", -1, 0); 388 if (used == NULL) 389 return; 390 391 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 392 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 393 if (status == DDI_PROP_SUCCESS) { 394 for (bus = 0; bus <= pci_bios_nbus; bus++) 395 remove_resource_range(&pci_bus_res[bus].io_ports, 396 narray, ncount / 2); 397 ddi_prop_free(narray); 398 } 399 400 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 401 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 402 if (status == DDI_PROP_SUCCESS) { 403 for (bus = 0; bus <= pci_bios_nbus; bus++) 404 remove_resource_range(&pci_bus_res[bus].mem_space, 405 narray, ncount / 2); 406 ddi_prop_free(narray); 407 } 408 } 409 410 void 411 pci_reprogram(void) 412 { 413 int i, pci_reconfig = 1; 414 char *onoff; 415 416 /* 417 * Excise phantom roots if possible 418 */ 419 pci_renumber_root_busses(); 420 421 /* add bus-range property for root/peer bus nodes */ 422 for (i = 0; i <= pci_bios_nbus; i++) { 423 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 424 uchar_t subbus; 425 if (pci_root_subbus(i, &subbus) == AE_OK) 426 pci_bus_res[i].sub_bus = subbus; 427 add_bus_range_prop(i); 428 } 429 } 430 431 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 432 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 433 if (strcmp(onoff, "off") == 0) { 434 pci_reconfig = 0; 435 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 436 } 437 ddi_prop_free(onoff); 438 } 439 440 /* remove used-resources from PCI resource maps */ 441 remove_used_resources(); 442 443 for (i = 0; i <= pci_bios_nbus; i++) { 444 /* configure devices not configured by bios */ 445 if (pci_reconfig) 446 enumerate_bus_devs(i, CONFIG_NEW); 447 /* All dev programmed, so we can create available prop */ 448 add_bus_available_prop(i); 449 } 450 } 451 452 /* 453 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 454 */ 455 static void 456 create_root_bus_dip(uchar_t bus) 457 { 458 int pci_regs[] = {0, 0, 0}; 459 dev_info_t *dip; 460 461 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 462 463 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 464 (pnode_t)DEVI_SID_NODEID, &dip); 465 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 466 "#address-cells", 3); 467 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 468 "#size-cells", 2); 469 pci_regs[0] = pci_bus_res[bus].root_addr; 470 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 471 "reg", (int *)pci_regs, 3); 472 473 /* 474 * If system has PCIe bus, then create different properties 475 */ 476 if (create_pcie_root_bus(bus, dip) == B_FALSE) 477 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 478 "device_type", "pci"); 479 480 (void) ndi_devi_bind_driver(dip, 0); 481 pci_bus_res[bus].dip = dip; 482 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 483 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 484 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 485 486 if (bus != 0) 487 return; 488 489 /* 490 * Special treatment of bus 0: 491 * If no resource from MPSPEC/HRT, copy pcimem from boot 492 * and make I/O space the entire range starting at 0x100. There 493 * is no difference between prefetchable memory or not. 494 */ 495 if (pci_bus_res[0].mem_space == NULL) 496 pci_bus_res[0].mem_space = 497 memlist_dup(bootops->boot_mem->pcimem); 498 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 499 if (pci_bus_res[0].io_ports == NULL) 500 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xff00); 501 } 502 503 /* 504 * For any fixed configuration (often compatability) pci devices 505 * and those with their own expansion rom, create device nodes 506 * to hold the already configured device details. 507 */ 508 void 509 enumerate_bus_devs(uchar_t bus, int config_op) 510 { 511 uchar_t dev, func, nfunc, header; 512 ushort_t venid; 513 dev_info_t *dip; 514 struct pci_devfunc { 515 struct pci_devfunc *next; 516 dev_info_t *dip; 517 uchar_t bus; 518 uchar_t dev; 519 uchar_t func; 520 } *devlist = NULL, *entry; 521 522 if (config_op == CONFIG_NEW) { 523 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 524 } else if (config_op == CONFIG_FIX) { 525 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 526 } else 527 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 528 529 for (dev = 0; dev < max_dev_pci; dev++) { 530 nfunc = 1; 531 for (func = 0; func < nfunc; func++) { 532 533 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 534 dev, func); 535 536 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 537 538 if ((venid == 0xffff) || (venid == 0)) { 539 /* no function at this address */ 540 continue; 541 } 542 543 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 544 if (header == 0xff) { 545 continue; /* illegal value */ 546 } 547 548 /* 549 * according to some mail from Microsoft posted 550 * to the pci-drivers alias, their only requirement 551 * for a multifunction device is for the 1st 552 * function to have to PCI_HEADER_MULTI bit set. 553 */ 554 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 555 nfunc = 8; 556 } 557 558 if (config_op == CONFIG_FIX) { 559 /* 560 * If we're processing PCI fixes, no dip 561 * will be returned. 562 */ 563 (void) process_devfunc(bus, dev, func, header, 564 venid, config_op); 565 566 } else if (config_op == CONFIG_INFO) { 567 /* 568 * Create the node, unconditionally, on the 569 * first pass only. It may still need 570 * resource assignment, which will be 571 * done on the second, CONFIG_NEW, pass. 572 */ 573 dip = process_devfunc(bus, dev, func, header, 574 venid, config_op); 575 /* 576 * If dip isn't null, put on a list to 577 * save for reprogramming when config_op 578 * is CONFIG_NEW. 579 */ 580 581 if (dip) { 582 entry = kmem_alloc(sizeof (*entry), 583 KM_SLEEP); 584 entry->dip = dip; 585 entry->dev = dev; 586 entry->func = func; 587 entry->next = devlist; 588 devlist = entry; 589 } 590 } 591 } 592 } 593 594 if (config_op == CONFIG_NEW) { 595 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 596 while (devlist) { 597 entry = devlist; 598 devlist = entry->next; 599 cmn_err(CE_NOTE, 600 "!reprogram pci device [%d/%d/%d] (%s)", 601 bus, entry->dev, entry->func, 602 ddi_driver_name(entry->dip)); 603 (void) add_reg_props(entry->dip, bus, entry->dev, 604 entry->func, CONFIG_UPDATE, 0); 605 kmem_free(entry, sizeof (*entry)); 606 } 607 pci_bus_res[bus].privdata = NULL; 608 } else if (config_op != CONFIG_FIX) { 609 pci_bus_res[bus].privdata = devlist; 610 } 611 } 612 613 static int 614 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 615 ushort_t subvenid, ushort_t subdevid) 616 { 617 static int prop_exist = -1; 618 static char *pciide_str; 619 char compat[32]; 620 621 if (prop_exist == -1) { 622 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 623 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 624 &pciide_str) == DDI_SUCCESS); 625 } 626 627 if (!prop_exist) 628 return (0); 629 630 /* compare property value against various forms of compatible */ 631 if (subvenid) { 632 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 633 venid, devid, subvenid, subdevid, revid); 634 if (strcmp(pciide_str, compat) == 0) 635 return (1); 636 637 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 638 venid, devid, subvenid, subdevid); 639 if (strcmp(pciide_str, compat) == 0) 640 return (1); 641 642 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 643 subvenid, subdevid); 644 if (strcmp(pciide_str, compat) == 0) 645 return (1); 646 } 647 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 648 venid, devid, revid); 649 if (strcmp(pciide_str, compat) == 0) 650 return (1); 651 652 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 653 if (strcmp(pciide_str, compat) == 0) 654 return (1); 655 656 return (0); 657 } 658 659 static int 660 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 661 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 662 { 663 struct ide_table { /* table for PCI_MASS_OTHER */ 664 ushort_t venid; 665 ushort_t devid; 666 } *entry; 667 668 /* XXX SATA devices: need a way to add dynamically */ 669 static struct ide_table ide_other[] = { 670 {0x1095, 0x3112}, 671 {0x1095, 0x3114}, 672 {0x1095, 0x3512}, 673 {0, 0} 674 }; 675 676 if (basecl != PCI_CLASS_MASS) 677 return (0); 678 679 if (subcl == PCI_MASS_IDE) { 680 return (1); 681 } 682 683 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 684 return (0); 685 } 686 687 entry = &ide_other[0]; 688 while (entry->venid) { 689 if (entry->venid == venid && entry->devid == devid) 690 return (1); 691 entry++; 692 } 693 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 694 } 695 696 static int 697 is_display(uint_t classcode) 698 { 699 static uint_t disp_classes[] = { 700 0x000100, 701 0x030000, 702 0x030001 703 }; 704 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 705 706 for (i = 0; i < nclasses; i++) { 707 if (classcode == disp_classes[i]) 708 return (1); 709 } 710 return (0); 711 } 712 713 static void 714 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 715 void (*undofn)(uint8_t, uint8_t, uint8_t)) 716 { 717 struct pci_fixundo *newundo; 718 719 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 720 721 /* 722 * Adding an item to this list means that we must turn its NMIENABLE 723 * bit back on at a later time. 724 */ 725 newundo->bus = bus; 726 newundo->dev = dev; 727 newundo->fn = fn; 728 newundo->undofn = undofn; 729 newundo->next = undolist; 730 731 /* add to the undo list in LIFO order */ 732 undolist = newundo; 733 } 734 735 void 736 add_pci_fixes(void) 737 { 738 int i; 739 740 for (i = 0; i <= pci_bios_nbus; i++) { 741 /* 742 * For each bus, apply needed fixes to the appropriate devices. 743 * This must be done before the main enumeration loop because 744 * some fixes must be applied to devices normally encountered 745 * later in the pci scan (e.g. if a fix to device 7 must be 746 * applied before scanning device 6, applying fixes in the 747 * normal enumeration loop would obviously be too late). 748 */ 749 enumerate_bus_devs(i, CONFIG_FIX); 750 } 751 } 752 753 void 754 undo_pci_fixes(void) 755 { 756 struct pci_fixundo *nextundo; 757 uint8_t bus, dev, fn; 758 759 /* 760 * All fixes in the undo list are performed unconditionally. Future 761 * fixes may require selective undo. 762 */ 763 while (undolist != NULL) { 764 765 bus = undolist->bus; 766 dev = undolist->dev; 767 fn = undolist->fn; 768 769 (*(undolist->undofn))(bus, dev, fn); 770 771 nextundo = undolist->next; 772 kmem_free(undolist, sizeof (struct pci_fixundo)); 773 undolist = nextundo; 774 } 775 } 776 777 static void 778 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 779 { 780 uint8_t val8; 781 782 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 783 /* 784 * The NMIONERR bit is turned back on to allow the SMM BIOS 785 * to handle more critical PCI errors (e.g. PERR#). 786 */ 787 val8 |= AMD8111_ENABLENMI; 788 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 789 } 790 791 static void 792 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 793 { 794 uint8_t val8; 795 796 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 797 798 if ((val8 & AMD8111_ENABLENMI) == 0) 799 return; 800 801 /* 802 * We reset NMIONERR in the LPC because master-abort on the PCI 803 * bridge side of the 8111 will cause NMI, which might cause SMI, 804 * which sometimes prevents all devices from being enumerated. 805 */ 806 val8 &= ~AMD8111_ENABLENMI; 807 808 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 809 810 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 811 } 812 813 static dev_info_t * 814 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 815 ushort_t vendorid, int config_op) 816 { 817 char nodename[32], unitaddr[5]; 818 dev_info_t *dip; 819 uchar_t basecl, subcl, intr, revid; 820 ushort_t subvenid, subdevid, status; 821 ushort_t slot_num; 822 uint_t classcode, revclass; 823 int reprogram = 0, pciide; 824 int power[2] = {1, 1}; 825 int pciex = 0; 826 ushort_t is_pci_bridge = 0; 827 828 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 829 830 switch (header & PCI_HEADER_TYPE_M) { 831 case PCI_HEADER_ZERO: 832 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 833 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 834 break; 835 case PCI_HEADER_CARDBUS: 836 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 837 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 838 break; 839 default: 840 subvenid = 0; 841 subdevid = 0; 842 break; 843 } 844 845 if (config_op == CONFIG_FIX) { 846 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 847 pci_fix_amd8111(bus, dev, func); 848 } 849 return (NULL); 850 } 851 852 /* XXX should be use generic names? derive from class? */ 853 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 854 classcode = revclass >> 8; 855 revid = revclass & 0xff; 856 857 /* figure out if this is pci-ide */ 858 basecl = classcode >> 16; 859 subcl = (classcode >> 8) & 0xff; 860 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 861 subvenid, subdevid); 862 863 if (pciide) 864 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 865 else if (is_display(classcode)) 866 (void) snprintf(nodename, sizeof (nodename), "display"); 867 else if (subvenid != 0) 868 (void) snprintf(nodename, sizeof (nodename), 869 "pci%x,%x", subvenid, subdevid); 870 else 871 (void) snprintf(nodename, sizeof (nodename), 872 "pci%x,%x", vendorid, deviceid); 873 874 /* make sure parent bus dip has been created */ 875 if (pci_bus_res[bus].dip == NULL) { 876 create_root_bus_dip(bus); 877 } 878 879 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 880 DEVI_SID_NODEID, &dip); 881 882 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 883 &is_pci_bridge) == B_TRUE) 884 pciex = 1; 885 886 /* add properties */ 887 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 888 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 889 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 890 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 891 "class-code", classcode); 892 if (func == 0) 893 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 894 else 895 (void) snprintf(unitaddr, sizeof (unitaddr), 896 "%x,%x", dev, func); 897 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 898 "unit-address", unitaddr); 899 900 /* add device_type for display nodes */ 901 if (is_display(classcode)) { 902 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 903 "device_type", "display"); 904 } 905 /* add special stuff for header type */ 906 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 907 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 908 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 909 910 if (subvenid != 0) { 911 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 912 "subsystem-id", subdevid); 913 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 914 "subsystem-vendor-id", subvenid); 915 } 916 if (!pciex) 917 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 918 "min-grant", mingrant); 919 if (!pciex) 920 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 921 "max-latency", maxlatency); 922 } 923 924 /* interrupt, record if not 0 */ 925 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 926 if (intr != 0) 927 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 928 "interrupts", intr); 929 930 /* 931 * Add support for 133 mhz pci eventually 932 */ 933 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 934 935 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 936 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 937 if (!pciex && (status & PCI_STAT_FBBC)) 938 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 939 "fast-back-to-back"); 940 if (!pciex && (status & PCI_STAT_66MHZ)) 941 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 942 "66mhz-capable"); 943 if (status & PCI_STAT_UDF) 944 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 945 "udf-supported"); 946 if (pciex && slot_num) 947 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 948 "physical-slot#", slot_num); 949 950 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 951 "power-consumption", power, 2); 952 953 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 954 add_ppb_props(dip, bus, dev, func, pciex); 955 956 /* check for ck8-04 based PCI ISA bridge only */ 957 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 958 (func == 0)) 959 add_nvidia_isa_bridge_props(dip, bus, dev, func); 960 961 if (pciex && is_pci_bridge) 962 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 963 (char *)"PCIe-PCI bridge"); 964 else 965 add_model_prop(dip, classcode); 966 967 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 968 revid, classcode, pciex); 969 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 970 (void) ndi_devi_bind_driver(dip, 0); 971 972 /* special handling for pci-ide */ 973 if (pciide) { 974 dev_info_t *cdip; 975 976 /* 977 * Create properties specified by P1275 Working Group 978 * Proposal #414 Version 1 979 */ 980 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 981 "device_type", "pci-ide"); 982 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 983 "#address-cells", 1); 984 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 985 "#size-cells", 0); 986 987 /* allocate two child nodes */ 988 ndi_devi_alloc_sleep(dip, "ide", 989 (pnode_t)DEVI_SID_NODEID, &cdip); 990 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 991 "reg", 0); 992 (void) ndi_devi_bind_driver(cdip, 0); 993 ndi_devi_alloc_sleep(dip, "ide", 994 (pnode_t)DEVI_SID_NODEID, &cdip); 995 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 996 "reg", 1); 997 (void) ndi_devi_bind_driver(cdip, 0); 998 999 reprogram = 0; /* don't reprogram pci-ide bridge */ 1000 } 1001 1002 1003 if (reprogram) 1004 return (dip); 1005 return (NULL); 1006 } 1007 1008 /* 1009 * Set the compatible property to a value compliant with 1010 * rev 2.1 of the IEEE1275 PCI binding. 1011 * (Also used for PCI-Express devices). 1012 * 1013 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1014 * pciVVVV,DDDD.SSSS.ssss (1) 1015 * pciSSSS,ssss (2) 1016 * pciVVVV,DDDD.RR (3) 1017 * pciVVVV,DDDD (4) 1018 * pciclass,CCSSPP (5) 1019 * pciclass,CCSS (6) 1020 * 1021 * The Subsystem (SSSS) forms are not inserted if 1022 * subsystem-vendor-id is 0. 1023 * 1024 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1025 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1026 * 1027 * Set with setprop and \x00 between each 1028 * to generate the encoded string array form. 1029 */ 1030 void 1031 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1032 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1033 int pciex) 1034 { 1035 int i = 0; 1036 int size = COMPAT_BUFSIZE; 1037 char *compat[13]; 1038 char *buf, *curr; 1039 1040 curr = buf = kmem_alloc(size, KM_SLEEP); 1041 1042 if (pciex) { 1043 if (subvenid) { 1044 compat[i++] = curr; /* form 0 */ 1045 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1046 vendorid, deviceid, subvenid, subdevid, revid); 1047 size -= strlen(curr) + 1; 1048 curr += strlen(curr) + 1; 1049 1050 compat[i++] = curr; /* form 1 */ 1051 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1052 vendorid, deviceid, subvenid, subdevid); 1053 size -= strlen(curr) + 1; 1054 curr += strlen(curr) + 1; 1055 1056 } 1057 compat[i++] = curr; /* form 3 */ 1058 (void) snprintf(curr, size, "pciex%x,%x.%x", 1059 vendorid, deviceid, revid); 1060 size -= strlen(curr) + 1; 1061 curr += strlen(curr) + 1; 1062 1063 compat[i++] = curr; /* form 4 */ 1064 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1065 size -= strlen(curr) + 1; 1066 curr += strlen(curr) + 1; 1067 1068 compat[i++] = curr; /* form 5 */ 1069 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1070 size -= strlen(curr) + 1; 1071 curr += strlen(curr) + 1; 1072 1073 compat[i++] = curr; /* form 6 */ 1074 (void) snprintf(curr, size, "pciexclass,%04x", 1075 (classcode >> 8)); 1076 size -= strlen(curr) + 1; 1077 curr += strlen(curr) + 1; 1078 } 1079 1080 if (subvenid) { 1081 compat[i++] = curr; /* form 0 */ 1082 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1083 vendorid, deviceid, subvenid, subdevid, revid); 1084 size -= strlen(curr) + 1; 1085 curr += strlen(curr) + 1; 1086 1087 compat[i++] = curr; /* form 1 */ 1088 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1089 vendorid, deviceid, subvenid, subdevid); 1090 size -= strlen(curr) + 1; 1091 curr += strlen(curr) + 1; 1092 1093 compat[i++] = curr; /* form 2 */ 1094 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1095 size -= strlen(curr) + 1; 1096 curr += strlen(curr) + 1; 1097 } 1098 compat[i++] = curr; /* form 3 */ 1099 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1100 size -= strlen(curr) + 1; 1101 curr += strlen(curr) + 1; 1102 1103 compat[i++] = curr; /* form 4 */ 1104 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1105 size -= strlen(curr) + 1; 1106 curr += strlen(curr) + 1; 1107 1108 compat[i++] = curr; /* form 5 */ 1109 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1110 size -= strlen(curr) + 1; 1111 curr += strlen(curr) + 1; 1112 1113 compat[i++] = curr; /* form 6 */ 1114 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1115 size -= strlen(curr) + 1; 1116 curr += strlen(curr) + 1; 1117 1118 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1119 "compatible", compat, i); 1120 kmem_free(buf, COMPAT_BUFSIZE); 1121 } 1122 1123 /* 1124 * Adjust the reg properties for a dual channel PCI-IDE device. 1125 * 1126 * NOTE: don't do anything that changes the order of the hard-decodes 1127 * and programmed BARs. The kernel driver depends on these values 1128 * being in this order regardless of whether they're for a 'native' 1129 * mode BAR or not. 1130 */ 1131 /* 1132 * config info for pci-ide devices 1133 */ 1134 static struct { 1135 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1136 uchar_t bar_offset; /* offset for alt status register */ 1137 ushort_t addr; /* compatibility mode base address */ 1138 ushort_t length; /* number of ports for this BAR */ 1139 } pciide_bar[] = { 1140 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1141 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1142 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1143 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1144 }; 1145 1146 static int 1147 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1148 { 1149 int hard_decode = 0; 1150 1151 /* 1152 * Adjust the base and len for the BARs of the PCI-IDE 1153 * device's primary and secondary controllers. The first 1154 * two BARs are for the primary controller and the next 1155 * two BARs are for the secondary controller. The fifth 1156 * and sixth bars are never adjusted. 1157 */ 1158 if (index >= 0 && index <= 3) { 1159 *lenp = pciide_bar[index].length; 1160 1161 if (progcl & pciide_bar[index].native_mask) { 1162 *basep += pciide_bar[index].bar_offset; 1163 } else { 1164 *basep = pciide_bar[index].addr; 1165 hard_decode = 1; 1166 } 1167 } 1168 1169 /* 1170 * if either base or len is zero make certain both are zero 1171 */ 1172 if (*basep == 0 || *lenp == 0) { 1173 *basep = 0; 1174 *lenp = 0; 1175 hard_decode = 0; 1176 } 1177 1178 return (hard_decode); 1179 } 1180 1181 1182 /* 1183 * Add the "reg" and "assigned-addresses" property 1184 */ 1185 static int 1186 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1187 int config_op, int pciide) 1188 { 1189 uchar_t baseclass, subclass, progclass, header; 1190 ushort_t bar_sz; 1191 uint_t value = 0, len, devloc; 1192 uint_t base, base_hi, type; 1193 ushort_t offset, end; 1194 int max_basereg, j, reprogram = 0; 1195 uint_t phys_hi; 1196 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1197 uint16_t cmd_reg; 1198 1199 pci_regspec_t regs[16] = {{0}}; 1200 pci_regspec_t assigned[15] = {{0}}; 1201 int nreg, nasgn, enable = 0; 1202 1203 io_res = &pci_bus_res[bus].io_ports; 1204 mem_res = &pci_bus_res[bus].mem_space; 1205 if (bus == 0) /* for bus 0, there is only mem_space */ 1206 pmem_res = mem_res; 1207 else 1208 pmem_res = &pci_bus_res[bus].pmem_space; 1209 1210 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1211 regs[0].pci_phys_hi = devloc; 1212 nreg = 1; /* rest of regs[0] is all zero */ 1213 nasgn = 0; 1214 1215 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1216 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1217 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1218 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1219 1220 switch (header) { 1221 case PCI_HEADER_ZERO: 1222 max_basereg = PCI_BASE_NUM; 1223 break; 1224 case PCI_HEADER_PPB: 1225 max_basereg = PCI_BCNF_BASE_NUM; 1226 break; 1227 case PCI_HEADER_CARDBUS: 1228 max_basereg = PCI_CBUS_BASE_NUM; 1229 break; 1230 default: 1231 max_basereg = 0; 1232 break; 1233 } 1234 1235 /* 1236 * Create the register property by saving the current 1237 * value of the base register. Write 0xffffffff to the 1238 * base register. Read the value back to determine the 1239 * required size of the address space. Restore the base 1240 * register contents. 1241 * 1242 * Do not disable I/O and memory access; this isn't necessary 1243 * since no driver is yet attached to this device, and disabling 1244 * I/O and memory access has the side-effect of disabling PCI-PCI 1245 * bridge mappings, which makes the bridge transparent to secondary- 1246 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1247 * Spec V1.2). 1248 */ 1249 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1250 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1251 j++, offset += bar_sz) { 1252 int hard_decode = 0; 1253 1254 /* determine the size of the address space */ 1255 base = pci_getl(bus, dev, func, offset); 1256 pci_putl(bus, dev, func, offset, 0xffffffff); 1257 value = pci_getl(bus, dev, func, offset); 1258 pci_putl(bus, dev, func, offset, base); 1259 1260 /* construct phys hi,med.lo, size hi, lo */ 1261 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1262 /* i/o space */ 1263 bar_sz = PCI_BAR_SZ_32; 1264 value &= PCI_BASE_IO_ADDR_M; 1265 len = ((value ^ (value-1)) + 1) >> 1; 1266 1267 /* XXX Adjust first 4 IDE registers */ 1268 if (pciide) { 1269 if (subclass != PCI_MASS_IDE) 1270 progclass = (PCI_IDE_IF_NATIVE_PRI | 1271 PCI_IDE_IF_NATIVE_SEC); 1272 hard_decode = pciIdeAdjustBAR(progclass, j, 1273 &base, &len); 1274 } else if (value == 0) { 1275 /* skip base regs with size of 0 */ 1276 continue; 1277 } 1278 1279 regs[nreg].pci_size_low = 1280 assigned[nasgn].pci_size_low = len; 1281 if (!hard_decode) { 1282 regs[nreg].pci_phys_hi = 1283 (PCI_ADDR_IO | devloc) + offset; 1284 } else { 1285 regs[nreg].pci_phys_hi = 1286 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1287 offset; 1288 regs[nreg].pci_phys_low = 1289 base & PCI_BASE_IO_ADDR_M; 1290 } 1291 assigned[nasgn].pci_phys_hi = 1292 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1293 type = base & (~PCI_BASE_IO_ADDR_M); 1294 base &= PCI_BASE_IO_ADDR_M; 1295 1296 /* 1297 * first pass - gather what's there 1298 * update/second pass - adjust/allocate regions 1299 * config - allocate regions 1300 */ 1301 if (config_op == CONFIG_INFO) { /* first pass */ 1302 /* take out of the resource map of the bus */ 1303 if (*io_res && base != 0) 1304 (void) memlist_remove(io_res, 1305 (uint64_t)base, (uint64_t)len); 1306 else if (*io_res) 1307 reprogram = 1; 1308 } else if (*io_res && base == 0) { 1309 base = (uint_t)memlist_find(io_res, 1310 (uint64_t)len, (uint64_t)0x4); 1311 if (base != 0) { 1312 /* XXX need to worry about 64-bit? */ 1313 pci_putl(bus, dev, func, offset, 1314 base | type); 1315 base = pci_getl(bus, dev, func, offset); 1316 base &= PCI_BASE_IO_ADDR_M; 1317 } 1318 if (base == 0) { 1319 cmn_err(CE_WARN, "failed to program" 1320 " IO space [%d/%d/%d] BAR@0x%x" 1321 " length 0x%x", 1322 bus, dev, func, offset, len); 1323 } else 1324 enable |= PCI_COMM_IO; 1325 } 1326 assigned[nasgn].pci_phys_low = base; 1327 nreg++, nasgn++; 1328 1329 } else { 1330 /* memory space */ 1331 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1332 bar_sz = PCI_BAR_SZ_64; 1333 base_hi = pci_getl(bus, dev, func, offset + 4); 1334 phys_hi = PCI_ADDR_MEM64; 1335 } else { 1336 bar_sz = PCI_BAR_SZ_32; 1337 base_hi = 0; 1338 phys_hi = PCI_ADDR_MEM32; 1339 } 1340 1341 /* skip base regs with size of 0 */ 1342 value &= PCI_BASE_M_ADDR_M; 1343 1344 if (value == 0) { 1345 continue; 1346 } 1347 len = ((value ^ (value-1)) + 1) >> 1; 1348 regs[nreg].pci_size_low = 1349 assigned[nasgn].pci_size_low = len; 1350 1351 phys_hi |= (devloc | offset); 1352 if (base & PCI_BASE_PREF_M) { 1353 mres = pmem_res; 1354 phys_hi |= PCI_PREFETCH_B; 1355 } else { 1356 mres = mem_res; 1357 } 1358 regs[nreg].pci_phys_hi = 1359 assigned[nasgn].pci_phys_hi = phys_hi; 1360 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1361 assigned[nasgn].pci_phys_mid = base_hi; 1362 type = base & ~PCI_BASE_M_ADDR_M; 1363 base &= PCI_BASE_M_ADDR_M; 1364 1365 if (config_op == CONFIG_INFO) { 1366 /* take out of the resource map of the bus */ 1367 if (*mres && base != 0) { 1368 (void) memlist_remove(mres, 1369 (uint64_t)base, (uint64_t)len); 1370 } else if (*mres) 1371 reprogram = 1; 1372 } else if (*mres && base == 0) { 1373 base = (uint_t)memlist_find(mres, 1374 (uint64_t)len, (uint64_t)0x1000); 1375 if (base != NULL) { 1376 pci_putl(bus, dev, func, offset, 1377 base | type); 1378 base = pci_getl(bus, dev, func, offset); 1379 base &= PCI_BASE_M_ADDR_M; 1380 } 1381 1382 if (base == 0) { 1383 cmn_err(CE_WARN, "failed to program " 1384 "mem space [%d/%d/%d] BAR@0x%x" 1385 " length 0x%x", 1386 bus, dev, func, offset, len); 1387 } else 1388 enable |= PCI_COMM_MAE; 1389 } 1390 assigned[nasgn].pci_phys_low = base; 1391 nreg++, nasgn++; 1392 } 1393 } 1394 switch (header) { 1395 case PCI_HEADER_ZERO: 1396 offset = PCI_CONF_ROM; 1397 break; 1398 case PCI_HEADER_PPB: 1399 offset = PCI_BCNF_ROM; 1400 break; 1401 default: /* including PCI_HEADER_CARDBUS */ 1402 goto done; 1403 } 1404 1405 /* 1406 * Add the expansion rom memory space 1407 * Determine the size of the ROM base reg; don't write reserved bits 1408 * ROM isn't in the PCI memory space. 1409 */ 1410 base = pci_getl(bus, dev, func, offset); 1411 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1412 value = pci_getl(bus, dev, func, offset); 1413 pci_putl(bus, dev, func, offset, base); 1414 if (value & PCI_BASE_ROM_ENABLE) 1415 value &= PCI_BASE_ROM_ADDR_M; 1416 else 1417 value = 0; 1418 1419 if (value != 0) { 1420 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1421 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1422 PCI_ADDR_MEM32 | devloc) + offset; 1423 base &= PCI_BASE_ROM_ADDR_M; 1424 assigned[nasgn].pci_phys_low = base; 1425 len = ((value ^ (value-1)) + 1) >> 1; 1426 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1427 nreg++, nasgn++; 1428 /* take it out of the memory resource */ 1429 if (*mem_res && base != 0) 1430 (void) memlist_remove(mem_res, 1431 (uint64_t)base, (uint64_t)len); 1432 } 1433 1434 /* 1435 * The following are ISA resources. There are not part 1436 * of the PCI local bus resources. So don't attempt to 1437 * do resource accounting against PCI. 1438 */ 1439 1440 /* add the three hard-decode, aliased address spaces for VGA */ 1441 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1442 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1443 1444 /* VGA hard decode 0x3b0-0x3bb */ 1445 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1446 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1447 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1448 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1449 nreg++, nasgn++; 1450 1451 /* VGA hard decode 0x3c0-0x3df */ 1452 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1453 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1454 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1455 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1456 nreg++, nasgn++; 1457 1458 /* Video memory */ 1459 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1460 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1461 regs[nreg].pci_phys_low = 1462 assigned[nasgn].pci_phys_low = 0xa0000; 1463 regs[nreg].pci_size_low = 1464 assigned[nasgn].pci_size_low = 0x20000; 1465 nreg++, nasgn++; 1466 } 1467 1468 /* add the hard-decode, aliased address spaces for 8514 */ 1469 if ((baseclass == PCI_CLASS_DISPLAY) && 1470 (subclass == PCI_DISPLAY_VGA) && 1471 (progclass & PCI_DISPLAY_IF_8514)) { 1472 1473 /* hard decode 0x2e8 */ 1474 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1475 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1476 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1477 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1478 nreg++, nasgn++; 1479 1480 /* hard decode 0x2ea-0x2ef */ 1481 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1482 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1483 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1484 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1485 nreg++, nasgn++; 1486 } 1487 1488 done: 1489 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1490 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1491 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1492 "assigned-addresses", 1493 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1494 if (config_op == CONFIG_NEW && enable) { 1495 cmn_err(CE_NOTE, 1496 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1497 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1498 cmd_reg |= (enable | PCI_COMM_ME); 1499 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1500 } 1501 return (reprogram); 1502 } 1503 1504 static void 1505 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1506 int pciex) 1507 { 1508 char *dev_type; 1509 int i; 1510 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1511 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1512 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1513 ASSERT(secbus <= subbus); 1514 1515 /* 1516 * Some BIOSes lie about max pci busses, we allow for 1517 * such mistakes here 1518 */ 1519 if (subbus > pci_bios_nbus) { 1520 pci_bios_nbus = subbus; 1521 alloc_res_array(); 1522 } 1523 1524 ASSERT(pci_bus_res[secbus].dip == NULL); 1525 pci_bus_res[secbus].dip = dip; 1526 pci_bus_res[secbus].par_bus = bus; 1527 1528 dev_type = pciex ? "pciex" : "pci"; 1529 1530 /* setup bus number hierarchy */ 1531 pci_bus_res[secbus].sub_bus = subbus; 1532 /* 1533 * Keep track of the largest subordinate bus number (this is essential 1534 * for peer busses because there is no other way of determining its 1535 * subordinate bus number). 1536 */ 1537 if (subbus > pci_bus_res[bus].sub_bus) 1538 pci_bus_res[bus].sub_bus = subbus; 1539 /* 1540 * Loop through subordinate busses, initializing their parent bus 1541 * field to this bridge's parent. The subordinate busses' parent 1542 * fields may very well be further refined later, as child bridges 1543 * are enumerated. (The value is to note that the subordinate busses 1544 * are not peer busses by changing their par_bus fields to anything 1545 * other than -1.) 1546 */ 1547 for (i = secbus + 1; i <= subbus; i++) 1548 pci_bus_res[i].par_bus = bus; 1549 1550 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1551 "device_type", dev_type); 1552 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1553 "#address-cells", 3); 1554 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1555 "#size-cells", 2); 1556 1557 /* 1558 * According to PPB spec, the base register should be programmed 1559 * with a value bigger than the limit register when there are 1560 * no resources available. This applies to io, memory, and 1561 * prefetchable memory. 1562 */ 1563 /* io range */ 1564 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1565 io_range[0] = ((val & 0xf0) << 8); 1566 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1567 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1568 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1569 memlist_insert(&pci_bus_res[secbus].io_ports, 1570 (uint64_t)io_range[0], 1571 (uint64_t)(io_range[1] - io_range[0] + 1)); 1572 if (pci_bus_res[bus].io_ports != NULL) { 1573 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1574 (uint64_t)io_range[0], 1575 (uint64_t)(io_range[1] - io_range[0] + 1)); 1576 } 1577 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1578 secbus, io_range[0], io_range[1]); 1579 /* if 32-bit supported, make sure upper bits are not set */ 1580 if ((val & 0xf) == 1 && 1581 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1582 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1583 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1584 } 1585 } 1586 1587 /* mem range */ 1588 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1589 mem_range[0] = ((val & 0xFFF0) << 16); 1590 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1591 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1592 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1593 memlist_insert(&pci_bus_res[secbus].mem_space, 1594 (uint64_t)mem_range[0], 1595 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1596 /* remove from parent resouce list */ 1597 if (pci_bus_res[bus].mem_space != NULL) { 1598 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1599 (uint64_t)mem_range[0], 1600 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1601 } 1602 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1603 secbus, mem_range[0], mem_range[1]); 1604 } 1605 1606 /* prefetchable memory range */ 1607 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1608 pmem_range[0] = ((val & 0xFFF0) << 16); 1609 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1610 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1611 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1612 memlist_insert(&pci_bus_res[secbus].pmem_space, 1613 (uint64_t)pmem_range[0], 1614 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1615 if (pci_bus_res[bus].pmem_space != NULL) { 1616 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1617 (uint64_t)pmem_range[0], 1618 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1619 } 1620 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1621 secbus, pmem_range[0], pmem_range[1]); 1622 /* if 64-bit supported, make sure upper bits are not set */ 1623 if ((val & 0xf) == 1 && 1624 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1625 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1626 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1627 } 1628 } 1629 1630 add_bus_range_prop(secbus); 1631 add_ppb_ranges_prop(secbus); 1632 } 1633 1634 extern const struct pci_class_strings_s class_pci[]; 1635 extern int class_pci_items; 1636 1637 static void 1638 add_model_prop(dev_info_t *dip, uint_t classcode) 1639 { 1640 const char *desc; 1641 int i; 1642 uchar_t baseclass = classcode >> 16; 1643 uchar_t subclass = (classcode >> 8) & 0xff; 1644 uchar_t progclass = classcode & 0xff; 1645 1646 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1647 desc = "IDE controller"; 1648 } else { 1649 for (desc = 0, i = 0; i < class_pci_items; i++) { 1650 if ((baseclass == class_pci[i].base_class) && 1651 (subclass == class_pci[i].sub_class) && 1652 (progclass == class_pci[i].prog_class)) { 1653 desc = class_pci[i].actual_desc; 1654 break; 1655 } 1656 } 1657 if (i == class_pci_items) 1658 desc = "Unknown class of pci/pnpbios device"; 1659 } 1660 1661 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1662 (char *)desc); 1663 } 1664 1665 static void 1666 add_bus_range_prop(int bus) 1667 { 1668 int bus_range[2]; 1669 1670 if (pci_bus_res[bus].dip == NULL) 1671 return; 1672 bus_range[0] = bus; 1673 bus_range[1] = pci_bus_res[bus].sub_bus; 1674 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1675 "bus-range", (int *)bus_range, 2); 1676 } 1677 1678 /* 1679 * Add slot-names property for any named pci hot-plug slots 1680 */ 1681 static void 1682 add_bus_slot_names_prop(int bus) 1683 { 1684 char slotprop[256]; 1685 int len; 1686 1687 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1688 if (len > 0) { 1689 /* 1690 * Only create a peer bus node if this bus may be a peer bus. 1691 * It may be a peer bus if the dip is NULL and if par_bus is 1692 * -1 (par_bus is -1 if this bus was not found to be 1693 * subordinate to any PCI-PCI bridge). 1694 * If it's not a peer bus, then the ACPI BBN-handling code 1695 * will remove it later. 1696 */ 1697 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 1698 pci_bus_res[bus].dip == NULL) { 1699 1700 create_root_bus_dip(bus); 1701 } 1702 if (pci_bus_res[bus].dip != NULL) { 1703 ASSERT((len % sizeof (int)) == 0); 1704 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1705 pci_bus_res[bus].dip, "slot-names", 1706 (int *)slotprop, len / sizeof (int)); 1707 } else { 1708 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 1709 "IRQ routing table; Not adding slot-names " 1710 "property for incorrect bus %d", bus); 1711 } 1712 } 1713 } 1714 1715 static int 1716 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1717 { 1718 if (entry == NULL) 1719 return (0); 1720 1721 /* assume 32-bit addresses */ 1722 rp->child_high = rp->parent_high = type; 1723 rp->child_mid = rp->parent_mid = 0; 1724 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1725 rp->size_high = 0; 1726 rp->size_low = (uint32_t)entry->size; 1727 return (1); 1728 } 1729 1730 static void 1731 add_ppb_ranges_prop(int bus) 1732 { 1733 int i = 0; 1734 ppb_ranges_t *rp; 1735 1736 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1737 1738 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1739 PCI_ADDR_IO | PCI_REG_REL_M); 1740 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1741 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1742 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1743 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1744 1745 if (i != 0) 1746 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1747 pci_bus_res[bus].dip, "ranges", (int *)rp, 1748 i * sizeof (ppb_ranges_t) / sizeof (int)); 1749 kmem_free(rp, 3 * sizeof (*rp)); 1750 } 1751 1752 static int 1753 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1754 { 1755 int i = 0; 1756 1757 while (list) { 1758 /* assume 32-bit addresses */ 1759 sp->pci_phys_hi = type; 1760 sp->pci_phys_mid = 0; 1761 sp->pci_phys_low = (uint32_t)list->address; 1762 sp->pci_size_hi = 0; 1763 sp->pci_size_low = (uint32_t)list->size; 1764 1765 list = list->next; 1766 sp++, i++; 1767 } 1768 return (i); 1769 } 1770 1771 static void 1772 add_bus_available_prop(int bus) 1773 { 1774 int i, count; 1775 struct pci_phys_spec *sp; 1776 1777 count = memlist_count(pci_bus_res[bus].io_ports) + 1778 memlist_count(pci_bus_res[bus].mem_space) + 1779 memlist_count(pci_bus_res[bus].pmem_space); 1780 1781 if (count == 0) /* nothing available */ 1782 return; 1783 1784 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1785 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1786 PCI_ADDR_IO | PCI_REG_REL_M); 1787 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1788 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1789 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1790 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1791 ASSERT(i == count); 1792 1793 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1794 "available", (int *)sp, 1795 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1796 kmem_free(sp, count * sizeof (*sp)); 1797 } 1798 1799 static void 1800 alloc_res_array(void) 1801 { 1802 static int array_max = 0; 1803 int old_max; 1804 void *old_res; 1805 1806 if (array_max > pci_bios_nbus + 1) 1807 return; /* array is big enough */ 1808 1809 old_max = array_max; 1810 old_res = pci_bus_res; 1811 1812 if (array_max == 0) 1813 array_max = 16; /* start with a reasonable number */ 1814 1815 while (array_max < pci_bios_nbus + 1) 1816 array_max <<= 1; 1817 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1818 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1819 1820 if (old_res) { /* copy content and free old array */ 1821 bcopy(old_res, pci_bus_res, 1822 old_max * sizeof (struct pci_bus_resource)); 1823 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1824 } 1825 } 1826