xref: /titanic_41/usr/src/uts/intel/io/ipmi/ipmivars.h (revision 5e989a96186a37eb528fb7bb4d28a150874ec799)
1 /*
2  * Copyright (c) 2006 IronPort Systems Inc. <ambrisko@ironport.com>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD: src/sys/dev/ipmi/ipmivars.h,v 1.3 2008/08/28 02:13:53 jhb Exp $
27  */
28 
29 /*
30  * Copyright 2012, Joyent, Inc.  All rights reserved.
31  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
32  */
33 
34 #ifndef _IPMIVARS_H_
35 #define	_IPMIVARS_H_
36 
37 #include <sys/types.h>
38 #include <sys/queue.h>
39 
40 #ifdef	__cplusplus
41 extern "C" {
42 #endif
43 
44 struct ipmi_device;
45 struct ipmi_request;
46 
47 typedef enum {
48 	IRS_ALLOCATED,
49 	IRS_QUEUED,
50 	IRS_PROCESSED,
51 	IRS_COMPLETED,
52 	IRS_CANCELED
53 } ir_status_t;
54 
55 struct ipmi_request {
56 	TAILQ_ENTRY(ipmi_request) ir_link;
57 	struct ipmi_device *ir_owner;	/* Driver uses NULL. */
58 	uchar_t		*ir_request;	/* Request is data to send to BMC. */
59 	size_t		ir_requestlen;
60 	uchar_t		*ir_reply;	/* Reply is data read from BMC. */
61 	size_t		ir_replybuflen;	/* Length of ir_reply[] buffer. */
62 	int		ir_replylen;	/* Length of reply from BMC. */
63 	int		ir_error;
64 	long		ir_msgid;
65 	uint8_t		ir_addr;
66 	uint8_t		ir_command;
67 	uint8_t		ir_compcode;
68 	int		ir_sz;		/* size of request */
69 
70 	kcondvar_t	ir_cv;
71 	ir_status_t	ir_status;
72 };
73 
74 #define	MAX_RES				3
75 #define	KCS_DATA			0
76 #define	KCS_CTL_STS			1
77 #define	SMIC_DATA			0
78 #define	SMIC_CTL_STS			1
79 #define	SMIC_FLAGS			2
80 
81 /* Per file descriptor data. */
82 typedef struct ipmi_device {
83 	TAILQ_HEAD(, ipmi_request) ipmi_completed_requests;
84 	pollhead_t		*ipmi_pollhead;
85 	int			ipmi_requests;
86 	uchar_t			ipmi_address;	/* IPMB address. */
87 	uchar_t			ipmi_lun;
88 	dev_t			ipmi_dev;
89 	list_node_t		ipmi_node;	/* list link for open devs */
90 } ipmi_device_t;
91 
92 struct ipmi_softc {
93 	int			ipmi_io_rid;
94 	int			ipmi_io_type;
95 	uint64_t		ipmi_io_address;
96 	int			ipmi_io_mode;
97 	int			ipmi_io_spacing;
98 	int			ipmi_io_irq;
99 	void			*ipmi_irq;
100 	int			ipmi_detaching;
101 	TAILQ_HEAD(, ipmi_request) ipmi_pending_requests;
102 	kmutex_t		ipmi_lock;
103 	kcondvar_t		ipmi_request_added;
104 	taskq_t			*ipmi_kthread;
105 	int			(*ipmi_startup)(struct ipmi_softc *);
106 	int			(*ipmi_enqueue_request)(struct ipmi_softc *,
107 				    struct ipmi_request *);
108 };
109 
110 #define	KCS_MODE		0x01
111 #define	SMIC_MODE		0x02
112 #define	BT_MODE			0x03
113 #define	SSIF_MODE		0x04
114 
115 /* KCS status flags */
116 #define	KCS_STATUS_OBF			0x01 /* Data Out ready from BMC */
117 #define	KCS_STATUS_IBF			0x02 /* Data In from System */
118 #define	KCS_STATUS_SMS_ATN		0x04 /* Ready in RX queue */
119 #define	KCS_STATUS_C_D			0x08 /* Command/Data register write */
120 #define	KCS_STATUS_OEM1			0x10
121 #define	KCS_STATUS_OEM2			0x20
122 #define	KCS_STATUS_S0			0x40
123 #define	KCS_STATUS_S1			0x80
124 #define	KCS_STATUS_STATE(x)		((x)>>6)
125 #define	KCS_STATUS_STATE_IDLE		0x0
126 #define	KCS_STATUS_STATE_READ		0x1
127 #define	KCS_STATUS_STATE_WRITE		0x2
128 #define	KCS_STATUS_STATE_ERROR		0x3
129 #define	KCS_IFACE_STATUS_OK		0x00
130 #define	KCS_IFACE_STATUS_ABORT		0x01
131 #define	KCS_IFACE_STATUS_ILLEGAL	0x02
132 #define	KCS_IFACE_STATUS_LENGTH_ERR	0x06
133 #define	KCS_IFACE_STATUS_UNKNOWN_ERR	0xff
134 
135 /* KCS control codes */
136 #define	KCS_CONTROL_GET_STATUS_ABORT	0x60
137 #define	KCS_CONTROL_WRITE_START		0x61
138 #define	KCS_CONTROL_WRITE_END		0x62
139 #define	KCS_DATA_IN_READ		0x68
140 
141 /* SMIC status flags */
142 #define	SMIC_STATUS_BUSY		0x01 /* System set and BMC clears it */
143 #define	SMIC_STATUS_SMS_ATN		0x04 /* BMC has a message */
144 #define	SMIC_STATUS_EVT_ATN		0x08 /* Event has been RX */
145 #define	SMIC_STATUS_SMI			0x10 /* asserted SMI */
146 #define	SMIC_STATUS_TX_RDY		0x40 /* Ready to accept WRITE */
147 #define	SMIC_STATUS_RX_RDY		0x80 /* Ready to read */
148 #define	SMIC_STATUS_RESERVED		0x22
149 
150 /* SMIC control codes */
151 #define	SMIC_CC_SMS_GET_STATUS		0x40
152 #define	SMIC_CC_SMS_WR_START		0x41
153 #define	SMIC_CC_SMS_WR_NEXT		0x42
154 #define	SMIC_CC_SMS_WR_END		0x43
155 #define	SMIC_CC_SMS_RD_START		0x44
156 #define	SMIC_CC_SMS_RD_NEXT		0x45
157 #define	SMIC_CC_SMS_RD_END		0x46
158 
159 /* SMIC status codes */
160 #define	SMIC_SC_SMS_RDY			0xc0
161 #define	SMIC_SC_SMS_WR_START		0xc1
162 #define	SMIC_SC_SMS_WR_NEXT		0xc2
163 #define	SMIC_SC_SMS_WR_END		0xc3
164 #define	SMIC_SC_SMS_RD_START		0xc4
165 #define	SMIC_SC_SMS_RD_NEXT		0xc5
166 #define	SMIC_SC_SMS_RD_END		0xc6
167 
168 #define	IPMI_ADDR(netfn, lun)		((netfn) << 2 | (lun))
169 #define	IPMI_REPLY_ADDR(addr)		((addr) + 0x4)
170 
171 #define	IPMI_LOCK(sc)			mutex_enter(&(sc)->ipmi_lock)
172 #define	IPMI_UNLOCK(sc)			mutex_exit(&(sc)->ipmi_lock)
173 #define	IPMI_LOCK_ASSERT(sc)		ASSERT(MUTEX_HELD(&(sc)->ipmi_lock))
174 
175 #define	ipmi_alloc_driver_request(addr, cmd, reqlen, replylen)		\
176 	ipmi_alloc_request(NULL, 0, (addr), (cmd), (reqlen), (replylen))
177 
178 #define	INB(sc, x)							\
179 	inb((sc)->ipmi_io_address + ((sc)->ipmi_io_spacing * (x)))
180 #define	OUTB(sc, x, value)						\
181 	outb((sc)->ipmi_io_address + ((sc)->ipmi_io_spacing * (x)), value)
182 
183 #define	MAX_TIMEOUT (3 * hz)
184 
185 /* Manage requests. */
186 void	ipmi_complete_request(struct ipmi_softc *, struct ipmi_request *);
187 struct ipmi_request *ipmi_dequeue_request(struct ipmi_softc *);
188 int	ipmi_polled_enqueue_request(struct ipmi_softc *, struct ipmi_request *);
189 struct ipmi_request *ipmi_alloc_request(struct ipmi_device *, long msgid,
190 	    uint8_t, uint8_t, size_t, size_t);
191 void	ipmi_free_request(struct ipmi_request *);
192 
193 /* Interface attach routines. */
194 boolean_t ipmi_startup(struct ipmi_softc *sc);
195 int	ipmi_kcs_attach(struct ipmi_softc *);
196 
197 /* Interface detach cleanup */
198 void	ipmi_shutdown(struct ipmi_softc *sc);
199 
200 #ifdef	__cplusplus
201 }
202 #endif
203 
204 #endif	/* _IPMIVARS_H_ */
205