1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 /* 6 * radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 7 * 8 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 9 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 10 * All rights reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 29 * DEALINGS IN THE SOFTWARE. 30 * 31 * Authors: 32 * Kevin E. Martin <martin@valinux.com> 33 * Gareth Hughes <gareth@valinux.com> 34 */ 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #ifndef __RADEON_DRV_H__ 39 #define __RADEON_DRV_H__ 40 41 /* 42 * Enable debugging information outputs. Need to recompile 43 * 44 * #define RADEON_FIFO_DEBUG 1 45 */ 46 47 /* General customization: */ 48 49 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 50 51 #define DRIVER_NAME "radeon" 52 #define DRIVER_DESC "ATI Radeon" 53 #define DRIVER_DATE "20060524" 54 55 /* 56 * Interface history: 57 * 58 * 1.1 - ?? 59 * 1.2 - Add vertex2 ioctl (keith) 60 * - Add stencil capability to clear ioctl (gareth, keith) 61 * - Increase MAX_TEXTURE_LEVELS (brian) 62 * 1.3 - Add cmdbuf ioctl (keith) 63 * - Add support for new radeon packets (keith) 64 * - Add getparam ioctl (keith) 65 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 66 * 1.4 - Add scratch registers to get_param ioctl. 67 * 1.5 - Add r200 packets to cmdbuf ioctl 68 * - Add r200 function to init ioctl 69 * - Add 'scalar2' instruction to cmdbuf 70 * 1.6 - Add static GART memory manager 71 * Add irq handler (won't be turned on unless X server knows to) 72 * Add irq ioctls and irq_active getparam. 73 * Add wait command for cmdbuf ioctl 74 * Add GART offset query for getparam 75 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 76 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 77 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 78 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 79 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 80 * Add 'GET' queries for starting additional clients on different 81 * VT's. 82 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 83 * Add texture rectangle support for r100. 84 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 85 * clients use to tell the DRM where they think the framebuffer is 86 * located in the card's address space 87 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 88 * and GL_EXT_blend_[func|equation]_separate on r200 89 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 90 * (No 3D support yet - just microcode loading). 91 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 92 * - Add hyperz support, add hyperz flags to clear ioctl. 93 * 1.14- Add support for color tiling 94 * - Add R100/R200 surface allocation/free support 95 * 1.15- Add support for texture micro tiling 96 * - Add support for r100 cube maps 97 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 98 * texture filtering on r200 99 * 1.17- Add initial support for R300 (3D). 100 * 1.18- Add support for GL_ATI_fragment_shader, new packets 101 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 102 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and 103 * R200_EMIT_ATF_TFACTOR 104 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 105 * 1.19- Add support for gart table in FB memory and PCIE r300 106 * 1.20- Add support for r300 texrect 107 * 1.21- Add support for card type getparam 108 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 109 * 1.23- Add new radeon memory map work from benh 110 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 111 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 112 * new packet type) 113 */ 114 115 #define DRIVER_MAJOR 1 116 #define DRIVER_MINOR 25 117 #define DRIVER_PATCHLEVEL 0 118 119 /* 120 * Radeon chip families 121 */ 122 enum radeon_family { 123 CHIP_R100, 124 CHIP_RV100, 125 CHIP_RS100, 126 CHIP_RV200, 127 CHIP_RS200, 128 CHIP_R200, 129 CHIP_RV250, 130 CHIP_RS300, 131 CHIP_RV280, 132 CHIP_R300, 133 CHIP_R350, 134 CHIP_RV350, 135 CHIP_RV380, 136 CHIP_R420, 137 CHIP_RV410, 138 CHIP_RS400, 139 CHIP_LAST, 140 }; 141 142 enum radeon_cp_microcode_version { 143 UCODE_R100, 144 UCODE_R200, 145 UCODE_R300, 146 }; 147 148 /* 149 * Chip flags 150 */ 151 #define RADEON_FAMILY_MASK 0x0000ffffUL 152 #define RADEON_FLAGS_MASK 0xffff0000UL 153 #define RADEON_IS_MOBILITY 0x00010000UL 154 #define RADEON_IS_IGP 0x00020000UL 155 #define RADEON_SINGLE_CRTC 0x00040000UL 156 #define RADEON_IS_AGP 0x00080000UL 157 #define RADEON_HAS_HIERZ 0x00100000UL 158 #define RADEON_IS_PCIE 0x00200000UL 159 #define RADEON_NEW_MEMMAP 0x00400000UL 160 #define RADEON_IS_PCI 0x00800000UL 161 162 #define GET_RING_HEAD(dev_priv) \ 163 (dev_priv->writeback_works ? \ 164 DRM_READ32((dev_priv)->ring_rptr, 0) : \ 165 RADEON_READ(RADEON_CP_RB_RPTR)) 166 167 #define SET_RING_HEAD(dev_priv, val) \ 168 DRM_WRITE32((dev_priv)->ring_rptr, 0, (val)) 169 170 typedef struct drm_radeon_freelist { 171 unsigned int age; 172 drm_buf_t *buf; 173 struct drm_radeon_freelist *next; 174 struct drm_radeon_freelist *prev; 175 } drm_radeon_freelist_t; 176 177 typedef struct drm_radeon_ring_buffer { 178 u32 *start; 179 u32 *end; 180 int size; 181 int size_l2qw; 182 183 u32 tail; 184 u32 tail_mask; 185 int space; 186 187 int high_mark; 188 } drm_radeon_ring_buffer_t; 189 190 typedef struct drm_radeon_depth_clear_t { 191 u32 rb3d_cntl; 192 u32 rb3d_zstencilcntl; 193 u32 se_cntl; 194 } drm_radeon_depth_clear_t; 195 196 struct drm_radeon_driver_file_fields { 197 int64_t radeon_fb_delta; 198 }; 199 200 struct mem_block { 201 struct mem_block *next; 202 struct mem_block *prev; 203 int start; 204 int size; 205 drm_file_t *filp; /* 0: free, -1: heap, other: real files */ 206 }; 207 208 struct radeon_surface { 209 int refcount; 210 u32 lower; 211 u32 upper; 212 u32 flags; 213 }; 214 215 struct radeon_virt_surface { 216 int surface_index; 217 u32 lower; 218 u32 upper; 219 u32 flags; 220 drm_file_t *filp; 221 }; 222 223 typedef struct drm_radeon_private { 224 225 drm_radeon_ring_buffer_t ring; 226 drm_radeon_sarea_t *sarea_priv; 227 228 u32 fb_location; 229 u32 fb_size; 230 int new_memmap; 231 232 int gart_size; 233 u32 gart_vm_start; 234 unsigned long gart_buffers_offset; 235 236 int cp_mode; 237 int cp_running; 238 239 drm_radeon_freelist_t *head; 240 drm_radeon_freelist_t *tail; 241 int last_buf; 242 volatile u32 *scratch; 243 int writeback_works; 244 245 int usec_timeout; 246 247 int microcode_version; 248 249 struct { 250 u32 boxes; 251 int freelist_timeouts; 252 int freelist_loops; 253 int requested_bufs; 254 int last_frame_reads; 255 int last_clear_reads; 256 int clears; 257 int texture_uploads; 258 } stats; 259 260 int do_boxes; 261 int page_flipping; 262 int current_page; 263 264 u32 color_fmt; 265 unsigned int front_offset; 266 unsigned int front_pitch; 267 unsigned int back_offset; 268 unsigned int back_pitch; 269 270 u32 depth_fmt; 271 unsigned int depth_offset; 272 unsigned int depth_pitch; 273 274 u32 front_pitch_offset; 275 u32 back_pitch_offset; 276 u32 depth_pitch_offset; 277 278 drm_radeon_depth_clear_t depth_clear; 279 280 unsigned long ring_offset; 281 unsigned long ring_rptr_offset; 282 unsigned long buffers_offset; 283 unsigned long gart_textures_offset; 284 285 drm_local_map_t *sarea; 286 drm_local_map_t *mmio; 287 drm_local_map_t *cp_ring; 288 drm_local_map_t *ring_rptr; 289 drm_local_map_t *gart_textures; 290 291 struct mem_block *gart_heap; 292 struct mem_block *fb_heap; 293 294 /* SW interrupt */ 295 wait_queue_head_t swi_queue; 296 atomic_t swi_emitted; 297 int vblank_crtc; 298 uint32_t irq_enable_reg; 299 int irq_enabled; 300 301 302 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 303 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 304 305 unsigned long pcigart_offset; 306 drm_ati_pcigart_info gart_info; 307 308 u32 scratch_ages[5]; 309 310 /* starting from here on, data is preserved accross an open */ 311 uint32_t flags; /* see radeon_chip_flags */ 312 313 } drm_radeon_private_t; 314 315 typedef struct drm_radeon_buf_priv { 316 u32 age; 317 } drm_radeon_buf_priv_t; 318 319 typedef struct drm_radeon_kcmd_buffer { 320 int bufsz; 321 char *buf; 322 int nbox; 323 drm_clip_rect_t __user *boxes; 324 } drm_radeon_kcmd_buffer_t; 325 326 extern int radeon_no_wb; 327 extern drm_ioctl_desc_t radeon_ioctls[]; 328 extern int radeon_max_ioctl; 329 330 331 /* 332 * Check whether the given hardware address is inside the framebuffer or the 333 * GART area. 334 */ 335 static inline int 336 radeon_check_offset(drm_radeon_private_t *dev_priv, uint64_t off) 337 { 338 u32 fb_start = dev_priv->fb_location; 339 u32 fb_end = fb_start + dev_priv->fb_size - 1; 340 u32 gart_start = dev_priv->gart_vm_start; 341 u32 gart_end = gart_start + dev_priv->gart_size - 1; 342 343 return ((off >= fb_start && off <= fb_end) || 344 (off >= gart_start && off <= gart_end)); 345 } 346 347 /* radeon_cp.c */ 348 extern int radeon_cp_init(DRM_IOCTL_ARGS); 349 extern int radeon_cp_start(DRM_IOCTL_ARGS); 350 extern int radeon_cp_stop(DRM_IOCTL_ARGS); 351 extern int radeon_cp_reset(DRM_IOCTL_ARGS); 352 extern int radeon_cp_idle(DRM_IOCTL_ARGS); 353 extern int radeon_cp_resume(DRM_IOCTL_ARGS); 354 extern int radeon_engine_reset(DRM_IOCTL_ARGS); 355 extern int radeon_fullscreen(DRM_IOCTL_ARGS); 356 extern int radeon_cp_buffers(DRM_IOCTL_ARGS); 357 358 extern void radeon_freelist_reset(drm_device_t *dev); 359 extern drm_buf_t *radeon_freelist_get(drm_device_t *dev); 360 361 extern int radeon_wait_ring(drm_radeon_private_t *dev_priv, int n); 362 363 extern int radeon_do_cp_idle(drm_radeon_private_t *dev_priv); 364 365 extern int radeon_mem_alloc(DRM_IOCTL_ARGS); 366 extern int radeon_mem_free(DRM_IOCTL_ARGS); 367 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); 368 extern void radeon_mem_takedown(struct mem_block **heap); 369 extern void radeon_mem_release(drm_file_t *filp, struct mem_block *heap); 370 371 /* radeon_irq.c */ 372 extern int radeon_irq_emit(DRM_IOCTL_ARGS); 373 extern int radeon_irq_wait(DRM_IOCTL_ARGS); 374 375 extern void radeon_do_release(drm_device_t *dev); 376 extern int radeon_driver_vblank_wait(drm_device_t *dev, 377 unsigned int *sequence); 378 extern int radeon_driver_vblank_wait2(drm_device_t *dev, 379 unsigned int *sequence); 380 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 381 extern void radeon_driver_irq_preinstall(drm_device_t *dev); 382 extern void radeon_driver_irq_postinstall(drm_device_t *dev); 383 extern void radeon_driver_irq_uninstall(drm_device_t *dev); 384 extern int radeon_vblank_crtc_get(struct drm_device *dev); 385 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 386 387 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 388 extern int radeon_driver_unload(struct drm_device *dev); 389 extern int radeon_driver_firstopen(struct drm_device *dev); 390 extern void radeon_driver_preclose(drm_device_t *dev, drm_file_t *filp); 391 extern void radeon_driver_postclose(drm_device_t *dev, drm_file_t *filp); 392 extern void radeon_driver_lastclose(drm_device_t *dev); 393 extern int radeon_driver_open(drm_device_t *dev, drm_file_t *filp_priv); 394 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 395 unsigned long arg); 396 397 /* r300_cmdbuf.c */ 398 extern void r300_init_reg_flags(void); 399 400 extern int r300_do_cp_cmdbuf(drm_device_t *dev, 401 drm_file_t *fpriv, drm_radeon_kcmd_buffer_t *cmdbuf); 402 403 /* Flags for stats.boxes */ 404 #define RADEON_BOX_DMA_IDLE 0x1 405 #define RADEON_BOX_RING_FULL 0x2 406 #define RADEON_BOX_FLIP 0x4 407 #define RADEON_BOX_WAIT_IDLE 0x8 408 #define RADEON_BOX_TEXTURE_LOAD 0x10 409 410 /* 411 * Register definitions, register access macros and drmAddMap constants 412 * for Radeon kernel driver. 413 */ 414 #define RADEON_AGP_COMMAND 0x0f60 415 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 416 #define RADEON_AGP_ENABLE (1<<8) 417 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 418 #define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 419 #define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 420 #define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 421 #define RADEON_SCISSOR_0_ENABLE (1 << 28) 422 #define RADEON_SCISSOR_1_ENABLE (1 << 29) 423 #define RADEON_SCISSOR_2_ENABLE (1 << 30) 424 425 #define RADEON_BUS_CNTL 0x0030 426 #define RADEON_BUS_MASTER_DIS (1 << 6) 427 428 #define RADEON_CLOCK_CNTL_DATA 0x000c 429 #define RADEON_PLL_WR_EN (1 << 7) 430 #define RADEON_CLOCK_CNTL_INDEX 0x0008 431 #define RADEON_CONFIG_APER_SIZE 0x0108 432 #define RADEON_CONFIG_MEMSIZE 0x00f8 433 #define RADEON_CRTC_OFFSET 0x0224 434 #define RADEON_CRTC_OFFSET_CNTL 0x0228 435 #define RADEON_CRTC_TILE_EN (1 << 15) 436 #define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 437 #define RADEON_CRTC2_OFFSET 0x0324 438 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 439 440 #define RADEON_PCIE_INDEX 0x0030 441 #define RADEON_PCIE_DATA 0x0034 442 #define RADEON_PCIE_TX_GART_CNTL 0x10 443 #define RADEON_PCIE_TX_GART_EN (1 << 0) 444 #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 445 #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 446 #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 447 #define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 448 #define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 449 #define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 450 #define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 451 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 452 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 453 #define RADEON_PCIE_TX_GART_BASE 0x13 454 #define RADEON_PCIE_TX_GART_START_LO 0x14 455 #define RADEON_PCIE_TX_GART_START_HI 0x15 456 #define RADEON_PCIE_TX_GART_END_LO 0x16 457 #define RADEON_PCIE_TX_GART_END_HI 0x17 458 459 #define RADEON_MPP_TB_CONFIG 0x01c0 460 #define RADEON_MEM_CNTL 0x0140 461 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 462 #define RADEON_AGP_BASE 0x0170 463 464 #define RADEON_RB3D_COLOROFFSET 0x1c40 465 #define RADEON_RB3D_COLORPITCH 0x1c48 466 467 #define RADEON_SRC_X_Y 0x1590 468 469 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 470 #define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 471 #define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 472 #define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 473 #define RADEON_GMC_BRUSH_NONE (15 << 4) 474 #define RADEON_GMC_DST_16BPP (4 << 8) 475 #define RADEON_GMC_DST_24BPP (5 << 8) 476 #define RADEON_GMC_DST_32BPP (6 << 8) 477 #define RADEON_GMC_DST_DATATYPE_SHIFT 8 478 #define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 479 #define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 480 #define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 481 #define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 482 #define RADEON_GMC_WR_MSK_DIS (1 << 30) 483 #define RADEON_ROP3_S 0x00cc0000 484 #define RADEON_ROP3_P 0x00f00000 485 #define RADEON_DP_WRITE_MASK 0x16cc 486 #define RADEON_SRC_PITCH_OFFSET 0x1428 487 #define RADEON_DST_PITCH_OFFSET 0x142c 488 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 489 #define RADEON_DST_TILE_LINEAR (0 << 30) 490 #define RADEON_DST_TILE_MACRO (1 << 30) 491 #define RADEON_DST_TILE_MICRO ((uint_t)2 << 30) 492 #define RADEON_DST_TILE_BOTH ((uint_t)3 << 30) 493 494 #define RADEON_SCRATCH_REG0 0x15e0 495 #define RADEON_SCRATCH_REG1 0x15e4 496 #define RADEON_SCRATCH_REG2 0x15e8 497 #define RADEON_SCRATCH_REG3 0x15ec 498 #define RADEON_SCRATCH_REG4 0x15f0 499 #define RADEON_SCRATCH_REG5 0x15f4 500 #define RADEON_SCRATCH_UMSK 0x0770 501 #define RADEON_SCRATCH_ADDR 0x0774 502 503 #define RADEON_SCRATCHOFF(x) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 504 505 #define GET_SCRATCH(x) (dev_priv->writeback_works ? \ 506 DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x)) : \ 507 RADEON_READ(RADEON_SCRATCH_REG0 + 4*(x))) 508 509 #define RADEON_GEN_INT_CNTL 0x0040 510 #define RADEON_CRTC_VBLANK_MASK (1 << 0) 511 #define RADEON_CRTC2_VBLANK_MASK (1 << 9) 512 #define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 513 #define RADEON_SW_INT_ENABLE (1 << 25) 514 515 #define RADEON_GEN_INT_STATUS 0x0044 516 #define RADEON_CRTC_VBLANK_STAT (1 << 0) 517 #define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 518 #define RADEON_CRTC2_VBLANK_STAT (1 << 9) 519 #define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 520 #define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 521 #define RADEON_SW_INT_TEST (1 << 25) 522 #define RADEON_SW_INT_TEST_ACK (1 << 25) 523 #define RADEON_SW_INT_FIRE (1 << 26) 524 525 #define RADEON_HOST_PATH_CNTL 0x0130 526 #define RADEON_HDP_SOFT_RESET (1 << 26) 527 #define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 528 #define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 529 530 #define RADEON_ISYNC_CNTL 0x1724 531 #define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 532 #define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 533 #define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 534 #define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 535 #define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 536 #define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 537 538 #define RADEON_RBBM_GUICNTL 0x172c 539 #define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 540 #define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 541 #define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 542 #define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 543 544 #define RADEON_MC_AGP_LOCATION 0x014c 545 #define RADEON_MC_FB_LOCATION 0x0148 546 #define RADEON_MCLK_CNTL 0x0012 547 #define RADEON_FORCEON_MCLKA (1 << 16) 548 #define RADEON_FORCEON_MCLKB (1 << 17) 549 #define RADEON_FORCEON_YCLKA (1 << 18) 550 #define RADEON_FORCEON_YCLKB (1 << 19) 551 #define RADEON_FORCEON_MC (1 << 20) 552 #define RADEON_FORCEON_AIC (1 << 21) 553 554 #define RADEON_PP_BORDER_COLOR_0 0x1d40 555 #define RADEON_PP_BORDER_COLOR_1 0x1d44 556 #define RADEON_PP_BORDER_COLOR_2 0x1d48 557 #define RADEON_PP_CNTL 0x1c38 558 #define RADEON_SCISSOR_ENABLE (1 << 1) 559 #define RADEON_PP_LUM_MATRIX 0x1d00 560 #define RADEON_PP_MISC 0x1c14 561 #define RADEON_PP_ROT_MATRIX_0 0x1d58 562 #define RADEON_PP_TXFILTER_0 0x1c54 563 #define RADEON_PP_TXOFFSET_0 0x1c5c 564 #define RADEON_PP_TXFILTER_1 0x1c6c 565 #define RADEON_PP_TXFILTER_2 0x1c84 566 567 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 568 #define RADEON_RB2D_DC_FLUSH (3 << 0) 569 #define RADEON_RB2D_DC_FREE (3 << 2) 570 #define RADEON_RB2D_DC_FLUSH_ALL 0xf 571 #define RADEON_RB2D_DC_BUSY 0x80000000 572 #define RADEON_RB3D_CNTL 0x1c3c 573 #define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 574 #define RADEON_PLANE_MASK_ENABLE (1 << 1) 575 #define RADEON_DITHER_ENABLE (1 << 2) 576 #define RADEON_ROUND_ENABLE (1 << 3) 577 #define RADEON_SCALE_DITHER_ENABLE (1 << 4) 578 #define RADEON_DITHER_INIT (1 << 5) 579 #define RADEON_ROP_ENABLE (1 << 6) 580 #define RADEON_STENCIL_ENABLE (1 << 7) 581 #define RADEON_Z_ENABLE (1 << 8) 582 #define RADEON_ZBLOCK16 (1 << 15) 583 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 584 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 585 #define RADEON_RB3D_DEPTHPITCH 0x1c28 586 #define RADEON_RB3D_PLANEMASK 0x1d84 587 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 588 #define RADEON_RB3D_ZCACHE_MODE 0x3250 589 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 590 #define RADEON_RB3D_ZC_FLUSH (1 << 0) 591 #define RADEON_RB3D_ZC_FREE (1 << 2) 592 #define RADEON_RB3D_ZC_FLUSH_ALL 0x5 593 #define RADEON_RB3D_ZC_BUSY 0x80000000UL 594 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 595 #define RADEON_RB3D_DC_FLUSH (3 << 0) 596 #define RADEON_RB3D_DC_FREE (3 << 2) 597 #define RADEON_RB3D_DC_FLUSH_ALL 0xf 598 #define RADEON_RB3D_DC_BUSY 0x80000000UL 599 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 600 #define RADEON_Z_TEST_MASK (7 << 4) 601 #define RADEON_Z_TEST_ALWAYS (7 << 4) 602 #define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 603 #define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 604 #define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 605 #define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 606 #define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 607 #define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 608 #define RADEON_FORCE_Z_DIRTY (1 << 29) 609 #define RADEON_Z_WRITE_ENABLE (1 << 30) 610 #define RADEON_Z_DECOMPRESSION_ENABLE 0x80000000UL 611 #define RADEON_RBBM_SOFT_RESET 0x00f0 612 #define RADEON_SOFT_RESET_CP (1 << 0) 613 #define RADEON_SOFT_RESET_HI (1 << 1) 614 #define RADEON_SOFT_RESET_SE (1 << 2) 615 #define RADEON_SOFT_RESET_RE (1 << 3) 616 #define RADEON_SOFT_RESET_PP (1 << 4) 617 #define RADEON_SOFT_RESET_E2 (1 << 5) 618 #define RADEON_SOFT_RESET_RB (1 << 6) 619 #define RADEON_SOFT_RESET_HDP (1 << 7) 620 #define RADEON_RBBM_STATUS 0x0e40 621 #define RADEON_RBBM_FIFOCNT_MASK 0x007f 622 #define RADEON_RBBM_ACTIVE 0X80000000UL 623 #define RADEON_RE_LINE_PATTERN 0x1cd0 624 #define RADEON_RE_MISC 0x26c4 625 #define RADEON_RE_TOP_LEFT 0x26c0 626 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 627 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 628 #define RADEON_RE_STIPPLE_DATA 0x1ccc 629 630 #define RADEON_SCISSOR_TL_0 0x1cd8 631 #define RADEON_SCISSOR_BR_0 0x1cdc 632 #define RADEON_SCISSOR_TL_1 0x1ce0 633 #define RADEON_SCISSOR_BR_1 0x1ce4 634 #define RADEON_SCISSOR_TL_2 0x1ce8 635 #define RADEON_SCISSOR_BR_2 0x1cec 636 #define RADEON_SE_COORD_FMT 0x1c50 637 #define RADEON_SE_CNTL 0x1c4c 638 #define RADEON_FFACE_CULL_CW (0 << 0) 639 #define RADEON_BFACE_SOLID (3 << 1) 640 #define RADEON_FFACE_SOLID (3 << 3) 641 #define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 642 #define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 643 #define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 644 #define RADEON_ALPHA_SHADE_FLAT (1 << 10) 645 #define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 646 #define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 647 #define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 648 #define RADEON_FOG_SHADE_FLAT (1 << 14) 649 #define RADEON_FOG_SHADE_GOURAUD (2 << 14) 650 #define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 651 #define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 652 #define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 653 #define RADEON_ROUND_MODE_TRUNC (0 << 28) 654 #define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 655 #define RADEON_SE_CNTL_STATUS 0x2140 656 #define RADEON_SE_LINE_WIDTH 0x1db8 657 #define RADEON_SE_VPORT_XSCALE 0x1d98 658 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 659 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 660 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 661 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 662 #define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 663 #define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 664 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 665 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 666 #define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 667 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 668 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 669 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 670 #define RADEON_SURFACE_CNTL 0x0b00 671 #define RADEON_SURF_TRANSLATION_DIS (1 << 8) 672 #define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 673 #define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 674 #define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 675 #define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 676 #define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 677 #define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 678 #define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 679 #define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 680 #define RADEON_SURFACE0_INFO 0x0b0c 681 #define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 682 #define RADEON_SURF_TILE_MODE_MASK (3 << 16) 683 #define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 684 #define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 685 #define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 686 #define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 687 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 688 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 689 #define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 690 #define RADEON_SURFACE1_INFO 0x0b1c 691 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 692 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 693 #define RADEON_SURFACE2_INFO 0x0b2c 694 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 695 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 696 #define RADEON_SURFACE3_INFO 0x0b3c 697 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 698 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 699 #define RADEON_SURFACE4_INFO 0x0b4c 700 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 701 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 702 #define RADEON_SURFACE5_INFO 0x0b5c 703 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 704 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 705 #define RADEON_SURFACE6_INFO 0x0b6c 706 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 707 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 708 #define RADEON_SURFACE7_INFO 0x0b7c 709 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 710 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 711 #define RADEON_SW_SEMAPHORE 0x013c 712 713 #define RADEON_WAIT_UNTIL 0x1720 714 #define RADEON_WAIT_CRTC_PFLIP (1 << 0) 715 #define RADEON_WAIT_2D_IDLE (1 << 14) 716 #define RADEON_WAIT_3D_IDLE (1 << 15) 717 #define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 718 #define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 719 #define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 720 721 #define RADEON_RB3D_ZMASKOFFSET 0x3234 722 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 723 #define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 724 #define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 725 726 /* CP registers */ 727 #define RADEON_CP_ME_RAM_ADDR 0x07d4 728 #define RADEON_CP_ME_RAM_RADDR 0x07d8 729 #define RADEON_CP_ME_RAM_DATAH 0x07dc 730 #define RADEON_CP_ME_RAM_DATAL 0x07e0 731 732 #define RADEON_CP_RB_BASE 0x0700 733 #define RADEON_CP_RB_CNTL 0x0704 734 #define RADEON_BUF_SWAP_32BIT (2 << 16) 735 #define RADEON_RB_NO_UPDATE (1 << 27) 736 737 #define RADEON_CP_RB_RPTR_ADDR 0x070c 738 #define RADEON_CP_RB_RPTR 0x0710 739 #define RADEON_CP_RB_WPTR 0x0714 740 741 #define RADEON_CP_RB_WPTR_DELAY 0x0718 742 #define RADEON_PRE_WRITE_TIMER_SHIFT 0 743 #define RADEON_PRE_WRITE_LIMIT_SHIFT 23 744 745 #define RADEON_CP_IB_BASE 0x0738 746 747 #define RADEON_CP_CSQ_CNTL 0x0740 748 #define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 749 #define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 750 #define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 751 #define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 752 #define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 753 #define RADEON_CSQ_PRIBM_INDBM (4 << 28) 754 #define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 755 756 #define RADEON_AIC_CNTL 0x01d0 757 #define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 758 #define RADEON_AIC_STAT 0x01d4 759 #define RADEON_AIC_PT_BASE 0x01d8 760 #define RADEON_AIC_LO_ADDR 0x01dc 761 #define RADEON_AIC_HI_ADDR 0x01e0 762 #define RADEON_AIC_TLB_ADDR 0x01e4 763 #define RADEON_AIC_TLB_DATA 0x01e8 764 765 /* CP command packets */ 766 #define RADEON_CP_PACKET0 0x00000000 767 #define RADEON_ONE_REG_WR (1 << 15) 768 #define RADEON_CP_PACKET1 0x40000000 769 #define RADEON_CP_PACKET2 0x80000000 770 #define RADEON_CP_PACKET3 0xC0000000 771 #define RADEON_CP_NOP 0x00001000 772 #define RADEON_CP_NEXT_CHAR 0x00001900 773 #define RADEON_CP_PLY_NEXTSCAN 0x00001D00 774 #define RADEON_CP_SET_SCISSORS 0x00001E00 775 776 /* GEN_INDX_PRIM is unsupported starting with R300 */ 777 #define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 778 #define RADEON_WAIT_FOR_IDLE 0x00002600 779 #define RADEON_3D_DRAW_VBUF 0x00002800 780 #define RADEON_3D_DRAW_IMMD 0x00002900 781 #define RADEON_3D_DRAW_INDX 0x00002A00 782 #define RADEON_CP_LOAD_PALETTE 0x00002C00 783 #define RADEON_3D_LOAD_VBPNTR 0x00002F00 784 #define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 785 #define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 786 #define RADEON_3D_CLEAR_ZMASK 0x00003200 787 #define RADEON_CP_INDX_BUFFER 0x00003300 788 #define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 789 #define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 790 #define RADEON_CP_3D_DRAW_INDX_2 0x00003600 791 #define RADEON_3D_CLEAR_HIZ 0x00003700 792 #define RADEON_CP_3D_CLEAR_CMASK 0x00003802 793 #define RADEON_CNTL_HOSTDATA_BLT 0x00009400 794 #define RADEON_CNTL_PAINT_MULTI 0x00009A00 795 #define RADEON_CNTL_BITBLT_MULTI 0x00009B00 796 #define RADEON_CNTL_SET_SCISSORS 0xC0001E00 797 798 #define RADEON_CP_PACKET_MASK 0xC0000000 799 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 800 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 801 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 802 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 803 804 #define RADEON_VTX_Z_PRESENT 0x80000000 805 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 806 807 #define RADEON_PRIM_TYPE_NONE (0 << 0) 808 #define RADEON_PRIM_TYPE_POINT (1 << 0) 809 #define RADEON_PRIM_TYPE_LINE (2 << 0) 810 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 811 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 812 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 813 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 814 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 815 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 816 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 817 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 818 #define RADEON_PRIM_TYPE_MASK 0xf 819 #define RADEON_PRIM_WALK_IND (1 << 4) 820 #define RADEON_PRIM_WALK_LIST (2 << 4) 821 #define RADEON_PRIM_WALK_RING (3 << 4) 822 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 823 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 824 #define RADEON_MAOS_ENABLE (1 << 7) 825 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 826 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 827 #define RADEON_NUM_VERTICES_SHIFT 16 828 829 #define RADEON_COLOR_FORMAT_CI8 2 830 #define RADEON_COLOR_FORMAT_ARGB1555 3 831 #define RADEON_COLOR_FORMAT_RGB565 4 832 #define RADEON_COLOR_FORMAT_ARGB8888 6 833 #define RADEON_COLOR_FORMAT_RGB332 7 834 #define RADEON_COLOR_FORMAT_RGB8 9 835 #define RADEON_COLOR_FORMAT_ARGB4444 15 836 837 #define RADEON_TXFORMAT_I8 0 838 #define RADEON_TXFORMAT_AI88 1 839 #define RADEON_TXFORMAT_RGB332 2 840 #define RADEON_TXFORMAT_ARGB1555 3 841 #define RADEON_TXFORMAT_RGB565 4 842 #define RADEON_TXFORMAT_ARGB4444 5 843 #define RADEON_TXFORMAT_ARGB8888 6 844 #define RADEON_TXFORMAT_RGBA8888 7 845 #define RADEON_TXFORMAT_Y8 8 846 #define RADEON_TXFORMAT_VYUY422 10 847 #define RADEON_TXFORMAT_YVYU422 11 848 #define RADEON_TXFORMAT_DXT1 12 849 #define RADEON_TXFORMAT_DXT23 14 850 #define RADEON_TXFORMAT_DXT45 15 851 852 #define R200_PP_TXCBLEND_0 0x2f00 853 #define R200_PP_TXCBLEND_1 0x2f10 854 #define R200_PP_TXCBLEND_2 0x2f20 855 #define R200_PP_TXCBLEND_3 0x2f30 856 #define R200_PP_TXCBLEND_4 0x2f40 857 #define R200_PP_TXCBLEND_5 0x2f50 858 #define R200_PP_TXCBLEND_6 0x2f60 859 #define R200_PP_TXCBLEND_7 0x2f70 860 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 861 #define R200_PP_TFACTOR_0 0x2ee0 862 #define R200_SE_VTX_FMT_0 0x2088 863 #define R200_SE_VAP_CNTL 0x2080 864 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 865 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 866 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 867 #define R200_PP_TXFILTER_5 0x2ca0 868 #define R200_PP_TXFILTER_4 0x2c80 869 #define R200_PP_TXFILTER_3 0x2c60 870 #define R200_PP_TXFILTER_2 0x2c40 871 #define R200_PP_TXFILTER_1 0x2c20 872 #define R200_PP_TXFILTER_0 0x2c00 873 #define R200_PP_TXOFFSET_5 0x2d78 874 #define R200_PP_TXOFFSET_4 0x2d60 875 #define R200_PP_TXOFFSET_3 0x2d48 876 #define R200_PP_TXOFFSET_2 0x2d30 877 #define R200_PP_TXOFFSET_1 0x2d18 878 #define R200_PP_TXOFFSET_0 0x2d00 879 880 #define R200_PP_CUBIC_FACES_0 0x2c18 881 #define R200_PP_CUBIC_FACES_1 0x2c38 882 #define R200_PP_CUBIC_FACES_2 0x2c58 883 #define R200_PP_CUBIC_FACES_3 0x2c78 884 #define R200_PP_CUBIC_FACES_4 0x2c98 885 #define R200_PP_CUBIC_FACES_5 0x2cb8 886 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 887 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 888 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 889 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 890 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 891 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 892 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 893 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 894 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 895 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 896 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 897 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 898 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 899 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 900 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 901 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 902 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 903 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 904 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 905 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 906 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 907 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 908 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 909 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 910 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 911 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 912 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 913 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 914 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 915 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 916 917 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 918 #define R200_SE_VTE_CNTL 0x20b0 919 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 920 #define R200_PP_TAM_DEBUG3 0x2d9c 921 #define R200_PP_CNTL_X 0x2cc4 922 #define R200_SE_VAP_CNTL_STATUS 0x2140 923 #define R200_RE_SCISSOR_TL_0 0x1cd8 924 #define R200_RE_SCISSOR_TL_1 0x1ce0 925 #define R200_RE_SCISSOR_TL_2 0x1ce8 926 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 927 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 928 #define R200_SE_VTX_STATE_CNTL 0x2180 929 #define R200_RE_POINTSIZE 0x2648 930 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 931 932 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 933 #define RADEON_PP_TEX_SIZE_1 0x1d0c 934 #define RADEON_PP_TEX_SIZE_2 0x1d14 935 936 #define RADEON_PP_CUBIC_FACES_0 0x1d24 937 #define RADEON_PP_CUBIC_FACES_1 0x1d28 938 #define RADEON_PP_CUBIC_FACES_2 0x1d2c 939 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 940 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 941 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 942 943 #define RADEON_SE_TCL_STATE_FLUSH 0x2284 944 945 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 946 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 947 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 948 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 949 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 950 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 951 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 952 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 953 #define R200_3D_DRAW_IMMD_2 0xC0003500 954 #define R200_SE_VTX_FMT_1 0x208c 955 #define R200_RE_CNTL 0x1c50 956 957 #define R200_RB3D_BLENDCOLOR 0x3218 958 959 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 960 961 #define R200_PP_TRI_PERF 0x2cf8 962 963 #define R200_PP_AFS_0 0x2f80 964 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 965 966 #define R200_VAP_PVS_CNTL_1 0x22D0 967 968 /* MPEG settings from VHA code */ 969 #define RADEON_VHA_SETTO16_1 0x2694 970 #define RADEON_VHA_SETTO16_2 0x2680 971 #define RADEON_VHA_SETTO0_1 0x1840 972 #define RADEON_VHA_FB_OFFSET 0x19e4 973 #define RADEON_VHA_SETTO1AND70S 0x19d8 974 #define RADEON_VHA_DST_PITCH 0x1408 975 976 // set as reference header 977 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 978 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 979 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 980 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 981 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 982 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 983 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 984 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 985 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 986 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 987 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 988 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 989 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 990 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 991 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 992 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 993 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 994 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 995 996 997 998 /* Constants */ 999 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1000 1001 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1002 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1003 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1004 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1005 #define RADEON_LAST_DISPATCH 1 1006 1007 #define RADEON_MAX_VB_AGE 0x7fffffff 1008 #define RADEON_MAX_VB_VERTS (0xffff) 1009 1010 #define RADEON_RING_HIGH_MARK 128 1011 1012 #define RADEON_PCIGART_TABLE_SIZE (32*1024) 1013 1014 #define RADEON_READ(reg) \ 1015 DRM_READ32(dev_priv->mmio, (reg)) 1016 #define RADEON_WRITE(reg, val) \ 1017 DRM_WRITE32(dev_priv->mmio, (reg), (val)) 1018 #define RADEON_READ8(reg) \ 1019 DRM_READ8(dev_priv->mmio, (reg)) 1020 #define RADEON_WRITE8(reg, val) \ 1021 DRM_WRITE8(dev_priv->mmio, (reg), (val)) 1022 1023 #define RADEON_WRITE_PLL(addr, val) \ 1024 do { \ 1025 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1026 ((addr) & 0x1f) | RADEON_PLL_WR_EN); \ 1027 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1028 } while (*"\0") 1029 1030 #define RADEON_WRITE_PCIE(addr, val) \ 1031 do { \ 1032 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1033 ((addr) & 0xff)); \ 1034 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1035 } while (*"\0") 1036 1037 #define CP_PACKET0(reg, n) \ 1038 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1039 #define CP_PACKET0_TABLE(reg, n) \ 1040 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1041 #define CP_PACKET1(reg0, reg1) \ 1042 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1043 #define CP_PACKET2() \ 1044 (RADEON_CP_PACKET2) 1045 #define CP_PACKET3(pkt, n) \ 1046 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1047 1048 /* 1049 * Engine control helper macros 1050 */ 1051 1052 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1053 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1054 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1055 RADEON_WAIT_HOST_IDLECLEAN)); \ 1056 } while (*"\0") 1057 1058 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1059 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1060 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ 1061 RADEON_WAIT_HOST_IDLECLEAN)); \ 1062 } while (*"\0") 1063 1064 #define RADEON_WAIT_UNTIL_IDLE() do { \ 1065 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1066 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1067 RADEON_WAIT_3D_IDLECLEAN | \ 1068 RADEON_WAIT_HOST_IDLECLEAN)); \ 1069 } while (*"\0") 1070 1071 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1072 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1073 OUT_RING(RADEON_WAIT_CRTC_PFLIP); \ 1074 } while (*"\0") 1075 1076 #define RADEON_FLUSH_CACHE() do { \ 1077 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1078 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1079 } while (*"\0") 1080 1081 #define RADEON_PURGE_CACHE() do { \ 1082 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1083 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1084 } while (*"\0") 1085 1086 #define RADEON_FLUSH_ZCACHE() do { \ 1087 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1088 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1089 } while (*"\0") 1090 1091 #define RADEON_PURGE_ZCACHE() do { \ 1092 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1093 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1094 } while (*"\0") 1095 1096 /* 1097 * Misc helper macros 1098 */ 1099 1100 /* Perfbox functionality only. */ 1101 #define RING_SPACE_TEST_WITH_RETURN(dev_priv) \ 1102 do { \ 1103 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1104 u32 head = GET_RING_HEAD(dev_priv); \ 1105 if (head == dev_priv->ring.tail) \ 1106 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1107 } \ 1108 } while (*"\0") 1109 1110 #define VB_AGE_TEST_WITH_RETURN(dev_priv) \ 1111 do { \ 1112 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1113 if (sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE) { \ 1114 int __ret = radeon_do_cp_idle(dev_priv); \ 1115 if (__ret) \ 1116 return (__ret); \ 1117 sarea_priv->last_dispatch = 0; \ 1118 radeon_freelist_reset(dev); \ 1119 } \ 1120 } while (*"\0") 1121 1122 #define RADEON_DISPATCH_AGE(age) do { \ 1123 OUT_RING(CP_PACKET0(RADEON_LAST_DISPATCH_REG, 0)); \ 1124 OUT_RING(age); \ 1125 } while (*"\0") 1126 1127 #define RADEON_FRAME_AGE(age) do { \ 1128 OUT_RING(CP_PACKET0(RADEON_LAST_FRAME_REG, 0)); \ 1129 OUT_RING(age); \ 1130 } while (*"\0") 1131 1132 #define RADEON_CLEAR_AGE(age) do { \ 1133 OUT_RING(CP_PACKET0(RADEON_LAST_CLEAR_REG, 0)); \ 1134 OUT_RING(age); \ 1135 } while (*"\0") 1136 1137 /* 1138 * Ring control 1139 */ 1140 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1141 1142 #define BEGIN_RING(n) do { \ 1143 if (dev_priv->ring.space <= (n) * sizeof (u32)) { \ 1144 COMMIT_RING(); \ 1145 (void) radeon_wait_ring(dev_priv, (n) * sizeof (u32)); \ 1146 } \ 1147 _nr = n; dev_priv->ring.space -= (n) * sizeof (u32); \ 1148 ring = dev_priv->ring.start; \ 1149 write = dev_priv->ring.tail; \ 1150 mask = dev_priv->ring.tail_mask; \ 1151 } while (*"\0") 1152 1153 #define ADVANCE_RING() do { \ 1154 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1155 DRM_ERROR( \ 1156 "ADVANCE_RING(): mismatch: nr: " \ 1157 "%x write: %x line: %d\n", \ 1158 ((dev_priv->ring.tail + _nr) & mask), \ 1159 write, __LINE__); \ 1160 } else \ 1161 dev_priv->ring.tail = write; \ 1162 } while (*"\0") 1163 1164 1165 #if defined(lint) || defined(__lint) 1166 #define COMMIT_RING() /* For lint clean */ 1167 #else 1168 #define COMMIT_RING() do { \ 1169 /* Flush writes to ring */ \ 1170 DRM_MEMORYBARRIER(); \ 1171 GET_RING_HEAD(dev_priv); \ 1172 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); \ 1173 /* read from PCI bus to ensure correct posting */ \ 1174 RADEON_READ(RADEON_CP_RB_RPTR); \ 1175 } while (*"\0") 1176 #endif 1177 1178 #define OUT_RING(x) do { \ 1179 ring[write++] = (x); \ 1180 write &= mask; \ 1181 } while (*"\0") 1182 1183 #define OUT_RING_REG(reg, val) do { \ 1184 OUT_RING(CP_PACKET0(reg, 0)); \ 1185 OUT_RING(val); \ 1186 } while (*"\0") 1187 1188 #define OUT_RING_TABLE(tab, sz) do { \ 1189 int _size = (sz); \ 1190 int *_tab = (int *)(uintptr_t)(tab); \ 1191 \ 1192 if (write + _size > mask) { \ 1193 int _i = (mask+1) - write; \ 1194 _size -= _i; \ 1195 while (_i > 0) { \ 1196 *(int *)(ring + write) = *_tab++; \ 1197 write++; \ 1198 _i--; \ 1199 } \ 1200 write = 0; \ 1201 _tab += _i; \ 1202 } \ 1203 while (_size > 0) { \ 1204 *(ring + write) = *_tab++; \ 1205 write++; \ 1206 _size--; \ 1207 } \ 1208 write &= mask; \ 1209 } while (*"\0") 1210 1211 #endif /* __RADEON_DRV_H__ */ 1212