1 /* BEGIN CSTYLED */ 2 3 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 4 */ 5 /* 6 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 7 * Copyright (c) 2009, Intel Corporation. 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sub license, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * 30 */ 31 32 /* 33 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 34 * Use is subject to license terms. 35 */ 36 37 #include "drmP.h" 38 #include "drm.h" 39 #include "i915_drm.h" 40 #include "i915_drv.h" 41 42 43 #define MAX_NOPID ((u32)~0) 44 45 /** 46 * Interrupts that are always left unmasked. 47 * 48 * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 49 * we leave them always unmasked in IMR and then control enabling them through 50 * PIPESTAT alone. 51 */ 52 53 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ 54 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 55 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 56 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 57 58 /** Interrupts that we mask and unmask at runtime. */ 59 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) 60 61 /** These are all of the interrupts used by the driver */ 62 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \ 63 I915_INTERRUPT_ENABLE_VAR) 64 65 static inline void 66 i915_enable_irq(drm_i915_private_t *dev_priv, uint32_t mask) 67 { 68 if ((dev_priv->irq_mask_reg & mask) != 0) { 69 dev_priv->irq_mask_reg &= ~mask; 70 I915_WRITE(IMR, dev_priv->irq_mask_reg); 71 (void) I915_READ(IMR); 72 } 73 } 74 75 static inline void 76 i915_disable_irq(drm_i915_private_t *dev_priv, uint32_t mask) 77 { 78 if ((dev_priv->irq_mask_reg & mask) != mask) { 79 dev_priv->irq_mask_reg |= mask; 80 I915_WRITE(IMR, dev_priv->irq_mask_reg); 81 (void) I915_READ(IMR); 82 } 83 } 84 85 static inline uint32_t 86 i915_pipestat(int pipe) 87 { 88 if (pipe == 0) 89 return PIPEASTAT; 90 if (pipe == 1) 91 return PIPEBSTAT; 92 return 0; 93 } 94 95 void 96 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, uint32_t mask) 97 { 98 if ((dev_priv->pipestat[pipe] & mask) != mask) { 99 u32 reg = i915_pipestat(pipe); 100 101 dev_priv->pipestat[pipe] |= mask; 102 /* Enable the interrupt, clear any pending status */ 103 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 104 (void) I915_READ(reg); 105 } 106 } 107 108 void 109 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 110 { 111 if ((dev_priv->pipestat[pipe] & mask) != 0) { 112 u32 reg = i915_pipestat(pipe); 113 114 dev_priv->pipestat[pipe] &= ~mask; 115 I915_WRITE(reg, dev_priv->pipestat[pipe]); 116 (void) I915_READ(reg); 117 } 118 } 119 120 /** 121 * i915_pipe_enabled - check if a pipe is enabled 122 * @dev: DRM device 123 * @pipe: pipe to check 124 * 125 * Reading certain registers when the pipe is disabled can hang the chip. 126 * Use this routine to make sure the PLL is running and the pipe is active 127 * before reading such registers if unsure. 128 */ 129 static int 130 i915_pipe_enabled(struct drm_device *dev, int pipe) 131 { 132 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 133 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; 134 135 if (I915_READ(pipeconf) & PIPEACONF_ENABLE) 136 return 1; 137 138 return 0; 139 } 140 141 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 142 { 143 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 144 unsigned long high_frame; 145 unsigned long low_frame; 146 u32 high1, high2, low, count; 147 148 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; 149 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 150 151 if (!i915_pipe_enabled(dev, pipe)) { 152 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); 153 return 0; 154 } 155 156 /* 157 * High & low register fields aren't synchronized, so make sure 158 * we get a low value that's stable across two reads of the high 159 * register. 160 */ 161 do { 162 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 163 PIPE_FRAME_HIGH_SHIFT); 164 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 165 PIPE_FRAME_LOW_SHIFT); 166 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 167 PIPE_FRAME_HIGH_SHIFT); 168 } while (high1 != high2); 169 170 count = (high1 << 8) | low; 171 172 return count; 173 } 174 175 /** 176 * i915_capture_error_state - capture an error record for later analysis 177 * @dev: drm device 178 * 179 * Should be called when an error is detected (either a hang or an error 180 * interrupt) to capture error state from the time of the error. Fills 181 * out a structure which becomes available in debugfs for user level tools 182 * to pick up. 183 */ 184 static void i915_capture_error_state(struct drm_device *dev) 185 { 186 struct drm_i915_private *dev_priv = dev->dev_private; 187 struct drm_i915_error_state *error; 188 189 spin_lock_irqsave(&dev_priv->error_lock, flags); 190 #if 0 191 if (dev_priv->first_error) 192 goto out; 193 #endif 194 error = drm_alloc(sizeof(*error), DRM_MEM_DRIVER); 195 if (!error) { 196 DRM_DEBUG("out ot memory, not capturing error state\n"); 197 goto out; 198 } 199 200 error->eir = I915_READ(EIR); 201 error->pgtbl_er = I915_READ(PGTBL_ER); 202 error->pipeastat = I915_READ(PIPEASTAT); 203 error->pipebstat = I915_READ(PIPEBSTAT); 204 error->instpm = I915_READ(INSTPM); 205 if (!IS_I965G(dev)) { 206 error->ipeir = I915_READ(IPEIR); 207 error->ipehr = I915_READ(IPEHR); 208 error->instdone = I915_READ(INSTDONE); 209 error->acthd = I915_READ(ACTHD); 210 } else { 211 error->ipeir = I915_READ(IPEIR_I965); 212 error->ipehr = I915_READ(IPEHR_I965); 213 error->instdone = I915_READ(INSTDONE_I965); 214 error->instps = I915_READ(INSTPS); 215 error->instdone1 = I915_READ(INSTDONE1); 216 error->acthd = I915_READ(ACTHD_I965); 217 } 218 219 (void) uniqtime(&error->time); 220 221 dev_priv->first_error = error; 222 223 DRM_DEBUG("Time: %ld s %ld us\n", error->time.tv_sec, 224 error->time.tv_usec); 225 DRM_DEBUG("EIR: 0x%08x\n", error->eir); 226 DRM_DEBUG(" PGTBL_ER: 0x%08x\n", error->pgtbl_er); 227 DRM_DEBUG(" INSTPM: 0x%08x\n", error->instpm); 228 DRM_DEBUG(" IPEIR: 0x%08x\n", error->ipeir); 229 DRM_DEBUG(" IPEHR: 0x%08x\n", error->ipehr); 230 DRM_DEBUG(" INSTDONE: 0x%08x\n", error->instdone); 231 DRM_DEBUG(" ACTHD: 0x%08x\n", error->acthd); 232 DRM_DEBUG(" DMA_FADD_P: 0x%08x\n", I915_READ(0x2078)); 233 if (IS_I965G(dev)) { 234 DRM_DEBUG(" INSTPS: 0x%08x\n", error->instps); 235 DRM_DEBUG(" INSTDONE1: 0x%08x\n", error->instdone1); 236 } 237 drm_free(error, sizeof(*error), DRM_MEM_DRIVER); 238 out: 239 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 240 } 241 242 /** 243 * i915_handle_error - handle an error interrupt 244 * @dev: drm device 245 * 246 * Do some basic checking of regsiter state at error interrupt time and 247 * dump it to the syslog. Also call i915_capture_error_state() to make 248 * sure we get a record and make it available in debugfs. Fire a uevent 249 * so userspace knows something bad happened (should trigger collection 250 * of a ring dump etc.). 251 */ 252 void i915_handle_error(struct drm_device *dev) 253 { 254 struct drm_i915_private *dev_priv = dev->dev_private; 255 u32 eir = I915_READ(EIR); 256 u32 pipea_stats = I915_READ(PIPEASTAT); 257 u32 pipeb_stats = I915_READ(PIPEBSTAT); 258 259 i915_capture_error_state(dev); 260 261 DRM_DEBUG("render error detected, EIR: 0x%08x\n", 262 eir); 263 264 if (IS_G4X(dev)) { 265 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 266 u32 ipeir = I915_READ(IPEIR_I965); 267 268 DRM_DEBUG(" IPEIR: 0x%08x\n", 269 I915_READ(IPEIR_I965)); 270 DRM_DEBUG(" IPEHR: 0x%08x\n", 271 I915_READ(IPEHR_I965)); 272 DRM_DEBUG(" INSTDONE: 0x%08x\n", 273 I915_READ(INSTDONE_I965)); 274 DRM_DEBUG(" INSTPS: 0x%08x\n", 275 I915_READ(INSTPS)); 276 DRM_DEBUG(" INSTDONE1: 0x%08x\n", 277 I915_READ(INSTDONE1)); 278 DRM_DEBUG(" ACTHD: 0x%08x\n", 279 I915_READ(ACTHD_I965)); 280 I915_WRITE(IPEIR_I965, ipeir); 281 (void)I915_READ(IPEIR_I965); 282 } 283 if (eir & GM45_ERROR_PAGE_TABLE) { 284 u32 pgtbl_err = I915_READ(PGTBL_ER); 285 DRM_DEBUG("page table error\n"); 286 DRM_DEBUG(" PGTBL_ER: 0x%08x\n", 287 pgtbl_err); 288 I915_WRITE(PGTBL_ER, pgtbl_err); 289 (void)I915_READ(PGTBL_ER); 290 } 291 } 292 293 if (IS_I9XX(dev)) { 294 if (eir & I915_ERROR_PAGE_TABLE) { 295 u32 pgtbl_err = I915_READ(PGTBL_ER); 296 DRM_DEBUG("page table error\n"); 297 DRM_DEBUG("PGTBL_ER: 0x%08x\n", 298 pgtbl_err); 299 I915_WRITE(PGTBL_ER, pgtbl_err); 300 (void)I915_READ(PGTBL_ER); 301 } 302 } 303 304 if (eir & I915_ERROR_MEMORY_REFRESH) { 305 DRM_DEBUG("memory refresh error\n"); 306 DRM_DEBUG("PIPEASTAT: 0x%08x\n", 307 pipea_stats); 308 DRM_DEBUG("PIPEBSTAT: 0x%08x\n", 309 pipeb_stats); 310 /* pipestat has already been acked */ 311 } 312 if (eir & I915_ERROR_INSTRUCTION) { 313 DRM_DEBUG("instruction error\n"); 314 DRM_DEBUG(" INSTPM: 0x%08x\n", 315 I915_READ(INSTPM)); 316 if (!IS_I965G(dev)) { 317 u32 ipeir = I915_READ(IPEIR); 318 319 DRM_DEBUG(" IPEIR: 0x%08x\n", 320 I915_READ(IPEIR)); 321 DRM_DEBUG(" IPEHR: 0x%08x\n", 322 I915_READ(IPEHR)); 323 DRM_DEBUG(" INSTDONE: 0x%08x\n", 324 I915_READ(INSTDONE)); 325 DRM_DEBUG(" ACTHD: 0x%08x\n", 326 I915_READ(ACTHD)); 327 I915_WRITE(IPEIR, ipeir); 328 (void)I915_READ(IPEIR); 329 } else { 330 u32 ipeir = I915_READ(IPEIR_I965); 331 332 DRM_DEBUG(" IPEIR: 0x%08x\n", 333 I915_READ(IPEIR_I965)); 334 DRM_DEBUG(" IPEHR: 0x%08x\n", 335 I915_READ(IPEHR_I965)); 336 DRM_DEBUG(" INSTDONE: 0x%08x\n", 337 I915_READ(INSTDONE_I965)); 338 DRM_DEBUG(" INSTPS: 0x%08x\n", 339 I915_READ(INSTPS)); 340 DRM_DEBUG(" INSTDONE1: 0x%08x\n", 341 I915_READ(INSTDONE1)); 342 DRM_DEBUG(" ACTHD: 0x%08x\n", 343 I915_READ(ACTHD_I965)); 344 I915_WRITE(IPEIR_I965, ipeir); 345 (void)I915_READ(IPEIR_I965); 346 } 347 } 348 349 I915_WRITE(EIR, eir); 350 (void)I915_READ(EIR); 351 eir = I915_READ(EIR); 352 if (eir) { 353 /* 354 * some errors might have become stuck, 355 * mask them. 356 */ 357 DRM_DEBUG("EIR stuck: 0x%08x, masking\n", eir); 358 I915_WRITE(EMR, I915_READ(EMR) | eir); 359 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 360 } 361 362 } 363 364 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 365 { 366 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 367 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 368 369 if (!i915_pipe_enabled(dev, pipe)) { 370 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); 371 return 0; 372 } 373 374 return I915_READ(reg); 375 } 376 377 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 378 { 379 drm_device_t *dev = (drm_device_t *) (void *) arg; 380 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 381 u32 iir; 382 u32 pipea_stats = 0, pipeb_stats = 0; 383 int vblank = 0; 384 385 iir = I915_READ(IIR); 386 387 if (iir == 0) { 388 return IRQ_NONE; 389 } 390 start: 391 392 if (dev_priv->sarea_priv) { 393 if (dev_priv->hw_status_page) 394 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 395 } 396 397 I915_WRITE(IIR, iir); 398 399 (void) I915_READ(IIR); /* Flush posted writes */ 400 401 402 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 403 i915_handle_error(dev); 404 405 if (iir & I915_USER_INTERRUPT) { 406 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); 407 DRM_WAKEUP(&dev_priv->irq_queue); 408 } 409 410 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { 411 pipea_stats = I915_READ(PIPEASTAT); 412 413 /* The vblank interrupt gets enabled even if we didn't ask for 414 it, so make sure it's shut down again */ 415 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)) 416 pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | 417 PIPE_VBLANK_INTERRUPT_ENABLE); 418 else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| 419 PIPE_VBLANK_INTERRUPT_STATUS)) 420 { 421 vblank++; 422 drm_handle_vblank(dev, 0); 423 } 424 425 I915_WRITE(PIPEASTAT, pipea_stats); 426 } 427 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { 428 pipeb_stats = I915_READ(PIPEBSTAT); 429 430 /* The vblank interrupt gets enabled even if we didn't ask for 431 it, so make sure it's shut down again */ 432 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)) 433 pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | 434 PIPE_VBLANK_INTERRUPT_ENABLE); 435 else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| 436 PIPE_VBLANK_INTERRUPT_STATUS)) 437 { 438 vblank++; 439 drm_handle_vblank(dev, 1); 440 } 441 442 I915_WRITE(PIPEBSTAT, pipeb_stats); 443 } 444 return IRQ_HANDLED; 445 446 } 447 448 int i915_emit_irq(drm_device_t * dev) 449 { 450 451 drm_i915_private_t *dev_priv = dev->dev_private; 452 RING_LOCALS; 453 454 i915_kernel_lost_context(dev); 455 456 dev_priv->counter++; 457 if (dev_priv->counter > 0x7FFFFFFFUL) 458 dev_priv->counter = 1; 459 if (dev_priv->sarea_priv) 460 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 461 462 #if defined(__i386) 463 if (IS_GM45(dev)) { 464 BEGIN_LP_RING(3); 465 OUT_RING(MI_STORE_DWORD_INDEX); 466 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 467 OUT_RING(dev_priv->counter); 468 ADVANCE_LP_RING(); 469 470 (void) READ_BREADCRUMB(dev_priv); 471 BEGIN_LP_RING(2); 472 OUT_RING(0); 473 OUT_RING(MI_USER_INTERRUPT); 474 ADVANCE_LP_RING(); 475 } else { 476 #endif /* __i386 */ 477 BEGIN_LP_RING(4); 478 OUT_RING(MI_STORE_DWORD_INDEX); 479 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 480 OUT_RING(dev_priv->counter); 481 OUT_RING(MI_USER_INTERRUPT); 482 ADVANCE_LP_RING(); 483 #if defined(__i386) 484 } 485 #endif /* __i386 */ 486 487 #if defined(__i386) 488 if (IS_I965GM(dev) || IS_GM45(dev)) 489 #else 490 if (IS_I965GM(dev)) 491 #endif /* __i386 */ 492 { 493 (void) READ_BREADCRUMB(dev_priv); 494 BEGIN_LP_RING(2); 495 OUT_RING(0); 496 OUT_RING(0); 497 ADVANCE_LP_RING(); 498 (void) READ_BREADCRUMB(dev_priv); 499 } 500 501 return dev_priv->counter; 502 } 503 504 void i915_user_irq_on(struct drm_device *dev) 505 { 506 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 507 spin_lock(&dev_priv->user_irq_lock); 508 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)){ 509 i915_enable_irq(dev_priv, I915_USER_INTERRUPT); 510 } 511 spin_unlock(&dev_priv->user_irq_lock); 512 513 } 514 515 void i915_user_irq_off(struct drm_device *dev) 516 { 517 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 518 spin_lock(&dev_priv->user_irq_lock); 519 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { 520 i915_disable_irq(dev_priv, I915_USER_INTERRUPT); 521 } 522 spin_unlock(&dev_priv->user_irq_lock); 523 } 524 525 526 static int i915_wait_irq(drm_device_t * dev, int irq_nr) 527 { 528 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 529 int ret = 0; 530 531 if (!dev_priv) { 532 DRM_ERROR("called with no initialization\n"); 533 return -EINVAL; 534 } 535 536 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 537 if (dev_priv->sarea_priv) { 538 dev_priv->sarea_priv->last_dispatch = 539 READ_BREADCRUMB(dev_priv); 540 } 541 return 0; 542 } 543 DRM_DEBUG("i915_wait_irq: irq_nr=%d breadcrumb=%d\n", irq_nr, READ_BREADCRUMB(dev_priv)); 544 i915_user_irq_on(dev); 545 DRM_WAIT_ON(ret, &dev_priv->irq_queue, 3 * DRM_HZ, 546 READ_BREADCRUMB(dev_priv) >= irq_nr); 547 i915_user_irq_off(dev); 548 549 if (ret == EBUSY) { 550 DRM_DEBUG("%d: EBUSY -- rec: %d emitted: %d\n", 551 ret, 552 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 553 } 554 555 if (dev_priv->sarea_priv) 556 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 557 558 return ret; 559 } 560 561 562 /* Needs the lock as it touches the ring. 563 */ 564 /*ARGSUSED*/ 565 int i915_irq_emit(DRM_IOCTL_ARGS) 566 { 567 DRM_DEVICE; 568 drm_i915_private_t *dev_priv = dev->dev_private; 569 drm_i915_irq_emit_t emit; 570 int result; 571 572 LOCK_TEST_WITH_RETURN(dev, fpriv); 573 574 if (!dev_priv) { 575 DRM_ERROR("%s called with no initialization\n", __FUNCTION__); 576 return (EINVAL); 577 } 578 579 580 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) { 581 drm_i915_irq_emit32_t irq_emit32; 582 583 DRM_COPYFROM_WITH_RETURN(&irq_emit32, 584 (drm_i915_irq_emit32_t __user *) data, 585 sizeof (drm_i915_irq_emit32_t)); 586 emit.irq_seq = (int __user *)(uintptr_t)irq_emit32.irq_seq; 587 } else 588 DRM_COPYFROM_WITH_RETURN(&emit, 589 (drm_i915_irq_emit_t __user *) data, sizeof(emit)); 590 591 spin_lock(&dev->struct_mutex); 592 result = i915_emit_irq(dev); 593 spin_unlock(&dev->struct_mutex); 594 595 if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { 596 DRM_ERROR("copy_to_user\n"); 597 return (EFAULT); 598 } 599 600 return 0; 601 } 602 603 /* Doesn't need the hardware lock. 604 */ 605 /*ARGSUSED*/ 606 int i915_irq_wait(DRM_IOCTL_ARGS) 607 { 608 DRM_DEVICE; 609 drm_i915_private_t *dev_priv = dev->dev_private; 610 drm_i915_irq_wait_t irqwait; 611 612 if (!dev_priv) { 613 DRM_ERROR("%s called with no initialization\n", __FUNCTION__); 614 return (EINVAL); 615 } 616 617 DRM_COPYFROM_WITH_RETURN(&irqwait, 618 (drm_i915_irq_wait_t __user *) data, sizeof(irqwait)); 619 620 return i915_wait_irq(dev, irqwait.irq_seq); 621 } 622 623 int i915_enable_vblank(struct drm_device *dev, int pipe) 624 { 625 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 626 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 627 u32 pipeconf; 628 629 pipeconf = I915_READ(pipeconf_reg); 630 if (!(pipeconf & PIPEACONF_ENABLE)) 631 return -EINVAL; 632 633 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 634 if (IS_I965G(dev)) 635 i915_enable_pipestat(dev_priv, pipe, 636 PIPE_START_VBLANK_INTERRUPT_ENABLE); 637 else 638 i915_enable_pipestat(dev_priv, pipe, 639 PIPE_VBLANK_INTERRUPT_ENABLE); 640 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 641 642 return 0; 643 } 644 645 void i915_disable_vblank(struct drm_device *dev, int pipe) 646 { 647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 648 649 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 650 i915_disable_pipestat(dev_priv, pipe, 651 PIPE_VBLANK_INTERRUPT_ENABLE | 652 PIPE_START_VBLANK_INTERRUPT_ENABLE); 653 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 654 } 655 656 /* Set the vblank monitor pipe 657 */ 658 /*ARGSUSED*/ 659 int i915_vblank_pipe_set(DRM_IOCTL_ARGS) 660 { 661 DRM_DEVICE; 662 drm_i915_private_t *dev_priv = dev->dev_private; 663 664 if (!dev_priv) { 665 DRM_ERROR("called with no initialization\n"); 666 return (-EINVAL); 667 } 668 669 return (0); 670 } 671 672 /*ARGSUSED*/ 673 int i915_vblank_pipe_get(DRM_IOCTL_ARGS) 674 { 675 DRM_DEVICE; 676 drm_i915_private_t *dev_priv = dev->dev_private; 677 drm_i915_vblank_pipe_t pipe; 678 679 if (!dev_priv) { 680 DRM_ERROR("called with no initialization\n"); 681 return -EINVAL; 682 } 683 684 DRM_COPYFROM_WITH_RETURN(&pipe, (drm_i915_vblank_pipe_t __user *)data, sizeof (pipe)); 685 686 pipe.pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 687 688 return 0; 689 } 690 691 /** 692 * Schedule buffer swap at given vertical blank. 693 */ 694 /*ARGSUSED*/ 695 int i915_vblank_swap(DRM_IOCTL_ARGS) 696 { 697 /* The delayed swap mechanism was fundamentally racy, and has been 698 * removed. The model was that the client requested a delayed flip/swap 699 * from the kernel, then waited for vblank before continuing to perform 700 * rendering. The problem was that the kernel might wake the client 701 * up before it dispatched the vblank swap (since the lock has to be 702 * held while touching the ringbuffer), in which case the client would 703 * clear and start the next frame before the swap occurred, and 704 * flicker would occur in addition to likely missing the vblank. 705 * 706 * In the absence of this ioctl, userland falls back to a correct path 707 * of waiting for a vblank, then dispatching the swap on its own. 708 * Context switching to userland and back is plenty fast enough for 709 * meeting the requirements of vblank swapping. 710 */ 711 return -EINVAL; 712 713 } 714 715 /* drm_dma.h hooks 716 */ 717 int i915_driver_irq_preinstall(drm_device_t * dev) 718 { 719 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 720 721 if (!dev_priv->mmio_map) 722 return -EINVAL; 723 724 I915_WRITE16(HWSTAM, 0xeffe); 725 I915_WRITE(PIPEASTAT, 0); 726 I915_WRITE(PIPEBSTAT, 0); 727 I915_WRITE(IMR, 0xffffffff); 728 I915_WRITE16(IER, 0x0); 729 (void) I915_READ(IER); 730 731 return 0; 732 } 733 734 void i915_driver_irq_postinstall(drm_device_t * dev) 735 { 736 int error_mask; 737 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 738 739 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 740 741 /* Unmask the interrupts that we always want on. */ 742 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; 743 744 dev_priv->pipestat[0] = 0; 745 dev_priv->pipestat[1] = 0; 746 747 /* 748 * Enable some error detection, note the instruction error mask 749 * bit is reserved, so we leave it masked. 750 */ 751 if (IS_G4X(dev)) { 752 error_mask = ~(GM45_ERROR_PAGE_TABLE | 753 GM45_ERROR_MEM_PRIV | 754 GM45_ERROR_CP_PRIV | 755 I915_ERROR_MEMORY_REFRESH); 756 } else { 757 error_mask = ~(I915_ERROR_PAGE_TABLE | 758 I915_ERROR_MEMORY_REFRESH); 759 } 760 I915_WRITE(EMR, error_mask); 761 762 /* Disable pipe interrupt enables, clear pending pipe status */ 763 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 764 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 765 /* Clear pending interrupt status */ 766 I915_WRITE(IIR, I915_READ(IIR)); 767 768 I915_WRITE(IMR, dev_priv->irq_mask_reg); 769 I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); 770 (void) I915_READ(IER); 771 772 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue, DRM_INTR_PRI(dev)); 773 774 return; 775 } 776 777 void i915_driver_irq_uninstall(drm_device_t * dev) 778 { 779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 780 if ((!dev_priv) || (dev->irq_enabled == 0)) 781 return; 782 783 dev_priv->vblank_pipe = 0; 784 785 I915_WRITE(HWSTAM, 0xffffffff); 786 I915_WRITE(PIPEASTAT, 0); 787 I915_WRITE(PIPEBSTAT, 0); 788 I915_WRITE(IMR, 0xffffffff); 789 I915_WRITE(IER, 0x0); 790 791 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 792 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 793 I915_WRITE(IIR, I915_READ(IIR)); 794 795 DRM_FINI_WAITQUEUE(&dev_priv->irq_queue); 796 } 797