xref: /titanic_41/usr/src/uts/intel/io/drm/i915_irq.c (revision 257873cfc1dd3337766407f80397db60a56f2f5a)
1 /* BEGIN CSTYLED */
2 
3 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4  */
5 /*
6  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7  * All Rights Reserved.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the
11  * "Software"), to deal in the Software without restriction, including
12  * without limitation the rights to use, copy, modify, merge, publish,
13  * distribute, sub license, and/or sell copies of the Software, and to
14  * permit persons to whom the Software is furnished to do so, subject to
15  * the following conditions:
16  *
17  * The above copyright notice and this permission notice (including the
18  * next paragraph) shall be included in all copies or substantial portions
19  * of the Software.
20  *
21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
22  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
24  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
25  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
26  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
27  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28  *
29  */
30 
31 /*
32  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
33  * Use is subject to license terms.
34  */
35 
36 #include "drmP.h"
37 #include "drm.h"
38 #include "i915_drm.h"
39 #include "i915_drv.h"
40 
41 #define USER_INT_FLAG (1<<1)
42 #define VSYNC_PIPEB_FLAG (1<<5)
43 #define VSYNC_PIPEA_FLAG (1<<7)
44 
45 #define MAX_NOPID ((u32)~0)
46 
47 /**
48  * Emit blits for scheduled buffer swaps.
49  *
50  * This function will be called with the HW lock held.
51  */
52 static void i915_vblank_tasklet(drm_device_t *dev)
53 {
54 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
55 	/* LINTED E_FUNC_VAR_UNUSED */
56 	unsigned long irqflags;
57 	struct list_head *list, *tmp, hits, *hit;
58 	int nhits, slice[2], upper[2], lower[2], i;
59 	unsigned counter[2] = { atomic_read(&dev->vbl_received),
60 				atomic_read(&dev->vbl_received2) };
61 	drm_drawable_info_t *drw;
62 	drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
63 	u32 cpp = dev_priv->cpp;
64 	u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
65 				XY_SRC_COPY_BLT_WRITE_ALPHA |
66 				XY_SRC_COPY_BLT_WRITE_RGB)
67 			     : XY_SRC_COPY_BLT_CMD;
68 	u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
69 			  (cpp << 23) | (1 << 24);
70 	RING_LOCALS;
71 
72 	DRM_DEBUG("%s\n", __FUNCTION__);
73 
74 	INIT_LIST_HEAD(&hits);
75 
76 	nhits = 0;
77 	spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
78 
79 	/* Find buffer swaps scheduled for this vertical blank */
80 	list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
81 		drm_i915_vbl_swap_t *vbl_swap =
82 			list_entry(list, drm_i915_vbl_swap_t, head);
83 
84 		if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23))
85 			continue;
86 
87 		list_del(list);
88 		dev_priv->swaps_pending--;
89 
90 		spin_unlock(&dev_priv->swaps_lock);
91 		spin_lock(&dev->drw_lock);
92 
93 		drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
94 
95 		if (!drw) {
96 			spin_unlock(&dev->drw_lock);
97 			drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
98 			spin_lock(&dev_priv->swaps_lock);
99 			continue;
100 		}
101 
102 		list_for_each(hit, &hits) {
103 			drm_i915_vbl_swap_t *swap_cmp =
104 				list_entry(hit, drm_i915_vbl_swap_t, head);
105 			drm_drawable_info_t *drw_cmp =
106 				drm_get_drawable_info(dev, swap_cmp->drw_id);
107 
108 			if (drw_cmp &&
109 			    drw_cmp->rects[0].y1 > drw->rects[0].y1) {
110 				list_add_tail(list, hit);
111 				break;
112 			}
113 		}
114 
115 		spin_unlock(&dev->drw_lock);
116 
117 		/* List of hits was empty, or we reached the end of it */
118 		if (hit == &hits)
119 			list_add_tail(list, hits.prev);
120 
121 		nhits++;
122 
123 		spin_lock(&dev_priv->swaps_lock);
124 	}
125 
126 	if (nhits == 0) {
127 		spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
128 		return;
129 	}
130 
131 	spin_unlock(&dev_priv->swaps_lock);
132 
133 	i915_kernel_lost_context(dev);
134 
135 	BEGIN_LP_RING(6);
136 
137 	OUT_RING(GFX_OP_DRAWRECT_INFO);
138 	OUT_RING(0);
139 	OUT_RING(0);
140 	OUT_RING(sarea_priv->width | sarea_priv->height << 16);
141 	OUT_RING(sarea_priv->width | sarea_priv->height << 16);
142 	OUT_RING(0);
143 
144 	ADVANCE_LP_RING();
145 
146 	sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
147 
148 	upper[0] = upper[1] = 0;
149 	slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
150 	slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
151 	lower[0] = sarea_priv->pipeA_y + slice[0];
152 	lower[1] = sarea_priv->pipeB_y + slice[0];
153 
154 	spin_lock(&dev->drw_lock);
155 
156 	/* Emit blits for buffer swaps, partitioning both outputs into as many
157 	 * slices as there are buffer swaps scheduled in order to avoid tearing
158 	 * (based on the assumption that a single buffer swap would always
159 	 * complete before scanout starts).
160 	 */
161 	for (i = 0; i++ < nhits;
162 	     upper[0] = lower[0], lower[0] += slice[0],
163 	     upper[1] = lower[1], lower[1] += slice[1]) {
164 		if (i == nhits)
165 			lower[0] = lower[1] = sarea_priv->height;
166 
167 		list_for_each(hit, &hits) {
168 			drm_i915_vbl_swap_t *swap_hit =
169 				list_entry(hit, drm_i915_vbl_swap_t, head);
170 			drm_clip_rect_t *rect;
171 			int num_rects, pipe;
172 			unsigned short top, bottom;
173 
174 			drw = drm_get_drawable_info(dev, swap_hit->drw_id);
175 
176 			if (!drw)
177 				continue;
178 
179 			rect = drw->rects;
180 			pipe = swap_hit->pipe;
181 			top = upper[pipe];
182 			bottom = lower[pipe];
183 
184 			for (num_rects = drw->num_rects; num_rects--; rect++) {
185 				int y1 = max(rect->y1, top);
186 				int y2 = min(rect->y2, bottom);
187 
188 				if (y1 >= y2)
189 					continue;
190 
191 				BEGIN_LP_RING(8);
192 
193 				OUT_RING(cmd);
194 				OUT_RING(pitchropcpp);
195 				OUT_RING((y1 << 16) | rect->x1);
196 				OUT_RING((y2 << 16) | rect->x2);
197 				OUT_RING(sarea_priv->front_offset);
198 				OUT_RING((y1 << 16) | rect->x1);
199 				OUT_RING(pitchropcpp & 0xffff);
200 				OUT_RING(sarea_priv->back_offset);
201 
202 				ADVANCE_LP_RING();
203 			}
204 		}
205 	}
206 
207 	spin_unlock_irqrestore(&dev->drw_lock, irqflags);
208 
209 	list_for_each_safe(hit, tmp, &hits) {
210 		drm_i915_vbl_swap_t *swap_hit =
211 			list_entry(hit, drm_i915_vbl_swap_t, head);
212 
213 		list_del(hit);
214 
215 		drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
216 	}
217 }
218 
219 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
220 {
221 	drm_device_t *dev = (drm_device_t *) (void *)arg;
222 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
223 	u16 temp;
224 	u32 pipea_stats, pipeb_stats;
225 
226 	pipea_stats = I915_READ(I915REG_PIPEASTAT);
227 	pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
228 
229 	temp = I915_READ16(I915REG_INT_IDENTITY_R);
230 	temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
231 
232 #if 0
233 	DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
234 #endif
235         if (temp == 0)
236                 return IRQ_NONE;
237 
238 	I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
239 
240 	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
241 
242 	if (temp & USER_INT_FLAG) {
243 		DRM_WAKEUP(&dev_priv->irq_queue);
244 #ifdef I915_HAVE_FENCE
245 		i915_fence_handler(dev);
246 #endif
247 	}
248 
249 	if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
250 		int vblank_pipe = dev_priv->vblank_pipe;
251 
252 		if ((vblank_pipe &
253 		     (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
254 		    == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
255 			if (temp & VSYNC_PIPEA_FLAG)
256 				atomic_inc(&dev->vbl_received);
257 			if (temp & VSYNC_PIPEB_FLAG)
258 				atomic_inc(&dev->vbl_received2);
259 		} else if (((temp & VSYNC_PIPEA_FLAG) &&
260 			    (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
261 			   ((temp & VSYNC_PIPEB_FLAG) &&
262 			    (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
263 			atomic_inc(&dev->vbl_received);
264 
265 		DRM_WAKEUP(&dev->vbl_queue);
266 		drm_vbl_send_signals(dev);
267 
268 		if (dev_priv->swaps_pending > 0)
269 			drm_locked_tasklet(dev, i915_vblank_tasklet);
270 		I915_WRITE(I915REG_PIPEASTAT,
271 			pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
272 			I915_VBLANK_CLEAR);
273 		I915_WRITE(I915REG_PIPEBSTAT,
274 			pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
275 			I915_VBLANK_CLEAR);
276 	}
277 
278         return IRQ_HANDLED;
279 }
280 
281 int i915_emit_irq(drm_device_t * dev)
282 {
283 
284 	drm_i915_private_t *dev_priv = dev->dev_private;
285 	RING_LOCALS;
286 
287 	i915_kernel_lost_context(dev);
288 
289 	DRM_DEBUG("%s\n", __FUNCTION__);
290 
291 	dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
292 
293 	if (dev_priv->counter > 0x7FFFFFFFUL)
294 		 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
295 
296 	BEGIN_LP_RING(6);
297 	OUT_RING(CMD_STORE_DWORD_IDX);
298 	OUT_RING(BREADCRUMB_OFFSET << 2);
299 	OUT_RING(dev_priv->counter);
300 
301 	OUT_RING(0);
302 	OUT_RING(0);
303 	OUT_RING(GFX_OP_USER_INTERRUPT);
304 	ADVANCE_LP_RING();
305 
306 	return dev_priv->counter;
307 
308 
309 }
310 
311 void i915_user_irq_on(drm_i915_private_t *dev_priv)
312 {
313 	spin_lock(&dev_priv->user_irq_lock);
314 	if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
315 		dev_priv->irq_enable_reg |= USER_INT_FLAG;
316 		I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
317 	}
318 	spin_unlock(&dev_priv->user_irq_lock);
319 
320 }
321 
322 void i915_user_irq_off(drm_i915_private_t *dev_priv)
323 {
324 	spin_lock(&dev_priv->user_irq_lock);
325 	if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
326 		/*EMPTY*/;
327 		//		dev_priv->irq_enable_reg &= ~USER_INT_FLAG;
328 		//		I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
329 	}
330 	spin_unlock(&dev_priv->user_irq_lock);
331 }
332 
333 
334 static int i915_wait_irq(drm_device_t * dev, int irq_nr)
335 {
336 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
337 	int ret = 0;
338 
339 	DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr,
340 		  READ_BREADCRUMB(dev_priv));
341 
342 	if (READ_BREADCRUMB(dev_priv) >= irq_nr)
343 		return 0;
344 
345 	dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
346 
347 	i915_user_irq_on(dev_priv);
348 	DRM_WAIT_ON(ret, &dev_priv->irq_queue, 3 * DRM_HZ,
349 		    READ_BREADCRUMB(dev_priv) >= irq_nr);
350 	i915_user_irq_off(dev_priv);
351 
352 	if (ret == EBUSY) {
353 		DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n",
354 			  __FUNCTION__,
355 			  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
356 	}
357 
358 	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
359 	return ret;
360 }
361 
362 static int i915_driver_vblank_do_wait(drm_device_t *dev, unsigned int *sequence,
363 				      atomic_t *counter)
364 {
365 	drm_i915_private_t *dev_priv = dev->dev_private;
366 	unsigned int cur_vblank;
367 	int ret = 0;
368 
369 	if (!dev_priv) {
370 		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
371 		return (EINVAL);
372 	}
373 
374 	DRM_WAIT_ON(ret, &dev->vbl_queue, 3 * DRM_HZ,
375 		    (((cur_vblank = atomic_read(counter))
376 			- *sequence) <= (1<<23)));
377 
378 	*sequence = cur_vblank;
379 
380 	return ret;
381 }
382 
383 int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
384 {
385 	return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
386 }
387 
388 int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
389 {
390 	return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
391 }
392 
393 /* Needs the lock as it touches the ring.
394  */
395 /*ARGSUSED*/
396 int i915_irq_emit(DRM_IOCTL_ARGS)
397 {
398 	DRM_DEVICE;
399 	drm_i915_private_t *dev_priv = dev->dev_private;
400 	drm_i915_irq_emit_t emit;
401 	int result;
402 
403 	LOCK_TEST_WITH_RETURN(dev, fpriv);
404 
405 	if (!dev_priv) {
406 		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
407 		return (EINVAL);
408 	}
409 
410 	if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
411 		drm_i915_irq_emit32_t irq_emit32;
412 
413 		DRM_COPYFROM_WITH_RETURN(&irq_emit32,
414 			(drm_i915_irq_emit32_t __user *) data,
415 			sizeof (drm_i915_irq_emit32_t));
416 		emit.irq_seq = (int __user *)(uintptr_t)irq_emit32.irq_seq;
417 	} else
418 		DRM_COPYFROM_WITH_RETURN(&emit,
419 		    (drm_i915_irq_emit_t __user *) data, sizeof(emit));
420 
421 	result = i915_emit_irq(dev);
422 
423 	if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
424 		DRM_ERROR("copy_to_user\n");
425 		return (EFAULT);
426 	}
427 
428 	return 0;
429 }
430 
431 /* Doesn't need the hardware lock.
432  */
433 /*ARGSUSED*/
434 int i915_irq_wait(DRM_IOCTL_ARGS)
435 {
436 	DRM_DEVICE;
437 	drm_i915_private_t *dev_priv = dev->dev_private;
438 	drm_i915_irq_wait_t irqwait;
439 
440 	if (!dev_priv) {
441 		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
442 		return (EINVAL);
443 	}
444 
445 	DRM_COPYFROM_WITH_RETURN(&irqwait,
446 	    (drm_i915_irq_wait_t __user *) data, sizeof(irqwait));
447 
448 	return i915_wait_irq(dev, irqwait.irq_seq);
449 }
450 
451 static void i915_enable_interrupt (drm_device_t *dev)
452 {
453 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
454 
455 	dev_priv->irq_enable_reg = USER_INT_FLAG;
456 	if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
457 		dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
458 	if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
459 		dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
460 
461 	I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
462 	dev_priv->irq_enabled = 1;
463 }
464 
465 /* drm_dma.h hooks
466 */
467 void i915_driver_irq_preinstall(drm_device_t * dev)
468 {
469 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
470 
471 	I915_WRITE16(I915REG_HWSTAM, 0xeffe);
472 	I915_WRITE16(I915REG_INT_MASK_R, 0x0);
473 	I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
474 }
475 
476 void i915_driver_irq_postinstall(drm_device_t * dev)
477 {
478 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
479 
480 	mutex_init(&dev_priv->swaps_lock, NULL, MUTEX_DRIVER, NULL);
481 	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
482 	dev_priv->swaps_pending = 0;
483 
484 	if (!dev_priv->vblank_pipe)
485 		dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
486 
487 	mutex_init(&dev_priv->user_irq_lock, NULL, MUTEX_DRIVER, NULL);
488 	dev_priv->user_irq_refcount = 0;
489 
490 	if (!dev_priv->vblank_pipe)
491 		dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
492 
493 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue, DRM_INTR_PRI(dev));
494 
495 	i915_enable_interrupt(dev);
496 
497 
498 	/*
499 	 * Initialize the hardware status page IRQ location.
500 	 */
501 
502 	I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
503 }
504 
505 void i915_driver_irq_uninstall(drm_device_t * dev)
506 {
507 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
508 	u16 temp;
509 	if (!dev_priv)
510 		return;
511 
512 	dev_priv->irq_enabled = 0;
513 	I915_WRITE16(I915REG_HWSTAM, 0xffff);
514 	I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
515 	I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
516 
517 	temp = I915_READ16(I915REG_INT_IDENTITY_R);
518 	I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
519 
520 	DRM_FINI_WAITQUEUE(&dev_priv->irq_queue);
521 	mutex_destroy(&dev_priv->swaps_lock);
522 	mutex_destroy(&dev_priv->user_irq_lock);
523 
524 }
525