1 /* BEGIN CSTYLED */ 2 3 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5 /* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sub license, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * 30 */ 31 32 /* 33 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 34 * Use is subject to license terms. 35 */ 36 37 #ifndef _I915_DRV_H 38 #define _I915_DRV_H 39 40 /* General customization: 41 */ 42 43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 44 45 #define DRIVER_NAME "i915" 46 #define DRIVER_DESC "Intel Graphics" 47 #define DRIVER_DATE "20060929" 48 49 #if defined(__SVR4) && defined(__sun) 50 #define spinlock_t kmutex_t 51 #endif 52 53 #define I915_NUM_PIPE 2 54 55 /* Interface history: 56 * 57 * 1.1: Original. 58 * 1.2: Add Power Management 59 * 1.3: Add vblank support 60 * 1.4: Fix cmdbuffer path, add heap destroy 61 */ 62 #define DRIVER_MAJOR 1 63 #define DRIVER_MINOR 5 64 #define DRIVER_PATCHLEVEL 0 65 66 #if defined(__linux__) 67 #define I915_HAVE_FENCE 68 #define I915_HAVE_BUFFER 69 #endif 70 71 typedef struct _drm_i915_ring_buffer { 72 int tail_mask; 73 unsigned long Size; 74 u8 *virtual_start; 75 int head; 76 int tail; 77 int space; 78 drm_local_map_t map; 79 } drm_i915_ring_buffer_t; 80 81 struct mem_block { 82 struct mem_block *next; 83 struct mem_block *prev; 84 int start; 85 int size; 86 drm_file_t *filp; /* 0: free, -1: heap, other: real files */ 87 }; 88 89 typedef struct _drm_i915_vbl_swap { 90 struct list_head head; 91 drm_drawable_t drw_id; 92 unsigned int plane; 93 unsigned int sequence; 94 int flip; 95 } drm_i915_vbl_swap_t; 96 97 typedef struct s3_i915_private { 98 ddi_acc_handle_t saveHandle; 99 caddr_t saveAddr; 100 uint32_t pgtbl_ctl; 101 uint8_t saveLBB; 102 uint32_t saveDSPACNTR; 103 uint32_t saveDSPBCNTR; 104 uint32_t saveDSPARB; 105 uint32_t savePIPEACONF; 106 uint32_t savePIPEBCONF; 107 uint32_t savePIPEASRC; 108 uint32_t savePIPEBSRC; 109 uint32_t saveFPA0; 110 uint32_t saveFPA1; 111 uint32_t saveDPLL_A; 112 uint32_t saveDPLL_A_MD; 113 uint32_t saveHTOTAL_A; 114 uint32_t saveHBLANK_A; 115 uint32_t saveHSYNC_A; 116 uint32_t saveVTOTAL_A; 117 uint32_t saveVBLANK_A; 118 uint32_t saveVSYNC_A; 119 uint32_t saveBCLRPAT_A; 120 uint32_t saveDSPASTRIDE; 121 uint32_t saveDSPASIZE; 122 uint32_t saveDSPAPOS; 123 uint32_t saveDSPABASE; 124 uint32_t saveDSPASURF; 125 uint32_t saveDSPATILEOFF; 126 uint32_t savePFIT_PGM_RATIOS; 127 uint32_t saveBLC_PWM_CTL; 128 uint32_t saveBLC_PWM_CTL2; 129 uint32_t saveFPB0; 130 uint32_t saveFPB1; 131 uint32_t saveDPLL_B; 132 uint32_t saveDPLL_B_MD; 133 uint32_t saveHTOTAL_B; 134 uint32_t saveHBLANK_B; 135 uint32_t saveHSYNC_B; 136 uint32_t saveVTOTAL_B; 137 uint32_t saveVBLANK_B; 138 uint32_t saveVSYNC_B; 139 uint32_t saveBCLRPAT_B; 140 uint32_t saveDSPBSTRIDE; 141 uint32_t saveDSPBSIZE; 142 uint32_t saveDSPBPOS; 143 uint32_t saveDSPBBASE; 144 uint32_t saveDSPBSURF; 145 uint32_t saveDSPBTILEOFF; 146 uint32_t saveVCLK_DIVISOR_VGA0; 147 uint32_t saveVCLK_DIVISOR_VGA1; 148 uint32_t saveVCLK_POST_DIV; 149 uint32_t saveVGACNTRL; 150 uint32_t saveADPA; 151 uint32_t saveLVDS; 152 uint32_t saveLVDSPP_ON; 153 uint32_t saveLVDSPP_OFF; 154 uint32_t saveDVOA; 155 uint32_t saveDVOB; 156 uint32_t saveDVOC; 157 uint32_t savePP_ON; 158 uint32_t savePP_OFF; 159 uint32_t savePP_CONTROL; 160 uint32_t savePP_CYCLE; 161 uint32_t savePFIT_CONTROL; 162 uint32_t save_palette_a[256]; 163 uint32_t save_palette_b[256]; 164 uint32_t saveFBC_CFB_BASE; 165 uint32_t saveFBC_LL_BASE; 166 uint32_t saveFBC_CONTROL; 167 uint32_t saveFBC_CONTROL2; 168 uint32_t saveIER; 169 uint32_t saveIIR; 170 uint32_t saveIMR; 171 uint32_t saveD_STATE; 172 uint32_t saveCG_2D_DIS; 173 uint32_t saveMI_ARB_STATE; 174 uint32_t savePIPEASTAT; 175 uint32_t savePIPEBSTAT; 176 uint32_t saveCACHE_MODE_0; 177 uint32_t saveSWF0[16]; 178 uint32_t saveSWF1[16]; 179 uint32_t saveSWF2[3]; 180 uint8_t saveMSR; 181 uint8_t saveSR[8]; 182 uint8_t saveGR[25]; 183 uint8_t saveAR_INDEX; 184 uint8_t saveAR[21]; 185 uint8_t saveDACMASK; 186 uint8_t saveDACDATA[256*3]; /* 256 3-byte colors */ 187 uint8_t saveCR[37]; 188 } s3_i915_private_t; 189 190 typedef struct drm_i915_private { 191 struct drm_device *dev; 192 193 drm_local_map_t *sarea; 194 drm_local_map_t *mmio_map; 195 196 drm_i915_sarea_t *sarea_priv; 197 drm_i915_ring_buffer_t ring; 198 199 drm_dma_handle_t *status_page_dmah; 200 void *hw_status_page; 201 dma_addr_t dma_status_page; 202 uint32_t counter; 203 unsigned int status_gfx_addr; 204 drm_local_map_t hws_map; 205 206 unsigned int cpp; 207 208 wait_queue_head_t irq_queue; 209 atomic_t irq_received; 210 211 int tex_lru_log_granularity; 212 int allow_batchbuffer; 213 struct mem_block *agp_heap; 214 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 215 int vblank_pipe; 216 spinlock_t user_irq_lock; 217 int user_irq_refcount; 218 int fence_irq_on; 219 uint32_t irq_mask_reg; 220 int irq_enabled; 221 222 #ifdef I915_HAVE_FENCE 223 uint32_t flush_sequence; 224 uint32_t flush_flags; 225 uint32_t flush_pending; 226 uint32_t saved_flush_status; 227 #endif 228 #ifdef I915_HAVE_BUFFER 229 void *agp_iomap; 230 #endif 231 spinlock_t swaps_lock; 232 drm_i915_vbl_swap_t vbl_swaps; 233 unsigned int swaps_pending; 234 235 } drm_i915_private_t; 236 237 enum intel_chip_family { 238 CHIP_I8XX = 0x01, 239 CHIP_I9XX = 0x02, 240 CHIP_I915 = 0x04, 241 CHIP_I965 = 0x08, 242 }; 243 244 extern drm_ioctl_desc_t i915_ioctls[]; 245 extern int i915_max_ioctl; 246 247 /* i915_dma.c */ 248 extern void i915_kernel_lost_context(drm_device_t * dev); 249 extern int i915_driver_load(struct drm_device *, unsigned long flags); 250 extern int i915_driver_unload(struct drm_device *dev); 251 extern void i915_driver_lastclose(drm_device_t * dev); 252 extern void i915_driver_preclose(drm_device_t * dev, drm_file_t *filp); 253 extern int i915_driver_device_is_agp(drm_device_t * dev); 254 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 255 unsigned long arg); 256 extern int i915_emit_box(struct drm_device *dev, 257 struct drm_clip_rect __user *boxes, 258 int i, int DR1, int DR4); 259 extern void i915_emit_breadcrumb(struct drm_device *dev); 260 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); 261 extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); 262 263 264 /* i915_irq.c */ 265 extern int i915_irq_emit(DRM_IOCTL_ARGS); 266 extern int i915_irq_wait(DRM_IOCTL_ARGS); 267 268 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 269 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 270 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 271 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 272 extern int i915_driver_irq_preinstall(drm_device_t * dev); 273 extern void i915_driver_irq_postinstall(drm_device_t * dev); 274 extern void i915_driver_irq_uninstall(drm_device_t * dev); 275 extern int i915_emit_irq(drm_device_t * dev); 276 extern int i915_vblank_swap(DRM_IOCTL_ARGS); 277 extern void i915_user_irq_on(drm_i915_private_t *dev_priv); 278 extern void i915_user_irq_off(drm_i915_private_t *dev_priv); 279 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); 280 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); 281 282 /* i915_mem.c */ 283 extern int i915_mem_alloc(DRM_IOCTL_ARGS); 284 extern int i915_mem_free(DRM_IOCTL_ARGS); 285 extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 286 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); 287 extern void i915_mem_takedown(struct mem_block **heap); 288 extern void i915_mem_release(drm_device_t * dev, 289 drm_file_t *filp, struct mem_block *heap); 290 extern struct mem_block **get_heap(drm_i915_private_t *, int); 291 extern struct mem_block *find_block_by_proc(struct mem_block *, drm_file_t *); 292 extern void mark_block(drm_device_t *, struct mem_block *, int); 293 extern void free_block(struct mem_block *); 294 295 #ifdef I915_HAVE_FENCE 296 /* i915_fence.c */ 297 298 299 extern void i915_fence_handler(drm_device_t *dev); 300 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, 301 uint32_t flags, 302 uint32_t *sequence, 303 uint32_t *native_type); 304 extern void i915_poke_flush(drm_device_t *dev, uint32_t class); 305 extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); 306 #endif 307 308 #ifdef I915_HAVE_BUFFER 309 /* i915_buffer.c */ 310 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); 311 extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); 312 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); 313 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, 314 drm_mem_type_manager_t *man); 315 extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); 316 extern int i915_move(drm_buffer_object_t *bo, int evict, 317 int no_wait, drm_bo_mem_reg_t *new_mem); 318 319 #endif 320 321 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 322 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 323 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 324 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 325 #define S3_READ(reg) \ 326 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) 327 #define S3_WRITE(reg, val) \ 328 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) = (val) 329 330 #define I915_VERBOSE 0 331 #define I915_RING_VALIDATE 0 332 333 #if I915_RING_VALIDATE 334 void i915_ring_validate(struct drm_device *dev, const char *func, int line); 335 #define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 336 #else 337 #define I915_RING_DO_VALIDATE(dev) 338 #endif 339 340 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 341 volatile unsigned char *virt; 342 343 #if I915_VERBOSE 344 #define BEGIN_LP_RING(n) do { \ 345 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 346 I915_RING_DO_VALIDATE(dev); \ 347 if (dev_priv->ring.space < (n)*4) \ 348 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 349 outcount = 0; \ 350 outring = dev_priv->ring.tail; \ 351 ringmask = dev_priv->ring.tail_mask; \ 352 virt = dev_priv->ring.virtual_start; \ 353 } while (*"\0") 354 #else 355 #define BEGIN_LP_RING(n) do { \ 356 I915_RING_DO_VALIDATE(dev); \ 357 if (dev_priv->ring.space < (n)*4) \ 358 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 359 outcount = 0; \ 360 outring = dev_priv->ring.tail; \ 361 ringmask = dev_priv->ring.tail_mask; \ 362 virt = dev_priv->ring.virtual_start; \ 363 } while (*"\0") 364 #endif 365 366 #if I915_VERBOSE 367 #define OUT_RING(n) do { \ 368 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 369 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 370 outcount++; \ 371 outring += 4; \ 372 outring &= ringmask; \ 373 } while (*"\0") 374 #else 375 #define OUT_RING(n) do { \ 376 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 377 outcount++; \ 378 outring += 4; \ 379 outring &= ringmask; \ 380 } while (*"\0") 381 #endif 382 383 #if I915_VERBOSE 384 #define ADVANCE_LP_RING() do { \ 385 DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 386 I915_RING_DO_VALIDATE(dev); \ 387 dev_priv->ring.tail = outring; \ 388 dev_priv->ring.space -= outcount * 4; \ 389 I915_WRITE(PRB0_TAIL, outring); \ 390 } while (*"\0") 391 #else 392 #define ADVANCE_LP_RING() do { \ 393 I915_RING_DO_VALIDATE(dev); \ 394 dev_priv->ring.tail = outring; \ 395 dev_priv->ring.space -= outcount * 4; \ 396 I915_WRITE(PRB0_TAIL, outring); \ 397 } while (*"\0") 398 #endif 399 400 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 401 402 /* Extended config space */ 403 #define LBB 0xf4 404 405 /* VGA stuff */ 406 407 #define VGA_ST01_MDA 0x3ba 408 #define VGA_ST01_CGA 0x3da 409 410 #define VGA_MSR_WRITE 0x3c2 411 #define VGA_MSR_READ 0x3cc 412 #define VGA_MSR_MEM_EN (1<<1) 413 #define VGA_MSR_CGA_MODE (1<<0) 414 415 #define VGA_SR_INDEX 0x3c4 416 #define VGA_SR_DATA 0x3c5 417 418 #define VGA_AR_INDEX 0x3c0 419 #define VGA_AR_VID_EN (1<<5) 420 #define VGA_AR_DATA_WRITE 0x3c0 421 #define VGA_AR_DATA_READ 0x3c1 422 423 #define VGA_GR_INDEX 0x3ce 424 #define VGA_GR_DATA 0x3cf 425 /* GR05 */ 426 #define VGA_GR_MEM_READ_MODE_SHIFT 3 427 #define VGA_GR_MEM_READ_MODE_PLANE 1 428 /* GR06 */ 429 #define VGA_GR_MEM_MODE_MASK 0xc 430 #define VGA_GR_MEM_MODE_SHIFT 2 431 #define VGA_GR_MEM_A0000_AFFFF 0 432 #define VGA_GR_MEM_A0000_BFFFF 1 433 #define VGA_GR_MEM_B0000_B7FFF 2 434 #define VGA_GR_MEM_B0000_BFFFF 3 435 436 #define VGA_DACMASK 0x3c6 437 #define VGA_DACRX 0x3c7 438 #define VGA_DACWX 0x3c8 439 #define VGA_DACDATA 0x3c9 440 441 #define VGA_CR_INDEX_MDA 0x3b4 442 #define VGA_CR_DATA_MDA 0x3b5 443 #define VGA_CR_INDEX_CGA 0x3d4 444 #define VGA_CR_DATA_CGA 0x3d5 445 446 447 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 448 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 449 #define CMD_REPORT_HEAD (7<<23) 450 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 451 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 452 453 #define INST_PARSER_CLIENT 0x00000000 454 #define INST_OP_FLUSH 0x02000000 455 #define INST_FLUSH_MAP_CACHE 0x00000001 456 457 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 458 #define MI_USER_INTERRUPT MI_INSTR(2, (0 << 29)) 459 #define MI_FLUSH (0x04 << 23) 460 #define MI_NO_WRITE_FLUSH (1 << 2) 461 #define MI_READ_FLUSH (1 << 0) 462 #define MI_EXE_FLUSH (1 << 1) 463 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 464 #define MI_STORE_DWORD_INDEX_SHIFT 2 465 466 #define BB1_START_ADDR_MASK (~0x7) 467 #define BB1_PROTECTED (1<<0) 468 #define BB1_UNPROTECTED (0<<0) 469 #define BB2_END_ADDR_MASK (~0x7) 470 471 #define I915REG_PGTBL_CTRL 0x2020 472 #define HWSTAM 0x02098 473 #define IIR 0x020a4 474 #define IMR 0x020a8 475 #define IER 0x020a0 476 #define INSTPM 0x020c0 477 #define ACTHD 0x020c8 478 #define PIPEASTAT 0x70024 479 #define PIPEBSTAT 0x71024 480 #define ACTHD_I965 0x02074 481 #define HWS_PGA 0x02080 482 483 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 484 #define I915_VBLANK_CLEAR (1UL<<1) 485 486 #define SRX_INDEX 0x3c4 487 #define SRX_DATA 0x3c5 488 #define SR01 1 489 #define SR01_SCREEN_OFF (1<<5) 490 491 #define PPCR 0x61204 492 #define PPCR_ON (1<<0) 493 494 #define DVOB 0x61140 495 #define DVOB_ON (1<<31) 496 #define DVOC 0x61160 497 #define DVOC_ON (1<<31) 498 #define LVDS 0x61180 499 #define LVDS_ON (1<<31) 500 501 #define ADPA 0x61100 502 #define ADPA_DPMS_MASK (~(3<<10)) 503 #define ADPA_DPMS_ON (0<<10) 504 #define ADPA_DPMS_SUSPEND (1<<10) 505 #define ADPA_DPMS_STANDBY (2<<10) 506 #define ADPA_DPMS_OFF (3<<10) 507 508 #ifdef NOPID 509 #undef NOPID 510 #endif 511 #define NOPID 0x2094 512 #define LP_RING 0x2030 513 #define HP_RING 0x2040 514 #define TAIL_ADDR 0x001FFFF8 515 #define HEAD_WRAP_COUNT 0xFFE00000 516 #define HEAD_WRAP_ONE 0x00200000 517 #define HEAD_ADDR 0x001FFFFC 518 #define RING_START 0x08 519 #define START_ADDR 0x0xFFFFF000 520 #define RING_LEN 0x0C 521 #define RING_NR_PAGES 0x001FF000 522 #define RING_REPORT_MASK 0x00000006 523 #define RING_REPORT_64K 0x00000002 524 #define RING_REPORT_128K 0x00000004 525 #define RING_NO_REPORT 0x00000000 526 #define RING_VALID_MASK 0x00000001 527 #define RING_VALID 0x00000001 528 #define RING_INVALID 0x00000000 529 #define PRB0_TAIL 0x02030 530 #define PRB0_HEAD 0x02034 531 #define PRB0_CTL 0x0203c 532 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 533 #define SC_UPDATE_SCISSOR (0x1<<1) 534 #define SC_ENABLE_MASK (0x1<<0) 535 #define SC_ENABLE (0x1<<0) 536 537 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 538 #define SCI_YMIN_MASK (0xffff<<16) 539 #define SCI_XMIN_MASK (0xffff<<0) 540 #define SCI_YMAX_MASK (0xffff<<16) 541 #define SCI_XMAX_MASK (0xffff<<0) 542 543 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 544 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 545 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 546 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 547 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 548 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 549 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 550 551 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 552 553 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 554 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 555 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 556 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 557 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) 558 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) 559 560 #define MI_BATCH_BUFFER ((0x30<<23)|1) 561 #define MI_BATCH_BUFFER_START (0x31<<23) 562 #define MI_BATCH_BUFFER_END (0xA<<23) 563 #define MI_BATCH_NON_SECURE (1) 564 565 #define MI_BATCH_NON_SECURE_I965 (1<<8) 566 567 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 568 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 569 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 570 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 571 572 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 573 574 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 575 #define ASYNC_FLIP (1<<22) 576 #define DISPLAY_PLANE_A (0<<20) 577 #define DISPLAY_PLANE_B (1<<20) 578 579 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 580 581 #define BREADCRUMB_BITS 31 582 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) 583 584 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) 585 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 586 587 /* 588 * add here for S3 support 589 */ 590 #define DPLL_A 0x06014 591 #define DPLL_B 0x06018 592 # define DPLL_VCO_ENABLE 0x80000000 /* (1 << 31) */ 593 # define DPLL_DVO_HIGH_SPEED (1 << 30) 594 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 595 # define DPLL_VGA_MODE_DIS (1 << 28) 596 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 597 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 598 # define DPLL_MODE_MASK (3 << 26) 599 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 600 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 601 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 602 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 603 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 604 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 605 606 /** 607 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 608 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 609 */ 610 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 611 /** 612 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 613 * this field (only one bit may be set). 614 */ 615 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 616 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 617 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 618 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 619 # define PLL_REF_INPUT_DREFCLK (0 << 13) 620 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 621 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 622 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 623 # define PLL_REF_INPUT_MASK (3 << 13) 624 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 625 /* 626 * Parallel to Serial Load Pulse phase selection. 627 * Selects the phase for the 10X DPLL clock for the PCIe 628 * digital display port. The range is 4 to 13; 10 or more 629 * is just a flip delay. The default is 6 630 */ 631 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 632 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 633 634 /** 635 * SDVO multiplier for 945G/GM. Not used on 965. 636 * 637 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 638 */ 639 # define SDVO_MULTIPLIER_MASK 0x000000ff 640 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 641 # define SDVO_MULTIPLIER_SHIFT_VGA 0 642 643 /** @defgroup DPLL_MD 644 * @{ 645 */ 646 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 647 #define DPLL_A_MD 0x0601c 648 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 649 #define DPLL_B_MD 0x06020 650 /** 651 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 652 * 653 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 654 */ 655 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 656 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 657 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 658 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 659 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 660 /** 661 * SDVO/UDI pixel multiplier. 662 * 663 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 664 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 665 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 666 * dummy bytes in the datastream at an increased clock rate, with both sides of 667 * the link knowing how many bytes are fill. 668 * 669 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 670 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 671 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 672 * through an SDVO command. 673 * 674 * This register field has values of multiplication factor minus 1, with 675 * a maximum multiplier of 5 for SDVO. 676 */ 677 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 678 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 679 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 680 * This best be set to the default value (3) or the CRT won't work. No, 681 * I don't entirely understand what this does... 682 */ 683 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 684 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 685 /** @} */ 686 687 #define DPLL_TEST 0x606c 688 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 689 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 690 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 691 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 692 # define DPLLB_TEST_N_BYPASS (1 << 19) 693 # define DPLLB_TEST_M_BYPASS (1 << 18) 694 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 695 # define DPLLA_TEST_N_BYPASS (1 << 3) 696 # define DPLLA_TEST_M_BYPASS (1 << 2) 697 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 698 699 /* 700 * Palette registers 701 */ 702 #define PALETTE_A 0x0a000 703 #define PALETTE_B 0x0a800 704 705 #define FPA0 0x06040 706 #define FPA1 0x06044 707 #define FPB0 0x06048 708 #define FPB1 0x0604c 709 710 #define D_STATE 0x6104 711 #define CG_2D_DIS 0x6200 712 #define CG_3D_DIS 0x6204 713 714 #define MI_ARB_STATE 0x20e4 715 716 /* 717 * Cache mode 0 reg. 718 * - Manipulating render cache behaviour is central 719 * to the concept of zone rendering, tuning this reg can help avoid 720 * unnecessary render cache reads and even writes (for z/stencil) 721 * at beginning and end of scene. 722 * 723 * - To change a bit, write to this reg with a mask bit set and the 724 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. 725 */ 726 #define CACHE_MODE_0 0x2120 727 728 /* I830 CRTC registers */ 729 #define HTOTAL_A 0x60000 730 #define HBLANK_A 0x60004 731 #define HSYNC_A 0x60008 732 #define VTOTAL_A 0x6000c 733 #define VBLANK_A 0x60010 734 #define VSYNC_A 0x60014 735 #define PIPEASRC 0x6001c 736 #define BCLRPAT_A 0x60020 737 #define VSYNCSHIFT_A 0x60028 738 739 #define HTOTAL_B 0x61000 740 #define HBLANK_B 0x61004 741 #define HSYNC_B 0x61008 742 #define VTOTAL_B 0x6100c 743 #define VBLANK_B 0x61010 744 #define VSYNC_B 0x61014 745 #define PIPEBSRC 0x6101c 746 #define BCLRPAT_B 0x61020 747 #define VSYNCSHIFT_B 0x61028 748 749 #define DSPACNTR 0x70180 750 #define DSPBCNTR 0x71180 751 #define DISPLAY_PLANE_ENABLE (1<<31) 752 #define DISPLAY_PLANE_DISABLE 0 753 #define DISPPLANE_GAMMA_ENABLE (1<<30) 754 #define DISPPLANE_GAMMA_DISABLE 0 755 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 756 #define DISPPLANE_8BPP (0x2<<26) 757 #define DISPPLANE_15_16BPP (0x4<<26) 758 #define DISPPLANE_16BPP (0x5<<26) 759 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 760 #define DISPPLANE_32BPP (0x7<<26) 761 #define DISPPLANE_STEREO_ENABLE (1<<25) 762 #define DISPPLANE_STEREO_DISABLE 0 763 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 764 #define DISPPLANE_SEL_PIPE_A 0 765 #define DISPPLANE_SEL_PIPE_B (1<<24) 766 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 767 #define DISPPLANE_SRC_KEY_DISABLE 0 768 #define DISPPLANE_LINE_DOUBLE (1<<20) 769 #define DISPPLANE_NO_LINE_DOUBLE 0 770 #define DISPPLANE_STEREO_POLARITY_FIRST 0 771 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 772 /* plane B only */ 773 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 774 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 775 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 776 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 777 778 #define DSPABASE 0x70184 779 #define DSPASTRIDE 0x70188 780 781 #define DSPBBASE 0x71184 782 #define DSPBADDR DSPBBASE 783 #define DSPBSTRIDE 0x71188 784 785 #define DSPAKEYVAL 0x70194 786 #define DSPAKEYMASK 0x70198 787 788 #define DSPAPOS 0x7018C /* reserved */ 789 #define DSPASIZE 0x70190 790 #define DSPBPOS 0x7118C 791 #define DSPBSIZE 0x71190 792 793 #define DSPASURF 0x7019C 794 #define DSPATILEOFF 0x701A4 795 796 #define DSPBSURF 0x7119C 797 #define DSPBTILEOFF 0x711A4 798 799 #define PIPEACONF 0x70008 800 #define PIPEACONF_ENABLE (1UL<<31) 801 #define PIPEACONF_DISABLE 0 802 #define PIPEACONF_DOUBLE_WIDE (1<<30) 803 #define I965_PIPECONF_ACTIVE (1<<30) 804 #define PIPEACONF_SINGLE_WIDE 0 805 #define PIPEACONF_PIPE_UNLOCKED 0 806 #define PIPEACONF_PIPE_LOCKED (1<<25) 807 #define PIPEACONF_PALETTE 0 808 #define PIPEACONF_GAMMA (1<<24) 809 #define PIPECONF_FORCE_BORDER (1<<25) 810 #define PIPECONF_PROGRESSIVE (0 << 21) 811 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 812 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 813 814 #define PIPEBCONF 0x71008 815 #define PIPEBCONF_ENABLE (1UL<<31) 816 #define PIPEBCONF_DISABLE 0 817 #define PIPEBCONF_DOUBLE_WIDE (1<<30) 818 #define PIPEBCONF_DISABLE 0 819 #define PIPEBCONF_GAMMA (1<<24) 820 #define PIPEBCONF_PALETTE 0 821 822 #define BLC_PWM_CTL 0x61254 823 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 824 825 #define BLC_PWM_CTL2 0x61250 826 827 #define PFIT_CONTROL 0x61230 828 #define PFIT_PGM_RATIOS 0x61234 829 830 /** 831 * Indicates that all dependencies of the panel are on: 832 * 833 * - PLL enabled 834 * - pipe enabled 835 * - LVDS/DVOB/DVOC on 836 */ 837 # define PP_READY (1 << 30) # define PP_SEQUENCE_NONE (0 << 28) 838 # define PP_SEQUENCE_ON (1 << 28) # define PP_SEQUENCE_OFF (2 << 28) 839 # define PP_SEQUENCE_MASK 0x30000000 840 #define PP_CONTROL 0x61204 841 # define POWER_TARGET_ON (1 << 0) 842 843 #define LVDSPP_ON 0x61208 844 #define LVDSPP_OFF 0x6120c 845 #define PP_CYCLE 0x61210 846 847 /* Framebuffer compression */ 848 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 849 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 850 #define FBC_CONTROL 0x03208 851 852 #define VGACNTRL 0x71400 853 854 #define VCLK_DIVISOR_VGA0 0x6000 855 #define VCLK_DIVISOR_VGA1 0x6004 856 #define VCLK_POST_DIV 0x6010 857 858 /* Framebuffer compression */ 859 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 860 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 861 #define FBC_CONTROL 0x03208 862 #define FBC_CTL_EN (1<<31) 863 #define FBC_CTL_PERIODIC (1<<30) 864 #define FBC_CTL_INTERVAL_SHIFT (16) 865 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 866 #define FBC_CTL_STRIDE_SHIFT (5) 867 #define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c 868 #define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 869 #define FBC_STAT_COMPRESSING (1<<31) 870 #define FBC_STAT_COMPRESSED (1<<30) 871 #define FBC_STAT_MODIFIED (1<<29) 872 #define FBC_STAT_CURRENT_LINE (1<<0) 873 #define FBC_CONTROL2 0x03214 874 #define FBC_CTL_FENCE_DBL (0<<4) 875 #define FBC_CTL_IDLE_IMM (0<<2) 876 #define FBC_CTL_IDLE_FULL (1<<2) 877 #define FBC_CTL_IDLE_LINE (2<<2) 878 #define FBC_CTL_IDLE_DEBUG (3<<2) 879 #define FBC_CTL_CPU_FENCE (1<<1) 880 #define FBC_CTL_PLANEA (0<<0) 881 #define FBC_CTL_PLANEB (1<<0) 882 #define FBC_FENCE_OFF 0x0321b 883 884 #define FBC_LL_SIZE (1536) 885 #define FBC_LL_PAD (32) 886 887 #define DSPARB 0x70030 888 889 #define PIPEAFRAMEHIGH 0x70040 890 #define PIPEBFRAMEHIGH 0x71040 891 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 892 #define PIPE_FRAME_HIGH_SHIFT 0 893 #define PIPEAFRAMEPIXEL 0x70044 894 #define PIPEBFRAMEPIXEL 0x71044 895 896 #define PIPE_FRAME_LOW_MASK 0xff000000 897 #define PIPE_FRAME_LOW_SHIFT 24 898 899 /* Interrupt bits: 900 */ 901 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 902 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 903 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 904 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 905 #define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */ 906 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 907 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 908 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 909 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 910 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 911 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 912 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 913 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 914 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 915 #define I915_DEBUG_INTERRUPT (1<<2) 916 #define I915_USER_INTERRUPT (1<<1) 917 918 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 919 #define I915_CRC_ERROR_ENABLE (1UL<<29) 920 #define I915_CRC_DONE_ENABLE (1UL<<28) 921 #define I915_GMBUS_EVENT_ENABLE (1UL<<27) 922 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 923 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 924 #define I915_DPST_EVENT_ENABLE (1UL<<23) 925 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 926 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 927 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 928 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 929 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 930 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 931 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 932 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 933 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 934 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 935 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 936 #define I915_DPST_EVENT_STATUS (1UL<<7) 937 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 938 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 939 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 940 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 941 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 942 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 943 944 /* 945 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 946 * of video memory available to the BIOS in SWF1. 947 */ 948 949 #define SWF0 0x71410 950 951 /* 952 * 855 scratch registers. 953 */ 954 #define SWF10 0x70410 955 956 #define SWF30 0x72414 957 958 #define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 959 #define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 960 #define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 961 #define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 962 #define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 963 #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 964 #define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 965 #define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 966 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 967 #define PCI_DEVICE_ID_INTEL_82946_GZ 0x2972 968 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 969 #define PCI_DEVICE_ID_INTEL_82Q963_IG 0x2992 970 #define PCI_DEVICE_ID_INTEL_82G965_IG 0x29a2 971 #define PCI_DEVICE_ID_INTEL_GM965_IG 0x2a02 972 #define PCI_DEVICE_ID_INTEL_GME965_IG 0x2a12 973 #define PCI_DEVICE_ID_INTEL_82G33_IG 0x29c2 974 #define PCI_DEVICE_ID_INTEL_82Q35_IG 0x29b2 975 #define PCI_DEVICE_ID_INTEL_82Q33_IG 0x29d2 976 #define PCI_DEVICE_ID_INTEL_CANTIGA_IG 0x2a42 977 #define PCI_DEVICE_ID_INTEL_EL_IG 0x2e02 978 #define PCI_DEVICE_ID_INTEL_82Q45_IG 0x2e12 979 #define PCI_DEVICE_ID_INTEL_82G45_IG 0x2e22 980 #define PCI_DEVICE_ID_INTEL_82G41_IG 0x2e32 981 982 983 #define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) 984 #define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) 985 #define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 986 #define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 987 #define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) 988 989 #define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG) 990 #define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) 991 #define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) 992 #define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG || \ 993 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GME_IG) 994 995 #define IS_I965G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82946_GZ || \ 996 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G35_IG || \ 997 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q963_IG || \ 998 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G965_IG || \ 999 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG || \ 1000 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG || \ 1001 (dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG || \ 1002 (dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1003 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1004 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1005 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1006 1007 #define IS_I965GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG) 1008 1009 #define IS_GM45(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG) 1010 1011 #define IS_G4X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1012 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1013 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1014 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1015 1016 #define IS_G33(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82G33_IG || \ 1017 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q35_IG || \ 1018 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q33_IG) 1019 1020 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1021 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1022 1023 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1024 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 1025 1026 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 1027 1028 #endif /* _I915_DRV_H */ 1029