1 /* 2 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* BEGIN CSTYLED */ 7 8 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 9 */ 10 /************************************************************************** 11 * 12 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 13 * All Rights Reserved. 14 * 15 * Permission is hereby granted, free of charge, to any person obtaining a 16 * copy of this software and associated documentation files (the 17 * "Software"), to deal in the Software without restriction, including 18 * without limitation the rights to use, copy, modify, merge, publish, 19 * distribute, sub license, and/or sell copies of the Software, and to 20 * permit persons to whom the Software is furnished to do so, subject to 21 * the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 28 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 30 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 31 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 32 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 33 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 34 * 35 **************************************************************************/ 36 37 #ifndef _I915_DRV_H 38 #define _I915_DRV_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 /* General customization: 43 */ 44 45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47 #define DRIVER_NAME "i915" 48 #define DRIVER_DESC "Intel Graphics" 49 #define DRIVER_DATE "20060801" 50 51 /* Interface history: 52 * 53 * 1.1: Original. 54 * 1.2: Add Power Management 55 */ 56 #define DRIVER_MAJOR 1 57 #define DRIVER_MINOR 2 58 #define DRIVER_PATCHLEVEL 0 59 60 typedef struct _drm_i915_ring_buffer { 61 int tail_mask; 62 unsigned long Start; 63 unsigned long End; 64 unsigned long Size; 65 u8 *virtual_start; 66 int head; 67 int tail; 68 int space; 69 drm_local_map_t map; 70 } drm_i915_ring_buffer_t; 71 72 struct mem_block { 73 struct mem_block *next; 74 struct mem_block *prev; 75 int start; 76 int size; 77 DRMFILE filp; /* 0: free, -1: heap, other: real files */ 78 }; 79 80 typedef struct drm_i915_private { 81 drm_local_map_t *sarea; 82 drm_local_map_t *mmio_map; 83 84 drm_i915_sarea_t *sarea_priv; 85 drm_i915_ring_buffer_t ring; 86 87 #if !defined(__SOLARIS__) && !defined(sun) 88 drm_dma_handle_t *status_page_dmah; 89 #endif 90 void *hw_status_page; 91 dma_addr_t dma_status_page; 92 unsigned long counter; 93 94 int back_offset; 95 int front_offset; 96 int current_page; 97 int page_flipping; 98 int use_mi_batchbuffer_start; 99 100 wait_queue_head_t irq_queue; 101 atomic_t irq_received; 102 atomic_t irq_emitted; 103 104 int tex_lru_log_granularity; 105 int allow_batchbuffer; 106 struct mem_block *agp_heap; 107 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 108 } drm_i915_private_t; 109 110 /* i915_dma.c */ 111 extern void i915_kernel_lost_context(drm_device_t * dev); 112 extern int i915_driver_load(drm_device_t *, unsigned long flags); 113 extern void i915_driver_lastclose(drm_device_t * dev); 114 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp); 115 extern int i915_driver_device_is_agp(drm_device_t * dev); 116 117 /* i915_irq.c */ 118 extern int i915_irq_emit(DRM_IOCTL_ARGS); 119 extern int i915_irq_wait(DRM_IOCTL_ARGS); 120 121 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 122 extern void i915_driver_irq_preinstall(drm_device_t * dev); 123 extern void i915_driver_irq_postinstall(drm_device_t * dev); 124 extern void i915_driver_irq_uninstall(drm_device_t * dev); 125 126 /* i915_mem.c */ 127 extern int i915_mem_alloc(DRM_IOCTL_ARGS); 128 extern int i915_mem_free(DRM_IOCTL_ARGS); 129 extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 130 extern void i915_mem_takedown(struct mem_block **heap); 131 extern void i915_mem_release(drm_device_t * dev, 132 DRMFILE filp, struct mem_block *heap); 133 extern struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region); 134 extern struct mem_block *find_block_by_proc(struct mem_block *heap, DRMFILE filp); 135 extern void mark_block(drm_device_t * dev, struct mem_block *p, int in_use); 136 extern void free_block(struct mem_block *p); 137 138 139 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 140 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 141 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 142 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 143 144 /* to make it LINT clean */ 145 static int i915_verbose = 0; 146 #ifndef I915_VERBOSE 147 #define I915_VERBOSE i915_verbose 148 #endif 149 150 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 151 volatile unsigned char *virt; 152 153 #define BEGIN_LP_RING(n) do { \ 154 if (I915_VERBOSE) \ 155 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ 156 n, __FUNCTION__); \ 157 if (dev_priv->ring.space < n*4) \ 158 (void) i915_wait_ring(dev, n*4, __FUNCTION__); \ 159 outcount = 0; \ 160 outring = dev_priv->ring.tail; \ 161 ringmask = dev_priv->ring.tail_mask; \ 162 virt = dev_priv->ring.virtual_start; \ 163 } while (*"\0") 164 165 #define OUT_RING(n) do { \ 166 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 167 *(volatile unsigned int *)(virt + outring) = n; \ 168 outcount++; \ 169 outring += 4; \ 170 outring &= ringmask; \ 171 } while (*"\0") 172 173 #define ADVANCE_LP_RING() do { \ 174 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 175 dev_priv->ring.tail = outring; \ 176 dev_priv->ring.space -= outcount * 4; \ 177 I915_WRITE(LP_RING + RING_TAIL, outring); \ 178 } while (*"\0") 179 180 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 181 182 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 183 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 184 #define CMD_REPORT_HEAD (7<<23) 185 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 186 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 187 188 #define INST_PARSER_CLIENT 0x00000000 189 #define INST_OP_FLUSH 0x02000000 190 #define INST_FLUSH_MAP_CACHE 0x00000001 191 192 #define BB1_START_ADDR_MASK (~0x7) 193 #define BB1_PROTECTED (1<<0) 194 #define BB1_UNPROTECTED (0<<0) 195 #define BB2_END_ADDR_MASK (~0x7) 196 197 #define I915REG_HWSTAM 0x02098 198 #define I915REG_INT_IDENTITY_R 0x020a4 199 #define I915REG_INT_MASK_R 0x020a8 200 #define I915REG_INT_ENABLE_R 0x020a0 201 202 #define SRX_INDEX 0x3c4 203 #define SRX_DATA 0x3c5 204 #define SR01 1 205 #define SR01_SCREEN_OFF (1<<5) 206 207 #define PPCR 0x61204 208 #define PPCR_ON (1<<0) 209 210 #define DVOB 0x61140 211 #define DVOB_ON (1<<31) 212 #define DVOC 0x61160 213 #define DVOC_ON (1<<31) 214 #define LVDS 0x61180 215 #define LVDS_ON (1<<31) 216 217 #define ADPA 0x61100 218 #define ADPA_DPMS_MASK (~(3<<10)) 219 #define ADPA_DPMS_ON (0<<10) 220 #define ADPA_DPMS_SUSPEND (1<<10) 221 #define ADPA_DPMS_STANDBY (2<<10) 222 #define ADPA_DPMS_OFF (3<<10) 223 224 #define NOPID 0x2094 225 #define LP_RING 0x2030 226 #define HP_RING 0x2040 227 #define RING_TAIL 0x00 228 #define TAIL_ADDR 0x001FFFF8 229 #define RING_HEAD 0x04 230 #define HEAD_WRAP_COUNT 0xFFE00000 231 #define HEAD_WRAP_ONE 0x00200000 232 #define HEAD_ADDR 0x001FFFFC 233 #define RING_START 0x08 234 #define START_ADDR 0x0xFFFFF000 235 #define RING_LEN 0x0C 236 #define RING_NR_PAGES 0x001FF000 237 #define RING_REPORT_MASK 0x00000006 238 #define RING_REPORT_64K 0x00000002 239 #define RING_REPORT_128K 0x00000004 240 #define RING_NO_REPORT 0x00000000 241 #define RING_VALID_MASK 0x00000001 242 #define RING_VALID 0x00000001 243 #define RING_INVALID 0x00000000 244 245 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 246 #define SC_UPDATE_SCISSOR (0x1<<1) 247 #define SC_ENABLE_MASK (0x1<<0) 248 #define SC_ENABLE (0x1<<0) 249 250 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 251 #define SCI_YMIN_MASK (0xffff<<16) 252 #define SCI_XMIN_MASK (0xffff<<0) 253 #define SCI_YMAX_MASK (0xffff<<16) 254 #define SCI_XMAX_MASK (0xffff<<0) 255 256 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 257 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 258 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 259 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 260 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 261 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 262 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 263 264 #define MI_BATCH_BUFFER ((0x30<<23)|1) 265 #define MI_BATCH_BUFFER_START (0x31<<23) 266 #define MI_BATCH_BUFFER_END (0xA<<23) 267 #define MI_BATCH_NON_SECURE (1) 268 269 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 270 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 271 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 272 273 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 274 275 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 276 #define ASYNC_FLIP (1<<22) 277 278 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 279 280 #endif /* _I915_DRV_H */ 281