1 /* BEGIN CSTYLED */ 2 3 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5 /* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sub license, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * 30 */ 31 32 /* 33 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 34 * Use is subject to license terms. 35 */ 36 37 #ifndef _I915_DRV_H 38 #define _I915_DRV_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 /* General customization: 43 */ 44 45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47 #define DRIVER_NAME "i915" 48 #define DRIVER_DESC "Intel Graphics" 49 #define DRIVER_DATE "20060929" 50 51 #if defined(__SVR4) && defined(__sun) 52 #define spinlock_t kmutex_t 53 #endif 54 55 /* Interface history: 56 * 57 * 1.1: Original. 58 * 1.2: Add Power Management 59 * 1.3: Add vblank support 60 * 1.4: Fix cmdbuffer path, add heap destroy 61 */ 62 #define DRIVER_MAJOR 1 63 #define DRIVER_MINOR 4 64 #define DRIVER_PATCHLEVEL 0 65 66 #if defined(__linux__) 67 #define I915_HAVE_FENCE 68 #define I915_HAVE_BUFFER 69 #endif 70 71 typedef struct _drm_i915_ring_buffer { 72 int tail_mask; 73 unsigned long Start; 74 unsigned long End; 75 unsigned long Size; 76 u8 *virtual_start; 77 int head; 78 int tail; 79 int space; 80 drm_local_map_t map; 81 } drm_i915_ring_buffer_t; 82 83 struct mem_block { 84 struct mem_block *next; 85 struct mem_block *prev; 86 int start; 87 int size; 88 DRMFILE filp; /* 0: free, -1: heap, other: real files */ 89 }; 90 91 typedef struct _drm_i915_vbl_swap { 92 struct list_head head; 93 drm_drawable_t drw_id; 94 unsigned int pipe; 95 unsigned int sequence; 96 } drm_i915_vbl_swap_t; 97 98 typedef struct drm_i915_private { 99 drm_local_map_t *sarea; 100 drm_local_map_t *mmio_map; 101 102 drm_i915_sarea_t *sarea_priv; 103 drm_i915_ring_buffer_t ring; 104 105 #if !defined(__SOLARIS__) && !defined(sun) 106 drm_dma_handle_t *status_page_dmah; 107 #endif 108 void *hw_status_page; 109 dma_addr_t dma_status_page; 110 uint32_t counter; 111 112 unsigned int cpp; 113 int back_offset; 114 int front_offset; 115 int current_page; 116 int page_flipping; 117 int use_mi_batchbuffer_start; 118 119 wait_queue_head_t irq_queue; 120 atomic_t irq_received; 121 atomic_t irq_emitted; 122 123 int tex_lru_log_granularity; 124 int allow_batchbuffer; 125 struct mem_block *agp_heap; 126 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 127 int vblank_pipe; 128 spinlock_t user_irq_lock; 129 int user_irq_refcount; 130 int fence_irq_on; 131 uint32_t irq_enable_reg; 132 int irq_enabled; 133 134 #ifdef I915_HAVE_FENCE 135 uint32_t flush_sequence; 136 uint32_t flush_flags; 137 uint32_t flush_pending; 138 uint32_t saved_flush_status; 139 #endif 140 #ifdef I915_HAVE_BUFFER 141 void *agp_iomap; 142 #endif 143 spinlock_t swaps_lock; 144 drm_i915_vbl_swap_t vbl_swaps; 145 unsigned int swaps_pending; 146 } drm_i915_private_t; 147 148 enum intel_chip_family { 149 CHIP_I8XX = 0x01, 150 CHIP_I9XX = 0x02, 151 CHIP_I915 = 0x04, 152 CHIP_I965 = 0x08, 153 }; 154 155 extern drm_ioctl_desc_t i915_ioctls[]; 156 extern int i915_max_ioctl; 157 158 /* i915_dma.c */ 159 extern void i915_kernel_lost_context(drm_device_t * dev); 160 extern int i915_driver_load(struct drm_device *, unsigned long flags); 161 extern void i915_driver_lastclose(drm_device_t * dev); 162 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp); 163 extern int i915_driver_device_is_agp(drm_device_t * dev); 164 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 165 unsigned long arg); 166 extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); 167 168 169 /* i915_irq.c */ 170 extern int i915_irq_emit(DRM_IOCTL_ARGS); 171 extern int i915_irq_wait(DRM_IOCTL_ARGS); 172 173 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); 174 extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence); 175 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 176 extern void i915_driver_irq_preinstall(drm_device_t * dev); 177 extern void i915_driver_irq_postinstall(drm_device_t * dev); 178 extern void i915_driver_irq_uninstall(drm_device_t * dev); 179 extern int i915_emit_irq(drm_device_t * dev); 180 extern void i915_user_irq_on(drm_i915_private_t *dev_priv); 181 extern void i915_user_irq_off(drm_i915_private_t *dev_priv); 182 183 /* i915_mem.c */ 184 extern int i915_mem_alloc(DRM_IOCTL_ARGS); 185 extern int i915_mem_free(DRM_IOCTL_ARGS); 186 extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 187 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); 188 extern void i915_mem_takedown(struct mem_block **heap); 189 extern void i915_mem_release(drm_device_t * dev, 190 DRMFILE filp, struct mem_block *heap); 191 extern struct mem_block **get_heap(drm_i915_private_t *, int); 192 extern struct mem_block *find_block_by_proc(struct mem_block *, DRMFILE); 193 extern void mark_block(drm_device_t *, struct mem_block *, int); 194 extern void free_block(struct mem_block *); 195 196 #ifdef I915_HAVE_FENCE 197 /* i915_fence.c */ 198 199 200 extern void i915_fence_handler(drm_device_t *dev); 201 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, 202 uint32_t flags, 203 uint32_t *sequence, 204 uint32_t *native_type); 205 extern void i915_poke_flush(drm_device_t *dev, uint32_t class); 206 extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); 207 #endif 208 209 #ifdef I915_HAVE_BUFFER 210 /* i915_buffer.c */ 211 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); 212 extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); 213 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); 214 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, 215 drm_mem_type_manager_t *man); 216 extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); 217 extern int i915_move(drm_buffer_object_t *bo, int evict, 218 int no_wait, drm_bo_mem_reg_t *new_mem); 219 220 #endif 221 222 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 223 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 224 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 225 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 226 227 /* to make it LINT clean */ 228 static int i915_verbose = 0; 229 #ifndef I915_VERBOSE 230 #define I915_VERBOSE i915_verbose 231 #endif 232 233 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 234 volatile unsigned char *virt; 235 236 #define BEGIN_LP_RING(n) do { \ 237 if (I915_VERBOSE) \ 238 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ 239 (n), __FUNCTION__); \ 240 if (dev_priv->ring.space < (n)*4) \ 241 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 242 outcount = 0; \ 243 outring = dev_priv->ring.tail; \ 244 ringmask = dev_priv->ring.tail_mask; \ 245 virt = dev_priv->ring.virtual_start; \ 246 } while (*"\0") 247 248 #define OUT_RING(n) do { \ 249 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 250 *(volatile unsigned int *)(virt + outring) = (n); \ 251 outcount++; \ 252 outring += 4; \ 253 outring &= ringmask; \ 254 } while (*"\0") 255 256 #define ADVANCE_LP_RING() do { \ 257 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 258 dev_priv->ring.tail = outring; \ 259 dev_priv->ring.space -= outcount * 4; \ 260 I915_WRITE(LP_RING + RING_TAIL, outring); \ 261 } while (*"\0") 262 263 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 264 265 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 266 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 267 #define CMD_REPORT_HEAD (7<<23) 268 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 269 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 270 271 #define INST_PARSER_CLIENT 0x00000000 272 #define INST_OP_FLUSH 0x02000000 273 #define INST_FLUSH_MAP_CACHE 0x00000001 274 275 #define CMD_MI_FLUSH (0x04 << 23) 276 #define MI_NO_WRITE_FLUSH (1 << 2) 277 #define MI_READ_FLUSH (1 << 0) 278 #define MI_EXE_FLUSH (1 << 1) 279 280 #define BB1_START_ADDR_MASK (~0x7) 281 #define BB1_PROTECTED (1<<0) 282 #define BB1_UNPROTECTED (0<<0) 283 #define BB2_END_ADDR_MASK (~0x7) 284 285 #define I915REG_HWSTAM 0x02098 286 #define I915REG_INT_IDENTITY_R 0x020a4 287 #define I915REG_INT_MASK_R 0x020a8 288 #define I915REG_INT_ENABLE_R 0x020a0 289 #define I915REG_INSTPM 0x020c0 290 291 #define I915REG_PIPEASTAT 0x70024 292 #define I915REG_PIPEBSTAT 0x71024 293 294 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 295 #define I915_VBLANK_CLEAR (1UL<<1) 296 297 #define SRX_INDEX 0x3c4 298 #define SRX_DATA 0x3c5 299 #define SR01 1 300 #define SR01_SCREEN_OFF (1<<5) 301 302 #define PPCR 0x61204 303 #define PPCR_ON (1<<0) 304 305 #define DVOB 0x61140 306 #define DVOB_ON (1<<31) 307 #define DVOC 0x61160 308 #define DVOC_ON (1<<31) 309 #define LVDS 0x61180 310 #define LVDS_ON (1<<31) 311 312 #define ADPA 0x61100 313 #define ADPA_DPMS_MASK (~(3<<10)) 314 #define ADPA_DPMS_ON (0<<10) 315 #define ADPA_DPMS_SUSPEND (1<<10) 316 #define ADPA_DPMS_STANDBY (2<<10) 317 #define ADPA_DPMS_OFF (3<<10) 318 319 #define NOPID 0x2094 320 #define LP_RING 0x2030 321 #define HP_RING 0x2040 322 #define RING_TAIL 0x00 323 #define TAIL_ADDR 0x001FFFF8 324 #define RING_HEAD 0x04 325 #define HEAD_WRAP_COUNT 0xFFE00000 326 #define HEAD_WRAP_ONE 0x00200000 327 #define HEAD_ADDR 0x001FFFFC 328 #define RING_START 0x08 329 #define START_ADDR 0x0xFFFFF000 330 #define RING_LEN 0x0C 331 #define RING_NR_PAGES 0x001FF000 332 #define RING_REPORT_MASK 0x00000006 333 #define RING_REPORT_64K 0x00000002 334 #define RING_REPORT_128K 0x00000004 335 #define RING_NO_REPORT 0x00000000 336 #define RING_VALID_MASK 0x00000001 337 #define RING_VALID 0x00000001 338 #define RING_INVALID 0x00000000 339 340 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 341 #define SC_UPDATE_SCISSOR (0x1<<1) 342 #define SC_ENABLE_MASK (0x1<<0) 343 #define SC_ENABLE (0x1<<0) 344 345 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 346 #define SCI_YMIN_MASK (0xffff<<16) 347 #define SCI_XMIN_MASK (0xffff<<0) 348 #define SCI_YMAX_MASK (0xffff<<16) 349 #define SCI_XMAX_MASK (0xffff<<0) 350 351 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 352 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 353 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 354 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 355 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 356 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 357 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 358 359 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 360 361 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 362 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 363 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 364 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 365 366 #define MI_BATCH_BUFFER ((0x30<<23)|1) 367 #define MI_BATCH_BUFFER_START (0x31<<23) 368 #define MI_BATCH_BUFFER_END (0xA<<23) 369 #define MI_BATCH_NON_SECURE (1) 370 371 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 372 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 373 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 374 375 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 376 377 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 378 #define ASYNC_FLIP (1<<22) 379 380 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 381 382 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) 383 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 384 385 #endif /* _I915_DRV_H */ 386