1 /* BEGIN CSTYLED */ 2 3 /* 4 * i915_drv.c -- Intel i915 driver -*- linux-c -*- 5 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 * 31 * Authors: 32 * Gareth Hughes <gareth@valinux.com> 33 * 34 */ 35 36 /* 37 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 41 /* 42 * I915 DRM Driver for Solaris 43 * 44 * This driver provides the hardware 3D acceleration support for Intel 45 * integrated video devices (e.g. i8xx/i915/i945 series chipsets), under the 46 * DRI (Direct Rendering Infrastructure). DRM (Direct Rendering Manager) here 47 * means the kernel device driver in DRI. 48 * 49 * I915 driver is a device dependent driver only, it depends on a misc module 50 * named drm for generic DRM operations. 51 */ 52 53 #include "drmP.h" 54 #include "i915_drm.h" 55 #include "i915_drv.h" 56 #include "drm_pciids.h" 57 58 /* 59 * copied from vgasubr.h 60 */ 61 62 struct vgaregmap { 63 uint8_t *addr; 64 ddi_acc_handle_t handle; 65 boolean_t mapped; 66 }; 67 68 enum pipe { 69 PIPE_A = 0, 70 PIPE_B, 71 }; 72 73 74 /* 75 * cb_ops entrypoint 76 */ 77 extern struct cb_ops drm_cb_ops; 78 79 /* 80 * module entrypoint 81 */ 82 static int i915_info(dev_info_t *, ddi_info_cmd_t, void *, void **); 83 static int i915_attach(dev_info_t *, ddi_attach_cmd_t); 84 static int i915_detach(dev_info_t *, ddi_detach_cmd_t); 85 86 87 /* drv_PCI_IDs comes from drm_pciids.h */ 88 static drm_pci_id_list_t i915_pciidlist[] = { 89 i915_PCI_IDS 90 }; 91 92 /* 93 * Local routines 94 */ 95 static void i915_configure(drm_driver_t *); 96 97 /* 98 * DRM driver 99 */ 100 static drm_driver_t i915_driver = {0}; 101 102 103 static struct dev_ops i915_dev_ops = { 104 DEVO_REV, /* devo_rev */ 105 0, /* devo_refcnt */ 106 i915_info, /* devo_getinfo */ 107 nulldev, /* devo_identify */ 108 nulldev, /* devo_probe */ 109 i915_attach, /* devo_attach */ 110 i915_detach, /* devo_detach */ 111 nodev, /* devo_reset */ 112 &drm_cb_ops, /* devo_cb_ops */ 113 NULL, /* devo_bus_ops */ 114 NULL, /* power */ 115 ddi_quiesce_not_supported, /* devo_quiesce */ 116 }; 117 118 static struct modldrv modldrv = { 119 &mod_driverops, /* drv_modops */ 120 "I915 DRM driver", /* drv_linkinfo */ 121 &i915_dev_ops, /* drv_dev_ops */ 122 }; 123 124 static struct modlinkage modlinkage = { 125 MODREV_1, (void *) &modldrv, NULL 126 }; 127 128 static ddi_device_acc_attr_t s3_attr = { 129 DDI_DEVICE_ATTR_V0, 130 DDI_NEVERSWAP_ACC, 131 DDI_STRICTORDER_ACC /* must be DDI_STRICTORDER_ACC */ 132 }; 133 134 /* 135 * softstate head 136 */ 137 static void *i915_statep; 138 139 int 140 _init(void) 141 { 142 int error; 143 144 i915_configure(&i915_driver); 145 146 if ((error = ddi_soft_state_init(&i915_statep, 147 sizeof (drm_device_t), DRM_MAX_INSTANCES)) != 0) 148 return (error); 149 150 if ((error = mod_install(&modlinkage)) != 0) { 151 ddi_soft_state_fini(&i915_statep); 152 return (error); 153 } 154 155 return (error); 156 157 } /* _init() */ 158 159 int 160 _fini(void) 161 { 162 int error; 163 164 if ((error = mod_remove(&modlinkage)) != 0) 165 return (error); 166 167 (void) ddi_soft_state_fini(&i915_statep); 168 169 return (0); 170 171 } /* _fini() */ 172 173 int 174 _info(struct modinfo *modinfop) 175 { 176 return (mod_info(&modlinkage, modinfop)); 177 178 } /* _info() */ 179 180 /* 181 * off range: 0x3b0 ~ 0x3ff 182 */ 183 184 static void 185 vga_reg_put8(struct vgaregmap *regmap, uint16_t off, uint8_t val) 186 { 187 ASSERT((off >= 0x3b0) && (off <= 0x3ff)); 188 189 ddi_put8(regmap->handle, regmap->addr + off, val); 190 } 191 192 /* 193 * off range: 0x3b0 ~ 0x3ff 194 */ 195 static uint8_t 196 vga_reg_get8(struct vgaregmap *regmap, uint16_t off) 197 { 198 199 ASSERT((off >= 0x3b0) && (off <= 0x3ff)); 200 201 return (ddi_get8(regmap->handle, regmap->addr + off)); 202 } 203 204 static void 205 i915_write_indexed(struct vgaregmap *regmap, 206 uint16_t index_port, uint16_t data_port, uint8_t index, uint8_t val) 207 { 208 vga_reg_put8(regmap, index_port, index); 209 vga_reg_put8(regmap, data_port, val); 210 } 211 212 static uint8_t 213 i915_read_indexed(struct vgaregmap *regmap, 214 uint16_t index_port, uint16_t data_port, uint8_t index) 215 { 216 vga_reg_put8(regmap, index_port, index); 217 return (vga_reg_get8(regmap, data_port)); 218 } 219 220 static void 221 i915_write_ar(struct vgaregmap *regmap, uint16_t st01, 222 uint8_t reg, uint8_t val, uint8_t palette_enable) 223 { 224 (void) vga_reg_get8(regmap, st01); 225 vga_reg_put8(regmap, VGA_AR_INDEX, palette_enable | reg); 226 vga_reg_put8(regmap, VGA_AR_DATA_WRITE, val); 227 } 228 229 static uint8_t 230 i915_read_ar(struct vgaregmap *regmap, uint16_t st01, 231 uint8_t index, uint8_t palette_enable) 232 { 233 (void) vga_reg_get8(regmap, st01); 234 vga_reg_put8(regmap, VGA_AR_INDEX, index | palette_enable); 235 return (vga_reg_get8(regmap, VGA_AR_DATA_READ)); 236 } 237 238 static int 239 i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 240 { 241 struct s3_i915_private *s3_priv = dev->s3_private; 242 243 if (pipe == PIPE_A) 244 return (S3_READ(DPLL_A) & DPLL_VCO_ENABLE); 245 else 246 return (S3_READ(DPLL_B) & DPLL_VCO_ENABLE); 247 } 248 249 static void 250 i915_save_palette(struct drm_device *dev, enum pipe pipe) 251 { 252 struct s3_i915_private *s3_priv = dev->s3_private; 253 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 254 uint32_t *array; 255 int i; 256 257 if (!i915_pipe_enabled(dev, pipe)) 258 return; 259 260 if (pipe == PIPE_A) 261 array = s3_priv->save_palette_a; 262 else 263 array = s3_priv->save_palette_b; 264 265 for(i = 0; i < 256; i++) 266 array[i] = S3_READ(reg + (i << 2)); 267 268 } 269 270 static void 271 i915_restore_palette(struct drm_device *dev, enum pipe pipe) 272 { 273 struct s3_i915_private *s3_priv = dev->s3_private; 274 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 275 uint32_t *array; 276 int i; 277 278 if (!i915_pipe_enabled(dev, pipe)) 279 return; 280 281 if (pipe == PIPE_A) 282 array = s3_priv->save_palette_a; 283 else 284 array = s3_priv->save_palette_b; 285 286 for(i = 0; i < 256; i++) 287 S3_WRITE(reg + (i << 2), array[i]); 288 } 289 290 static void 291 i915_save_vga(struct drm_device *dev) 292 { 293 struct s3_i915_private *s3_priv = dev->s3_private; 294 int i; 295 uint16_t cr_index, cr_data, st01; 296 struct vgaregmap regmap; 297 298 regmap.addr = (uint8_t *)s3_priv->saveAddr; 299 regmap.handle = s3_priv->saveHandle; 300 301 /* VGA color palette registers */ 302 s3_priv->saveDACMASK = vga_reg_get8(®map, VGA_DACMASK); 303 /* DACCRX automatically increments during read */ 304 vga_reg_put8(®map, VGA_DACRX, 0); 305 /* Read 3 bytes of color data from each index */ 306 for (i = 0; i < 256 * 3; i++) 307 s3_priv->saveDACDATA[i] = vga_reg_get8(®map, VGA_DACDATA); 308 309 /* MSR bits */ 310 s3_priv->saveMSR = vga_reg_get8(®map, VGA_MSR_READ); 311 if (s3_priv->saveMSR & VGA_MSR_CGA_MODE) { 312 cr_index = VGA_CR_INDEX_CGA; 313 cr_data = VGA_CR_DATA_CGA; 314 st01 = VGA_ST01_CGA; 315 } else { 316 cr_index = VGA_CR_INDEX_MDA; 317 cr_data = VGA_CR_DATA_MDA; 318 st01 = VGA_ST01_MDA; 319 } 320 321 /* CRT controller regs */ 322 i915_write_indexed(®map, cr_index, cr_data, 0x11, 323 i915_read_indexed(®map, cr_index, cr_data, 0x11) & (~0x80)); 324 for (i = 0; i <= 0x24; i++) 325 s3_priv->saveCR[i] = 326 i915_read_indexed(®map, cr_index, cr_data, i); 327 /* Make sure we don't turn off CR group 0 writes */ 328 s3_priv->saveCR[0x11] &= ~0x80; 329 330 /* Attribute controller registers */ 331 (void) vga_reg_get8(®map, st01); 332 s3_priv->saveAR_INDEX = vga_reg_get8(®map, VGA_AR_INDEX); 333 for (i = 0; i <= 0x14; i++) 334 s3_priv->saveAR[i] = i915_read_ar(®map, st01, i, 0); 335 (void) vga_reg_get8(®map, st01); 336 vga_reg_put8(®map, VGA_AR_INDEX, s3_priv->saveAR_INDEX); 337 (void) vga_reg_get8(®map, st01); 338 339 /* Graphics controller registers */ 340 for (i = 0; i < 9; i++) 341 s3_priv->saveGR[i] = 342 i915_read_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, i); 343 344 s3_priv->saveGR[0x10] = 345 i915_read_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, 0x10); 346 s3_priv->saveGR[0x11] = 347 i915_read_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, 0x11); 348 s3_priv->saveGR[0x18] = 349 i915_read_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, 0x18); 350 351 /* Sequencer registers */ 352 for (i = 0; i < 8; i++) 353 s3_priv->saveSR[i] = 354 i915_read_indexed(®map, VGA_SR_INDEX, VGA_SR_DATA, i); 355 } 356 357 static void 358 i915_restore_vga(struct drm_device *dev) 359 { 360 struct s3_i915_private *s3_priv = dev->s3_private; 361 int i; 362 uint16_t cr_index, cr_data, st01; 363 struct vgaregmap regmap; 364 365 regmap.addr = (uint8_t *)s3_priv->saveAddr; 366 regmap.handle = s3_priv->saveHandle; 367 368 /* 369 * I/O Address Select. This bit selects 3Bxh or 3Dxh as the 370 * I/O address for the CRT Controller registers, 371 * the Feature Control Register (FCR), and Input Status Register 372 * 1 (ST01). Presently ignored (whole range is claimed), but 373 * will "ignore" 3Bx for color configuration or 3Dx for monochrome. 374 * Note that it is typical in AGP chipsets to shadow this bit 375 * and properly steer I/O cycles to the proper bus for operation 376 * where a MDA exists on another bus such as ISA. 377 * 0 = Select 3Bxh I/O address (MDA emulation) (default). 378 * 1 = Select 3Dxh I/O address (CGA emulation). 379 */ 380 vga_reg_put8(®map, VGA_MSR_WRITE, s3_priv->saveMSR); 381 382 if (s3_priv->saveMSR & VGA_MSR_CGA_MODE) { 383 cr_index = VGA_CR_INDEX_CGA; 384 cr_data = VGA_CR_DATA_CGA; 385 st01 = VGA_ST01_CGA; 386 } else { 387 cr_index = VGA_CR_INDEX_MDA; 388 cr_data = VGA_CR_DATA_MDA; 389 st01 = VGA_ST01_MDA; 390 } 391 392 /* Sequencer registers, don't write SR07 */ 393 for (i = 0; i < 7; i++) 394 i915_write_indexed(®map, VGA_SR_INDEX, VGA_SR_DATA, i, 395 s3_priv->saveSR[i]); 396 /* CRT controller regs */ 397 /* Enable CR group 0 writes */ 398 i915_write_indexed(®map, cr_index, cr_data, 399 0x11, s3_priv->saveCR[0x11]); 400 for (i = 0; i <= 0x24; i++) 401 i915_write_indexed(®map, cr_index, 402 cr_data, i, s3_priv->saveCR[i]); 403 404 /* Graphics controller regs */ 405 for (i = 0; i < 9; i++) 406 i915_write_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, i, 407 s3_priv->saveGR[i]); 408 409 i915_write_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, 0x10, 410 s3_priv->saveGR[0x10]); 411 i915_write_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, 0x11, 412 s3_priv->saveGR[0x11]); 413 i915_write_indexed(®map, VGA_GR_INDEX, VGA_GR_DATA, 0x18, 414 s3_priv->saveGR[0x18]); 415 416 /* Attribute controller registers */ 417 (void) vga_reg_get8(®map, st01); /* switch back to index mode */ 418 for (i = 0; i <= 0x14; i++) 419 i915_write_ar(®map, st01, i, s3_priv->saveAR[i], 0); 420 (void) vga_reg_get8(®map, st01); /* switch back to index mode */ 421 vga_reg_put8(®map, VGA_AR_INDEX, s3_priv->saveAR_INDEX | 0x20); 422 (void) vga_reg_get8(®map, st01); /* switch back to index mode */ 423 424 /* VGA color palette registers */ 425 vga_reg_put8(®map, VGA_DACMASK, s3_priv->saveDACMASK); 426 /* DACCRX automatically increments during read */ 427 vga_reg_put8(®map, VGA_DACWX, 0); 428 /* Read 3 bytes of color data from each index */ 429 for (i = 0; i < 256 * 3; i++) 430 vga_reg_put8(®map, VGA_DACDATA, s3_priv->saveDACDATA[i]); 431 } 432 433 static int 434 i915_resume(struct drm_device *dev) 435 { 436 ddi_acc_handle_t conf_hdl; 437 struct s3_i915_private *s3_priv = dev->s3_private; 438 int i; 439 440 if (pci_config_setup(dev->dip, &conf_hdl) != DDI_SUCCESS) { 441 DRM_ERROR(("i915_resume: pci_config_setup fail")); 442 return (DDI_FAILURE); 443 } 444 /* 445 * Nexus driver will resume pci config space and set the power state 446 * for its children. So we needn't resume them explicitly here. 447 * see pci_pre_resume for detail. 448 */ 449 pci_config_put8(conf_hdl, LBB, s3_priv->saveLBB); 450 451 S3_WRITE(DSPARB, s3_priv->saveDSPARB); 452 453 /* 454 * Pipe & plane A info 455 * Prime the clock 456 */ 457 if (s3_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 458 S3_WRITE(DPLL_A, s3_priv->saveDPLL_A & 459 ~DPLL_VCO_ENABLE); 460 drv_usecwait(150); 461 } 462 S3_WRITE(FPA0, s3_priv->saveFPA0); 463 S3_WRITE(FPA1, s3_priv->saveFPA1); 464 /* Actually enable it */ 465 S3_WRITE(DPLL_A, s3_priv->saveDPLL_A); 466 drv_usecwait(150); 467 if (IS_I965G(dev)) 468 S3_WRITE(DPLL_A_MD, s3_priv->saveDPLL_A_MD); 469 drv_usecwait(150); 470 471 /* Restore mode */ 472 S3_WRITE(HTOTAL_A, s3_priv->saveHTOTAL_A); 473 S3_WRITE(HBLANK_A, s3_priv->saveHBLANK_A); 474 S3_WRITE(HSYNC_A, s3_priv->saveHSYNC_A); 475 S3_WRITE(VTOTAL_A, s3_priv->saveVTOTAL_A); 476 S3_WRITE(VBLANK_A, s3_priv->saveVBLANK_A); 477 S3_WRITE(VSYNC_A, s3_priv->saveVSYNC_A); 478 S3_WRITE(BCLRPAT_A, s3_priv->saveBCLRPAT_A); 479 480 /* Restore plane info */ 481 S3_WRITE(DSPASIZE, s3_priv->saveDSPASIZE); 482 S3_WRITE(DSPAPOS, s3_priv->saveDSPAPOS); 483 S3_WRITE(PIPEASRC, s3_priv->savePIPEASRC); 484 S3_WRITE(DSPABASE, s3_priv->saveDSPABASE); 485 S3_WRITE(DSPASTRIDE, s3_priv->saveDSPASTRIDE); 486 if (IS_I965G(dev)) { 487 S3_WRITE(DSPASURF, s3_priv->saveDSPASURF); 488 S3_WRITE(DSPATILEOFF, s3_priv->saveDSPATILEOFF); 489 } 490 S3_WRITE(PIPEACONF, s3_priv->savePIPEACONF); 491 i915_restore_palette(dev, PIPE_A); 492 /* Enable the plane */ 493 S3_WRITE(DSPACNTR, s3_priv->saveDSPACNTR); 494 S3_WRITE(DSPABASE, S3_READ(DSPABASE)); 495 496 /* Pipe & plane B info */ 497 if (s3_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 498 S3_WRITE(DPLL_B, s3_priv->saveDPLL_B & 499 ~DPLL_VCO_ENABLE); 500 drv_usecwait(150); 501 } 502 S3_WRITE(FPB0, s3_priv->saveFPB0); 503 S3_WRITE(FPB1, s3_priv->saveFPB1); 504 /* Actually enable it */ 505 S3_WRITE(DPLL_B, s3_priv->saveDPLL_B); 506 drv_usecwait(150); 507 if (IS_I965G(dev)) 508 S3_WRITE(DPLL_B_MD, s3_priv->saveDPLL_B_MD); 509 drv_usecwait(150); 510 511 /* Restore mode */ 512 S3_WRITE(HTOTAL_B, s3_priv->saveHTOTAL_B); 513 S3_WRITE(HBLANK_B, s3_priv->saveHBLANK_B); 514 S3_WRITE(HSYNC_B, s3_priv->saveHSYNC_B); 515 S3_WRITE(VTOTAL_B, s3_priv->saveVTOTAL_B); 516 S3_WRITE(VBLANK_B, s3_priv->saveVBLANK_B); 517 S3_WRITE(VSYNC_B, s3_priv->saveVSYNC_B); 518 S3_WRITE(BCLRPAT_B, s3_priv->saveBCLRPAT_B); 519 520 /* Restore plane info */ 521 S3_WRITE(DSPBSIZE, s3_priv->saveDSPBSIZE); 522 S3_WRITE(DSPBPOS, s3_priv->saveDSPBPOS); 523 S3_WRITE(PIPEBSRC, s3_priv->savePIPEBSRC); 524 S3_WRITE(DSPBBASE, s3_priv->saveDSPBBASE); 525 S3_WRITE(DSPBSTRIDE, s3_priv->saveDSPBSTRIDE); 526 if (IS_I965G(dev)) { 527 S3_WRITE(DSPBSURF, s3_priv->saveDSPBSURF); 528 S3_WRITE(DSPBTILEOFF, s3_priv->saveDSPBTILEOFF); 529 } 530 S3_WRITE(PIPEBCONF, s3_priv->savePIPEBCONF); 531 i915_restore_palette(dev, PIPE_B); 532 /* Enable the plane */ 533 S3_WRITE(DSPBCNTR, s3_priv->saveDSPBCNTR); 534 S3_WRITE(DSPBBASE, S3_READ(DSPBBASE)); 535 536 /* CRT state */ 537 S3_WRITE(ADPA, s3_priv->saveADPA); 538 539 /* LVDS state */ 540 if (IS_I965G(dev)) 541 S3_WRITE(BLC_PWM_CTL2, s3_priv->saveBLC_PWM_CTL2); 542 if (IS_MOBILE(dev) && !IS_I830(dev)) 543 S3_WRITE(LVDS, s3_priv->saveLVDS); 544 if (!IS_I830(dev) && !IS_845G(dev)) 545 S3_WRITE(PFIT_CONTROL, s3_priv->savePFIT_CONTROL); 546 547 S3_WRITE(PFIT_PGM_RATIOS, s3_priv->savePFIT_PGM_RATIOS); 548 S3_WRITE(BLC_PWM_CTL, s3_priv->saveBLC_PWM_CTL); 549 S3_WRITE(LVDSPP_ON, s3_priv->saveLVDSPP_ON); 550 S3_WRITE(LVDSPP_OFF, s3_priv->saveLVDSPP_OFF); 551 S3_WRITE(PP_CYCLE, s3_priv->savePP_CYCLE); 552 S3_WRITE(PP_CONTROL, s3_priv->savePP_CONTROL); 553 554 /* FIXME: restore TV & SDVO state */ 555 556 /* FBC info */ 557 S3_WRITE(FBC_CFB_BASE, s3_priv->saveFBC_CFB_BASE); 558 S3_WRITE(FBC_LL_BASE, s3_priv->saveFBC_LL_BASE); 559 S3_WRITE(FBC_CONTROL2, s3_priv->saveFBC_CONTROL2); 560 S3_WRITE(FBC_CONTROL, s3_priv->saveFBC_CONTROL); 561 562 /* VGA state */ 563 S3_WRITE(VGACNTRL, s3_priv->saveVGACNTRL); 564 S3_WRITE(VCLK_DIVISOR_VGA0, s3_priv->saveVCLK_DIVISOR_VGA0); 565 S3_WRITE(VCLK_DIVISOR_VGA1, s3_priv->saveVCLK_DIVISOR_VGA1); 566 S3_WRITE(VCLK_POST_DIV, s3_priv->saveVCLK_POST_DIV); 567 drv_usecwait(150); 568 569 /* Clock gating state */ 570 S3_WRITE (D_STATE, s3_priv->saveD_STATE); 571 S3_WRITE (CG_2D_DIS, s3_priv->saveCG_2D_DIS); 572 573 /* Cache mode state */ 574 S3_WRITE (CACHE_MODE_0, s3_priv->saveCACHE_MODE_0 | 0xffff0000); 575 576 /* Memory arbitration state */ 577 S3_WRITE (MI_ARB_STATE, s3_priv->saveMI_ARB_STATE | 0xffff0000); 578 579 for (i = 0; i < 16; i++) { 580 S3_WRITE(SWF0 + (i << 2), s3_priv->saveSWF0[i]); 581 S3_WRITE(SWF10 + (i << 2), s3_priv->saveSWF1[i+7]); 582 } 583 for (i = 0; i < 3; i++) 584 S3_WRITE(SWF30 + (i << 2), s3_priv->saveSWF2[i]); 585 586 i915_restore_vga(dev); 587 588 S3_WRITE(I915REG_PGTBL_CTRL, s3_priv->pgtbl_ctl); 589 590 (void) pci_config_teardown(&conf_hdl); 591 592 return (DDI_SUCCESS); 593 } 594 static int 595 i915_suspend(struct drm_device *dev) 596 { 597 ddi_acc_handle_t conf_hdl; 598 struct s3_i915_private *s3_priv = dev->s3_private; 599 int i; 600 601 602 if (pci_config_setup(dev->dip, &conf_hdl) != DDI_SUCCESS) { 603 DRM_ERROR(("i915_suspend: pci_config_setup fail")); 604 return (DDI_FAILURE); 605 } 606 607 /* 608 * Nexus driver will resume pci config space for its children. 609 * So pci config registers are not saved here. 610 */ 611 s3_priv->saveLBB = pci_config_get8(conf_hdl, LBB); 612 613 /* Display arbitration control */ 614 s3_priv->saveDSPARB = S3_READ(DSPARB); 615 616 /* 617 * Pipe & plane A info. 618 */ 619 s3_priv->savePIPEACONF = S3_READ(PIPEACONF); 620 s3_priv->savePIPEASRC = S3_READ(PIPEASRC); 621 s3_priv->saveFPA0 = S3_READ(FPA0); 622 s3_priv->saveFPA1 = S3_READ(FPA1); 623 s3_priv->saveDPLL_A = S3_READ(DPLL_A); 624 if (IS_I965G(dev)) 625 s3_priv->saveDPLL_A_MD = S3_READ(DPLL_A_MD); 626 s3_priv->saveHTOTAL_A = S3_READ(HTOTAL_A); 627 s3_priv->saveHBLANK_A = S3_READ(HBLANK_A); 628 s3_priv->saveHSYNC_A = S3_READ(HSYNC_A); 629 s3_priv->saveVTOTAL_A = S3_READ(VTOTAL_A); 630 s3_priv->saveVBLANK_A = S3_READ(VBLANK_A); 631 s3_priv->saveVSYNC_A = S3_READ(VSYNC_A); 632 s3_priv->saveBCLRPAT_A = S3_READ(BCLRPAT_A); 633 634 s3_priv->saveDSPACNTR = S3_READ(DSPACNTR); 635 s3_priv->saveDSPASTRIDE = S3_READ(DSPASTRIDE); 636 s3_priv->saveDSPASIZE = S3_READ(DSPASIZE); 637 s3_priv->saveDSPAPOS = S3_READ(DSPAPOS); 638 s3_priv->saveDSPABASE = S3_READ(DSPABASE); 639 if (IS_I965G(dev)) { 640 s3_priv->saveDSPASURF = S3_READ(DSPASURF); 641 s3_priv->saveDSPATILEOFF = S3_READ(DSPATILEOFF); 642 } 643 i915_save_palette(dev, PIPE_A); 644 s3_priv->savePIPEASTAT = S3_READ(I915REG_PIPEASTAT); 645 646 /* 647 * Pipe & plane B info 648 */ 649 s3_priv->savePIPEBCONF = S3_READ(PIPEBCONF); 650 s3_priv->savePIPEBSRC = S3_READ(PIPEBSRC); 651 s3_priv->saveFPB0 = S3_READ(FPB0); 652 s3_priv->saveFPB1 = S3_READ(FPB1); 653 s3_priv->saveDPLL_B = S3_READ(DPLL_B); 654 if (IS_I965G(dev)) 655 s3_priv->saveDPLL_B_MD = S3_READ(DPLL_B_MD); 656 s3_priv->saveHTOTAL_B = S3_READ(HTOTAL_B); 657 s3_priv->saveHBLANK_B = S3_READ(HBLANK_B); 658 s3_priv->saveHSYNC_B = S3_READ(HSYNC_B); 659 s3_priv->saveVTOTAL_B = S3_READ(VTOTAL_B); 660 s3_priv->saveVBLANK_B = S3_READ(VBLANK_B); 661 s3_priv->saveVSYNC_B = S3_READ(VSYNC_B); 662 s3_priv->saveBCLRPAT_A = S3_READ(BCLRPAT_A); 663 664 s3_priv->saveDSPBCNTR = S3_READ(DSPBCNTR); 665 s3_priv->saveDSPBSTRIDE = S3_READ(DSPBSTRIDE); 666 s3_priv->saveDSPBSIZE = S3_READ(DSPBSIZE); 667 s3_priv->saveDSPBPOS = S3_READ(DSPBPOS); 668 s3_priv->saveDSPBBASE = S3_READ(DSPBBASE); 669 if (IS_I965GM(dev) || IS_GM45(dev)) { 670 s3_priv->saveDSPBSURF = S3_READ(DSPBSURF); 671 s3_priv->saveDSPBTILEOFF = S3_READ(DSPBTILEOFF); 672 } 673 i915_save_palette(dev, PIPE_B); 674 s3_priv->savePIPEBSTAT = S3_READ(I915REG_PIPEBSTAT); 675 676 /* 677 * CRT state 678 */ 679 s3_priv->saveADPA = S3_READ(ADPA); 680 681 /* 682 * LVDS state 683 */ 684 s3_priv->savePP_CONTROL = S3_READ(PP_CONTROL); 685 s3_priv->savePFIT_PGM_RATIOS = S3_READ(PFIT_PGM_RATIOS); 686 s3_priv->saveBLC_PWM_CTL = S3_READ(BLC_PWM_CTL); 687 if (IS_I965G(dev)) 688 s3_priv->saveBLC_PWM_CTL2 = S3_READ(BLC_PWM_CTL2); 689 if (IS_MOBILE(dev) && !IS_I830(dev)) 690 s3_priv->saveLVDS = S3_READ(LVDS); 691 if (!IS_I830(dev) && !IS_845G(dev)) 692 s3_priv->savePFIT_CONTROL = S3_READ(PFIT_CONTROL); 693 s3_priv->saveLVDSPP_ON = S3_READ(LVDSPP_ON); 694 s3_priv->saveLVDSPP_OFF = S3_READ(LVDSPP_OFF); 695 s3_priv->savePP_CYCLE = S3_READ(PP_CYCLE); 696 697 /* FIXME: save TV & SDVO state */ 698 699 /* FBC state */ 700 s3_priv->saveFBC_CFB_BASE = S3_READ(FBC_CFB_BASE); 701 s3_priv->saveFBC_LL_BASE = S3_READ(FBC_LL_BASE); 702 s3_priv->saveFBC_CONTROL2 = S3_READ(FBC_CONTROL2); 703 s3_priv->saveFBC_CONTROL = S3_READ(FBC_CONTROL); 704 705 /* Interrupt state */ 706 s3_priv->saveIIR = S3_READ(I915REG_INT_IDENTITY_R); 707 s3_priv->saveIER = S3_READ(I915REG_INT_ENABLE_R); 708 s3_priv->saveIMR = S3_READ(I915REG_INT_MASK_R); 709 710 /* VGA state */ 711 s3_priv->saveVCLK_DIVISOR_VGA0 = S3_READ(VCLK_DIVISOR_VGA0); 712 s3_priv->saveVCLK_DIVISOR_VGA1 = S3_READ(VCLK_DIVISOR_VGA1); 713 s3_priv->saveVCLK_POST_DIV = S3_READ(VCLK_POST_DIV); 714 s3_priv->saveVGACNTRL = S3_READ(VGACNTRL); 715 716 /* Clock gating state */ 717 s3_priv->saveD_STATE = S3_READ(D_STATE); 718 s3_priv->saveCG_2D_DIS = S3_READ(CG_2D_DIS); 719 720 /* Cache mode state */ 721 s3_priv->saveCACHE_MODE_0 = S3_READ(CACHE_MODE_0); 722 723 /* Memory Arbitration state */ 724 s3_priv->saveMI_ARB_STATE = S3_READ(MI_ARB_STATE); 725 726 /* Scratch space */ 727 for (i = 0; i < 16; i++) { 728 s3_priv->saveSWF0[i] = S3_READ(SWF0 + (i << 2)); 729 s3_priv->saveSWF1[i] = S3_READ(SWF10 + (i << 2)); 730 } 731 for (i = 0; i < 3; i++) 732 s3_priv->saveSWF2[i] = S3_READ(SWF30 + (i << 2)); 733 734 735 i915_save_vga(dev); 736 /* 737 * Save page table control register 738 */ 739 s3_priv->pgtbl_ctl = S3_READ(I915REG_PGTBL_CTRL); 740 741 (void) pci_config_teardown(&conf_hdl); 742 743 return (DDI_SUCCESS); 744 } 745 746 /* 747 * This funtion check the length of memory mapped IO space to get the right bar. * And There are two possibilities here. 748 * 1. The MMIO registers is in memory map IO bar with 1M size. The bottom half 749 * of the 1M space is the MMIO registers. 750 * 2. The MMIO register is in memory map IO with 512K size. The whole 512K 751 * space is the MMIO registers. 752 */ 753 static int 754 i915_map_regs(dev_info_t *dip, caddr_t *save_addr, ddi_acc_handle_t *handlep) 755 { 756 int rnumber; 757 int nregs; 758 off_t size = 0; 759 760 if (ddi_dev_nregs(dip, &nregs)) { 761 cmn_err(CE_WARN, "i915_map_regs: failed to get nregs"); 762 return (DDI_FAILURE); 763 } 764 765 for (rnumber = 1; rnumber < nregs; rnumber++) { 766 (void) ddi_dev_regsize(dip, rnumber, &size); 767 if ((size == 0x80000) || 768 (size == 0x100000) || 769 (size == 0x400000)) 770 break; 771 } 772 773 if (rnumber >= nregs) { 774 cmn_err(CE_WARN, 775 "i915_map_regs: failed to find MMIO registers"); 776 return (DDI_FAILURE); 777 } 778 779 if (ddi_regs_map_setup(dip, rnumber, save_addr, 780 0, 0x80000, &s3_attr, handlep)) { 781 cmn_err(CE_WARN, 782 "i915_map_regs: failed to map bar %d", rnumber); 783 return (DDI_FAILURE); 784 } 785 786 return (DDI_SUCCESS); 787 } 788 static void 789 i915_unmap_regs(ddi_acc_handle_t *handlep) 790 { 791 ddi_regs_map_free(handlep); 792 } 793 static int 794 i915_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 795 { 796 drm_device_t *statep; 797 s3_i915_private_t *s3_private; 798 void *handle; 799 int unit; 800 801 unit = ddi_get_instance(dip); 802 switch (cmd) { 803 case DDI_ATTACH: 804 break; 805 case DDI_RESUME: 806 statep = ddi_get_soft_state(i915_statep, unit); 807 return (i915_resume(statep)); 808 default: 809 DRM_ERROR("i915_attach: attach and resume ops are supported"); 810 return (DDI_FAILURE); 811 812 } 813 814 if (ddi_soft_state_zalloc(i915_statep, unit) != DDI_SUCCESS) { 815 cmn_err(CE_WARN, 816 "i915_attach: failed to alloc softstate"); 817 return (DDI_FAILURE); 818 } 819 statep = ddi_get_soft_state(i915_statep, unit); 820 statep->dip = dip; 821 statep->driver = &i915_driver; 822 823 statep->s3_private = drm_alloc(sizeof(s3_i915_private_t), 824 DRM_MEM_DRIVER); 825 826 if (statep->s3_private == NULL) { 827 cmn_err(CE_WARN, "i915_attach: failed to allocate s3 priv"); 828 goto err_exit1; 829 } 830 831 /* 832 * Map in the mmio register space for s3. 833 */ 834 s3_private = (s3_i915_private_t *)statep->s3_private; 835 836 if (i915_map_regs(dip, &s3_private->saveAddr, 837 &s3_private->saveHandle)) { 838 cmn_err(CE_WARN, "i915_attach: failed to map MMIO"); 839 goto err_exit2; 840 } 841 842 /* 843 * Call drm_supp_register to create minor nodes for us 844 */ 845 handle = drm_supp_register(dip, statep); 846 if ( handle == NULL) { 847 DRM_ERROR("i915_attach: drm_supp_register failed"); 848 goto err_exit3; 849 } 850 statep->drm_handle = handle; 851 852 /* 853 * After drm_supp_register, we can call drm_xxx routine 854 */ 855 statep->drm_supported = DRM_UNSUPPORT; 856 if ( 857 drm_probe(statep, i915_pciidlist) != DDI_SUCCESS) { 858 DRM_ERROR("i915_open: " 859 "DRM current don't support this graphics card"); 860 goto err_exit4; 861 } 862 statep->drm_supported = DRM_SUPPORT; 863 864 /* call common attach code */ 865 if (drm_attach(statep) != DDI_SUCCESS) { 866 DRM_ERROR("i915_attach: drm_attach failed"); 867 goto err_exit4; 868 } 869 return (DDI_SUCCESS); 870 err_exit4: 871 (void) drm_supp_unregister(handle); 872 err_exit3: 873 i915_unmap_regs(&s3_private->saveHandle); 874 err_exit2: 875 drm_free(statep->s3_private, sizeof(s3_i915_private_t), 876 DRM_MEM_DRIVER); 877 err_exit1: 878 (void) ddi_soft_state_free(i915_statep, unit); 879 880 return (DDI_FAILURE); 881 882 } /* i915_attach() */ 883 884 static int 885 i915_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 886 { 887 drm_device_t *statep; 888 int unit; 889 s3_i915_private_t *s3_private; 890 891 if ((cmd != DDI_SUSPEND) && (cmd != DDI_DETACH)) { 892 DRM_ERROR("i915_detach: " 893 "only detach and resume ops are supported"); 894 return (DDI_FAILURE); 895 } 896 897 unit = ddi_get_instance(dip); 898 statep = ddi_get_soft_state(i915_statep, unit); 899 if (statep == NULL) { 900 DRM_ERROR("i915_detach: can not get soft state"); 901 return (DDI_FAILURE); 902 } 903 904 if (cmd == DDI_SUSPEND) 905 return (i915_suspend(statep)); 906 907 s3_private = (s3_i915_private_t *)statep->s3_private; 908 ddi_regs_map_free(&s3_private->saveHandle); 909 910 /* 911 * Free the struct for context saving in S3 912 */ 913 drm_free(statep->s3_private, sizeof(s3_i915_private_t), 914 DRM_MEM_DRIVER); 915 916 (void) drm_detach(statep); 917 (void) drm_supp_unregister(statep->drm_handle); 918 (void) ddi_soft_state_free(i915_statep, unit); 919 920 return (DDI_SUCCESS); 921 922 } /* i915_detach() */ 923 924 925 /*ARGSUSED*/ 926 static int 927 i915_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 928 { 929 drm_device_t *statep; 930 int error = DDI_SUCCESS; 931 int unit; 932 933 unit = drm_dev_to_instance((dev_t)arg); 934 switch (infocmd) { 935 case DDI_INFO_DEVT2DEVINFO: 936 statep = ddi_get_soft_state(i915_statep, unit); 937 if (statep == NULL || statep->dip == NULL) { 938 error = DDI_FAILURE; 939 } else { 940 *result = (void *) statep->dip; 941 error = DDI_SUCCESS; 942 } 943 break; 944 case DDI_INFO_DEVT2INSTANCE: 945 *result = (void *)(uintptr_t)unit; 946 error = DDI_SUCCESS; 947 break; 948 default: 949 error = DDI_FAILURE; 950 break; 951 } 952 return (error); 953 954 } /* i915_info() */ 955 956 957 static void i915_configure(drm_driver_t *driver) 958 { 959 driver->buf_priv_size = 1; /* No dev_priv */ 960 driver->load = i915_driver_load; 961 driver->unload = i915_driver_unload; 962 driver->preclose = i915_driver_preclose; 963 driver->lastclose = i915_driver_lastclose; 964 driver->device_is_agp = i915_driver_device_is_agp; 965 driver->vblank_wait = i915_driver_vblank_wait; 966 driver->vblank_wait2 = i915_driver_vblank_wait2; 967 driver->irq_preinstall = i915_driver_irq_preinstall; 968 driver->irq_postinstall = i915_driver_irq_postinstall; 969 driver->irq_uninstall = i915_driver_irq_uninstall; 970 driver->irq_handler = i915_driver_irq_handler; 971 972 driver->driver_ioctls = i915_ioctls; 973 driver->max_driver_ioctl = i915_max_ioctl; 974 975 driver->driver_name = DRIVER_NAME; 976 driver->driver_desc = DRIVER_DESC; 977 driver->driver_date = DRIVER_DATE; 978 driver->driver_major = DRIVER_MAJOR; 979 driver->driver_minor = DRIVER_MINOR; 980 driver->driver_patchlevel = DRIVER_PATCHLEVEL; 981 982 driver->use_agp = 1; 983 driver->require_agp = 1; 984 driver->use_irq = 1; 985 driver->use_vbl_irq = 1; 986 driver->use_vbl_irq2 = 1; 987 } 988