1 /* BEGIN CSTYLED */ 2 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 /* 30 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 31 * Use is subject to license terms. 32 */ 33 34 #ifndef _I915_DRM_H 35 #define _I915_DRM_H 36 37 #pragma ident "%Z%%M% %I% %E% SMI" 38 39 /* Please note that modifications to all structs defined here are 40 * subject to backwards-compatibility constraints. 41 */ 42 43 #include "drm.h" 44 45 /* Each region is a minimum of 16k, and there are at most 255 of them. 46 */ 47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 48 * of chars for next/prev indices */ 49 #define I915_LOG_MIN_TEX_REGION_SIZE 14 50 51 typedef struct _drm_i915_init { 52 enum { 53 I915_INIT_DMA = 0x01, 54 I915_CLEANUP_DMA = 0x02, 55 I915_RESUME_DMA = 0x03 56 } func; 57 unsigned int mmio_offset; 58 int sarea_priv_offset; 59 unsigned int ring_start; 60 unsigned int ring_end; 61 unsigned int ring_size; 62 unsigned int front_offset; 63 unsigned int back_offset; 64 unsigned int depth_offset; 65 unsigned int w; 66 unsigned int h; 67 unsigned int pitch; 68 unsigned int pitch_bits; 69 unsigned int back_pitch; 70 unsigned int depth_pitch; 71 unsigned int cpp; 72 unsigned int chipset; 73 } drm_i915_init_t; 74 75 typedef struct _drm_i915_sarea { 76 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 } drm_i915_sarea_t; 126 127 /* Driver specific fence types and classes. 128 */ 129 130 /* The only fence class we support */ 131 #define DRM_I915_FENCE_CLASS_ACCEL 0 132 /* Fence type that guarantees read-write flush */ 133 #define DRM_I915_FENCE_TYPE_RW 2 134 /* MI_FLUSH programmed just before the fence */ 135 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 136 137 /* Flags for perf_boxes 138 */ 139 #define I915_BOX_RING_EMPTY 0x1 140 #define I915_BOX_FLIP 0x2 141 #define I915_BOX_WAIT 0x4 142 #define I915_BOX_TEXTURE_LOAD 0x8 143 #define I915_BOX_LOST_CONTEXT 0x10 144 145 /* I915 specific ioctls 146 * The device specific ioctl range is 0x40 to 0x79. 147 */ 148 #define DRM_I915_INIT 0x00 149 #define DRM_I915_FLUSH 0x01 150 #define DRM_I915_FLIP 0x02 151 #define DRM_I915_BATCHBUFFER 0x03 152 #define DRM_I915_IRQ_EMIT 0x04 153 #define DRM_I915_IRQ_WAIT 0x05 154 #define DRM_I915_GETPARAM 0x06 155 #define DRM_I915_SETPARAM 0x07 156 #define DRM_I915_ALLOC 0x08 157 #define DRM_I915_FREE 0x09 158 #define DRM_I915_INIT_HEAP 0x0a 159 #define DRM_I915_CMDBUFFER 0x0b 160 #define DRM_I915_DESTROY_HEAP 0x0c 161 #define DRM_I915_HWS_ADDR 0x11 162 163 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 164 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 165 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 166 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 167 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 168 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 169 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 170 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 171 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 172 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 173 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 174 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 175 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 176 177 /* Allow drivers to submit batchbuffers directly to hardware, relying 178 * on the security mechanisms provided by hardware. 179 */ 180 typedef struct _drm_i915_batchbuffer { 181 int start; /* agp offset */ 182 int used; /* nr bytes in use */ 183 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 184 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 185 int num_cliprects; /* mulitpass with multiple cliprects? */ 186 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ 187 } drm_i915_batchbuffer_t; 188 189 typedef struct _drm_i915_batchbuffer32 { 190 int start; /* agp offset */ 191 int used; /* nr bytes in use */ 192 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 193 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 194 int num_cliprects; /* mulitpass with multiple cliprects? */ 195 caddr32_t cliprects; /* pointer to userspace cliprects */ 196 } drm_i915_batchbuffer32_t; 197 198 /* As above, but pass a pointer to userspace buffer which can be 199 * validated by the kernel prior to sending to hardware. 200 */ 201 typedef struct _drm_i915_cmdbuffer { 202 char __user *buf; /* pointer to userspace command buffer */ 203 int sz; /* nr bytes in buf */ 204 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 205 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 206 int num_cliprects; /* mulitpass with multiple cliprects? */ 207 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ 208 } drm_i915_cmdbuffer_t; 209 210 typedef struct _drm_i915_cmdbuffer32 { 211 caddr32_t buf; /* pointer to userspace command buffer */ 212 int sz; /* nr bytes in buf */ 213 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 214 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 215 int num_cliprects; /* mulitpass with multiple cliprects? */ 216 caddr32_t cliprects; /* pointer to userspace cliprects */ 217 } drm_i915_cmdbuffer32_t; 218 219 /* Userspace can request & wait on irq's: 220 */ 221 typedef struct drm_i915_irq_emit { 222 int __user *irq_seq; 223 } drm_i915_irq_emit_t; 224 225 typedef struct drm_i915_irq_emit32 { 226 caddr32_t irq_seq; 227 } drm_i915_irq_emit32_t; 228 229 typedef struct drm_i915_irq_wait { 230 int irq_seq; 231 } drm_i915_irq_wait_t; 232 233 /* Ioctl to query kernel params: 234 */ 235 #define I915_PARAM_IRQ_ACTIVE 1 236 #define I915_PARAM_ALLOW_BATCHBUFFER 2 237 #define I915_PARAM_LAST_DISPATCH 3 238 239 typedef struct drm_i915_getparam { 240 int param; 241 int __user *value; 242 } drm_i915_getparam_t; 243 244 typedef struct drm_i915_getparam32 { 245 int param; 246 caddr32_t value; 247 } drm_i915_getparam32_t; 248 249 /* Ioctl to set kernel params: 250 */ 251 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 252 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 253 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 254 255 typedef struct drm_i915_setparam { 256 int param; 257 int value; 258 } drm_i915_setparam_t; 259 260 /* A memory manager for regions of shared memory: 261 */ 262 #define I915_MEM_REGION_AGP 1 263 264 typedef struct drm_i915_mem_alloc { 265 int region; 266 int alignment; 267 int size; 268 int __user *region_offset; /* offset from start of fb or agp */ 269 } drm_i915_mem_alloc_t; 270 271 typedef struct drm_i915_mem_alloc32 { 272 int region; 273 int alignment; 274 int size; 275 caddr32_t region_offset; /* offset from start of fb or agp */ 276 } drm_i915_mem_alloc32_t; 277 278 typedef struct drm_i915_mem_free { 279 int region; 280 int region_offset; 281 } drm_i915_mem_free_t; 282 283 typedef struct drm_i915_mem_init_heap { 284 int region; 285 int size; 286 int start; 287 } drm_i915_mem_init_heap_t; 288 289 /* Allow memory manager to be torn down and re-initialized (eg on 290 * rotate): 291 */ 292 typedef struct drm_i915_mem_destroy_heap { 293 int region; 294 } drm_i915_mem_destroy_heap_t; 295 296 /* Allow X server to configure which pipes to monitor for vblank signals 297 */ 298 #define DRM_I915_VBLANK_PIPE_A 1 299 #define DRM_I915_VBLANK_PIPE_B 2 300 301 typedef struct drm_i915_vblank_pipe { 302 int pipe; 303 } drm_i915_vblank_pipe_t; 304 305 /* Schedule buffer swap at given vertical blank: 306 */ 307 typedef struct drm_i915_vblank_swap { 308 drm_drawable_t drawable; 309 drm_vblank_seq_type_t seqtype; 310 unsigned int sequence; 311 } drm_i915_vblank_swap_t; 312 313 typedef struct drm_i915_hws_addr { 314 uint64_t addr; 315 } drm_i915_hws_addr_t; 316 317 318 #endif /* _I915_DRM_H */ 319