1 /* BEGIN CSTYLED */ 2 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 /* 30 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 31 * Use is subject to license terms. 32 */ 33 34 #ifndef _I915_DRM_H 35 #define _I915_DRM_H 36 37 /* Please note that modifications to all structs defined here are 38 * subject to backwards-compatibility constraints. 39 */ 40 41 #include "drm.h" 42 43 /* Each region is a minimum of 16k, and there are at most 255 of them. 44 */ 45 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 46 * of chars for next/prev indices */ 47 #define I915_LOG_MIN_TEX_REGION_SIZE 14 48 49 typedef struct _drm_i915_init { 50 enum { 51 I915_INIT_DMA = 0x01, 52 I915_CLEANUP_DMA = 0x02, 53 I915_RESUME_DMA = 0x03 54 } func; 55 unsigned int mmio_offset; 56 int sarea_priv_offset; 57 unsigned int ring_start; 58 unsigned int ring_end; 59 unsigned int ring_size; 60 unsigned int front_offset; 61 unsigned int back_offset; 62 unsigned int depth_offset; 63 unsigned int w; 64 unsigned int h; 65 unsigned int pitch; 66 unsigned int pitch_bits; 67 unsigned int back_pitch; 68 unsigned int depth_pitch; 69 unsigned int cpp; 70 unsigned int chipset; 71 } drm_i915_init_t; 72 73 typedef struct _drm_i915_sarea { 74 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; 75 int last_upload; /* last time texture was uploaded */ 76 int last_enqueue; /* last time a buffer was enqueued */ 77 int last_dispatch; /* age of the most recently dispatched buffer */ 78 int ctxOwner; /* last context to upload state */ 79 int texAge; 80 int pf_enabled; /* is pageflipping allowed? */ 81 int pf_active; 82 int pf_current_page; /* which buffer is being displayed? */ 83 int perf_boxes; /* performance boxes to be displayed */ 84 int width, height; /* screen size in pixels */ 85 int pad0; 86 87 drm_handle_t front_handle; 88 int front_offset; 89 int front_size; 90 91 drm_handle_t back_handle; 92 int back_offset; 93 int back_size; 94 95 drm_handle_t depth_handle; 96 int depth_offset; 97 int depth_size; 98 99 drm_handle_t tex_handle; 100 int tex_offset; 101 int tex_size; 102 int log_tex_granularity; 103 int pitch; 104 int rotation; /* 0, 90, 180 or 270 */ 105 int rotated_offset; 106 int rotated_size; 107 int rotated_pitch; 108 int virtualX, virtualY; 109 110 unsigned int front_tiled; 111 unsigned int back_tiled; 112 unsigned int depth_tiled; 113 unsigned int rotated_tiled; 114 unsigned int rotated2_tiled; 115 116 int planeA_x; 117 int planeA_y; 118 int planeA_w; 119 int planeA_h; 120 int planeB_x; 121 int planeB_y; 122 int planeB_w; 123 int planeB_h; 124 125 /* Triple buffering */ 126 drm_handle_t third_handle; 127 int third_offset; 128 int third_size; 129 unsigned int third_tiled; 130 131 } drm_i915_sarea_t; 132 133 /* Driver specific fence types and classes. 134 */ 135 136 /* The only fence class we support */ 137 #define DRM_I915_FENCE_CLASS_ACCEL 0 138 /* Fence type that guarantees read-write flush */ 139 #define DRM_I915_FENCE_TYPE_RW 2 140 /* MI_FLUSH programmed just before the fence */ 141 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 142 143 /* Flags for perf_boxes 144 */ 145 #define I915_BOX_RING_EMPTY 0x1 146 #define I915_BOX_FLIP 0x2 147 #define I915_BOX_WAIT 0x4 148 #define I915_BOX_TEXTURE_LOAD 0x8 149 #define I915_BOX_LOST_CONTEXT 0x10 150 151 /* I915 specific ioctls 152 * The device specific ioctl range is 0x40 to 0x79. 153 */ 154 #define DRM_I915_INIT 0x00 155 #define DRM_I915_FLUSH 0x01 156 #define DRM_I915_FLIP 0x02 157 #define DRM_I915_BATCHBUFFER 0x03 158 #define DRM_I915_IRQ_EMIT 0x04 159 #define DRM_I915_IRQ_WAIT 0x05 160 #define DRM_I915_GETPARAM 0x06 161 #define DRM_I915_SETPARAM 0x07 162 #define DRM_I915_ALLOC 0x08 163 #define DRM_I915_FREE 0x09 164 #define DRM_I915_INIT_HEAP 0x0a 165 #define DRM_I915_CMDBUFFER 0x0b 166 #define DRM_I915_DESTROY_HEAP 0x0c 167 #define DRM_I915_SET_VBLANK_PIPE 0x0d 168 #define DRM_I915_GET_VBLANK_PIPE 0x0e 169 #define DRM_I915_VBLANK_SWAP 0x0f 170 #define DRM_I915_HWS_ADDR 0x11 171 172 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 173 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 174 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 175 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 176 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 177 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 178 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 179 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 180 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 181 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 182 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 183 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 184 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 185 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 186 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 187 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 188 189 /* Asynchronous page flipping: 190 */ 191 typedef struct drm_i915_flip { 192 /* 193 * This is really talking about planes, and we could rename it 194 * except for the fact that some of the duplicated i915_drm.h files 195 * out there check for HAVE_I915_FLIP and so might pick up this 196 * version. 197 */ 198 int pipes; 199 } drm_i915_flip_t; 200 201 /* Allow drivers to submit batchbuffers directly to hardware, relying 202 * on the security mechanisms provided by hardware. 203 */ 204 typedef struct _drm_i915_batchbuffer { 205 int start; /* agp offset */ 206 int used; /* nr bytes in use */ 207 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 208 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 209 int num_cliprects; /* mulitpass with multiple cliprects? */ 210 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ 211 } drm_i915_batchbuffer_t; 212 213 typedef struct _drm_i915_batchbuffer32 { 214 int start; /* agp offset */ 215 int used; /* nr bytes in use */ 216 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 217 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 218 int num_cliprects; /* mulitpass with multiple cliprects? */ 219 caddr32_t cliprects; /* pointer to userspace cliprects */ 220 } drm_i915_batchbuffer32_t; 221 222 /* As above, but pass a pointer to userspace buffer which can be 223 * validated by the kernel prior to sending to hardware. 224 */ 225 typedef struct _drm_i915_cmdbuffer { 226 char __user *buf; /* pointer to userspace command buffer */ 227 int sz; /* nr bytes in buf */ 228 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 229 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 230 int num_cliprects; /* mulitpass with multiple cliprects? */ 231 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ 232 } drm_i915_cmdbuffer_t; 233 234 typedef struct _drm_i915_cmdbuffer32 { 235 caddr32_t buf; /* pointer to userspace command buffer */ 236 int sz; /* nr bytes in buf */ 237 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 238 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 239 int num_cliprects; /* mulitpass with multiple cliprects? */ 240 caddr32_t cliprects; /* pointer to userspace cliprects */ 241 } drm_i915_cmdbuffer32_t; 242 243 /* Userspace can request & wait on irq's: 244 */ 245 typedef struct drm_i915_irq_emit { 246 int __user *irq_seq; 247 } drm_i915_irq_emit_t; 248 249 typedef struct drm_i915_irq_emit32 { 250 caddr32_t irq_seq; 251 } drm_i915_irq_emit32_t; 252 253 typedef struct drm_i915_irq_wait { 254 int irq_seq; 255 } drm_i915_irq_wait_t; 256 257 /* Ioctl to query kernel params: 258 */ 259 #define I915_PARAM_IRQ_ACTIVE 1 260 #define I915_PARAM_ALLOW_BATCHBUFFER 2 261 #define I915_PARAM_LAST_DISPATCH 3 262 #define I915_PARAM_CHIPSET_ID 4 263 264 typedef struct drm_i915_getparam { 265 int param; 266 int __user *value; 267 } drm_i915_getparam_t; 268 269 typedef struct drm_i915_getparam32 { 270 int param; 271 caddr32_t value; 272 } drm_i915_getparam32_t; 273 274 /* Ioctl to set kernel params: 275 */ 276 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 277 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 278 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 279 280 typedef struct drm_i915_setparam { 281 int param; 282 int value; 283 } drm_i915_setparam_t; 284 285 /* A memory manager for regions of shared memory: 286 */ 287 #define I915_MEM_REGION_AGP 1 288 289 typedef struct drm_i915_mem_alloc { 290 int region; 291 int alignment; 292 int size; 293 int __user *region_offset; /* offset from start of fb or agp */ 294 } drm_i915_mem_alloc_t; 295 296 typedef struct drm_i915_mem_alloc32 { 297 int region; 298 int alignment; 299 int size; 300 caddr32_t region_offset; /* offset from start of fb or agp */ 301 } drm_i915_mem_alloc32_t; 302 303 typedef struct drm_i915_mem_free { 304 int region; 305 int region_offset; 306 } drm_i915_mem_free_t; 307 308 typedef struct drm_i915_mem_init_heap { 309 int region; 310 int size; 311 int start; 312 } drm_i915_mem_init_heap_t; 313 314 /* Allow memory manager to be torn down and re-initialized (eg on 315 * rotate): 316 */ 317 typedef struct drm_i915_mem_destroy_heap { 318 int region; 319 } drm_i915_mem_destroy_heap_t; 320 321 /* Allow X server to configure which pipes to monitor for vblank signals 322 */ 323 #define DRM_I915_VBLANK_PIPE_A 1 324 #define DRM_I915_VBLANK_PIPE_B 2 325 326 typedef struct drm_i915_vblank_pipe { 327 int pipe; 328 } drm_i915_vblank_pipe_t; 329 330 /* Schedule buffer swap at given vertical blank: 331 */ 332 typedef struct drm_i915_vblank_swap { 333 drm_drawable_t drawable; 334 drm_vblank_seq_type_t seqtype; 335 unsigned int sequence; 336 } drm_i915_vblank_swap_t; 337 338 typedef struct drm_i915_hws_addr { 339 uint64_t addr; 340 } drm_i915_hws_addr_t; 341 342 343 #endif /* _I915_DRM_H */ 344