xref: /titanic_41/usr/src/uts/intel/io/amr/amrvar.h (revision 7257d1b4d25bfac0c802847390e98a464fd787ac)
1 /*
2  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 /*
6  * Copyright (c) 1999,2000 Michael Smith
7  * Copyright (c) 2000 BSDi
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * Copyright (c) 2002 Eric Moore
32  * Copyright (c) 2002 LSI Logic Corporation
33  * All rights reserved.
34  *
35  * Redistribution and use in source and binary forms, with or without
36  * modification, are permitted provided that the following conditions
37  * are met:
38  * 1. Redistributions of source code must retain the above copyright
39  *    notice, this list of conditions and the following disclaimer.
40  * 2. Redistributions in binary form must reproduce the above copyright
41  *    notice, this list of conditions and the following disclaimer in the
42  *    documentation and/or other materials provided with the distribution.
43  * 3. The party using or redistributing the source code and binary forms
44  *    agrees to the disclaimer below and the terms and conditions set forth
45  *    herein.
46  *
47  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
48  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
51  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57  * SUCH DAMAGE.
58  */
59 
60 #ifndef _AMRVAR_H
61 #define	_AMRVAR_H
62 
63 #pragma ident	"%Z%%M%	%I%	%E% SMI"
64 
65 #ifdef	__cplusplus
66 extern "C" {
67 #endif
68 
69 #define	AMR_DEBUG
70 #ifdef AMR_DEBUG
71 #define	AMRDB_PRINT(fmt) if (amr_debug_var) cmn_err fmt
72 #else
73 #define	AMRDB_PRINT(fmt)
74 #endif
75 
76 #define	AMRDB_PANIC(fmt) cmn_err fmt
77 
78 #define	AMR_PERIODIC_TIMEOUT		60
79 #define	AMR_RETRYCOUNT			10000
80 
81 /* for scsi commands */
82 #ifndef	SD_MODE_SENSE_PAGE3_CODE
83 #define	SD_MODE_SENSE_PAGE3_CODE	0x03
84 #endif
85 
86 #ifndef	SD_MODE_SENSE_PAGE4_CODE
87 #define	SD_MODE_SENSE_PAGE4_CODE	0x04
88 #endif
89 
90 #ifndef	SCMD_SYNCHRONIZE_CACHE
91 #define	SCMD_SYNCHRONIZE_CACHE		0x35
92 #endif
93 
94 #define	AMR_DEFAULT_SECTORS		512
95 #define	AMR_DEFAULT_HEADS		255
96 #define	AMR_DEFAULT_CYLINDERS		63
97 #define	AMR_DEFAULT_ROTATIONS		10000
98 
99 #define	AMR_INQ_ADDITIONAL_LEN		31
100 #define	AMR_INQ_ANSI_VER		2
101 #define	AMR_INQ_RESP_DATA_FORMAT	2
102 
103 #define	AMR_PRODUCT_INFO_SIZE \
104 			sizeof (((struct scsi_inquiry *)(NULL))->inq_pid)
105 #define	AMR_FIRMWARE_VER_SIZE \
106 			sizeof (((struct scsi_inquiry *)(NULL))->inq_revision)
107 
108 #define	AMR_LAST_COOKIE_TAG		0xffffffff
109 
110 /*
111  * Per-logical-drive datastructure
112  */
113 struct amr_logdrive
114 {
115 	uint32_t	al_size;
116 	uint8_t		al_state;
117 	uint8_t		al_properties;
118 };
119 
120 /*
121  * Per-command control structure.
122  */
123 struct amr_command
124 {
125 
126 	struct amr_command	*ac_prev;
127 	struct amr_command	*ac_next;
128 
129 	struct amr_softs	*ac_softs;
130 	uint8_t			ac_slot;
131 
132 	uint8_t			ac_status;
133 	uint32_t		ac_flags;
134 
135 	struct buf		*ac_buf;
136 	uint32_t		cmdlen;
137 	struct scsi_pkt		*pkt;
138 
139 	void			*ac_data;
140 	size_t			ac_length;
141 	uint32_t		ac_dataphys;
142 
143 	ddi_dma_handle_t	sg_dma_handle;
144 	ddi_dma_cookie_t	sg_dma_cookie;
145 	uint_t			sg_dma_cookien;
146 
147 	ddi_dma_handle_t	buffer_dma_handle;
148 	ddi_dma_cookie_t	buffer_dma_cookie;
149 	ddi_acc_handle_t	buffer_acc_handle;
150 	uint_t			num_of_cookie;
151 	uint_t			num_of_win;
152 	uint_t			current_cookie;
153 	uint_t			current_win;
154 	uint32_t		data_transfered;
155 	uint32_t		transfer_size;
156 
157 	struct amr_mailbox	mailbox;
158 	struct amr_sgentry	sgtable[AMR_NSEG];
159 
160 	time_t			ac_timestamp;
161 };
162 
163 /*
164  * ac_flags values in amr_command
165  */
166 #define	AMR_CMD_DATAIN		(1<<0)
167 #define	AMR_CMD_DATAOUT		(1<<1)
168 #define	AMR_CMD_CCB_DATAIN	(1<<2)
169 #define	AMR_CMD_CCB_DATAOUT	(1<<3)
170 #define	AMR_CMD_PRIORITY	(1<<4)
171 #define	AMR_CMD_MAPPED		(1<<5)
172 #define	AMR_CMD_SLEEP		(1<<6)
173 #define	AMR_CMD_BUSY		(1<<7)
174 #define	AMR_CMD_PKT_CONSISTENT	(1<<8)
175 #define	AMR_CMD_PKT_DMA_PARTIAL	(1<<9)
176 #define	AMR_CMD_GOT_SLOT	(1<<10)
177 
178 struct sg_item {
179 	struct amr_sgentry	*sg_table;
180 	ddi_dma_handle_t	sg_handle;
181 	ddi_acc_handle_t	sg_acc_handle;
182 	uint32_t		sg_phyaddr;
183 };
184 
185 struct product_info {
186 	uint8_t			pi_firmware_ver[AMR_FIRMWARE_VER_SIZE+1];
187 	uint8_t			pi_product_name[AMR_PRODUCT_INFO_SIZE+1];
188 };
189 
190 /*
191  * Per-controller-instance data
192  */
193 struct amr_softs
194 {
195 	/* bus attachments */
196 	dev_info_t		*dev_info_p;
197 	ddi_acc_handle_t	pciconfig_handle;
198 	ddi_acc_handle_t	regsmap_handle;
199 	ddi_iblock_cookie_t	iblock_cookiep;
200 
201 	ddi_dma_handle_t	mbox_dma_handle;
202 	ddi_acc_handle_t	mbox_acc_handle;
203 	ddi_dma_cookie_t	mbox_dma_cookie;
204 	uint_t			mbox_dma_cookien;
205 
206 	/* controller limits and features */
207 	uint8_t			maxio; /* maximum number of I/O transactions */
208 	uint8_t			maxdrives; /* max number of logical drives */
209 	uint8_t			maxchan; /* count of SCSI channels */
210 
211 	uint8_t			amr_nlogdrives;
212 
213 	/* connected logical drives */
214 	struct amr_logdrive	logic_drive[AMR_MAXLD];
215 
216 	/* product info of the card */
217 	struct product_info	amr_product_info;
218 
219 	/* controller state */
220 	uint32_t		state;
221 
222 	struct amr_mailbox	*mailbox;
223 	void			*mbox;
224 	uint32_t		mbox_phyaddr;
225 
226 	/* per-controller poll command */
227 	kmutex_t		cmd_mutex;
228 	kcondvar_t		cmd_cv;
229 
230 	uint32_t		amr_busyslots;
231 	struct amr_command	*busycmd[AMR_MAXCMD];
232 	struct sg_item		sg_items[AMR_MAXCMD];
233 	uint32_t		sg_max_count;
234 	struct amr_command	*waiting_q_head;
235 	struct amr_command	*waiting_q_tail;
236 	kmutex_t		queue_mutex;
237 
238 	/* periodic status check */
239 	timeout_id_t		timeout_t;
240 	kmutex_t		periodic_mutex;
241 
242 	scsi_hba_tran_t		*hba_tran;
243 
244 	ddi_taskq_t		*amr_taskq;
245 	uint32_t		amr_interrupts_counter;
246 };
247 
248 /*
249  * state values in amr_softs
250  */
251 #define	AMR_STATE_OPEN			(1<<0)
252 #define	AMR_STATE_SUSPEND		(1<<1)
253 #define	AMR_STATE_CARD_DETECTED		(1<<2)
254 #define	AMR_STATE_BUS_MASTER_ENABLED	(1<<3)
255 #define	AMR_STATE_SOFT_STATE_SETUP	(1<<4)
256 #define	AMR_STATE_PCI_CONFIG_SETUP	(1<<5)
257 #define	AMR_STATE_PCI_MEM_MAPPED	(1<<6)
258 #define	AMR_STATE_KMUTEX_INITED		(1<<7)
259 #define	AMR_STATE_MAILBOX_SETUP		(1<<8)
260 #define	AMR_STATE_SG_TABLES_SETUP	(1<<9)
261 #define	AMR_STATE_INTR_SETUP		(1<<10)
262 #define	AMR_STATE_TASKQ_SETUP		(1<<11)
263 #define	AMR_STATE_TRAN_SETUP		(1<<12)
264 #define	AMR_STATE_TIMEOUT_ENABLED	(1<<13)
265 
266 #ifdef	__cplusplus
267 }
268 #endif
269 
270 #endif /* _AMRVAR_H */
271