1 /* 2 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 /* 6 * Copyright (c) 1999,2000 Michael Smith 7 * Copyright (c) 2000 BSDi 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * Copyright (c) 2002 Eric Moore 32 * Copyright (c) 2002 LSI Logic Corporation 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. The party using or redistributing the source code and binary forms 44 * agrees to the disclaimer below and the terms and conditions set forth 45 * herein. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 */ 59 60 /* 61 * Note: If the structures and variables definitions can be found from the 62 * "MegaRAID PCI SCSI Disk Array Controller F/W Technical Reference 63 * Manual", the names defined in this documents will also be provided 64 * by " ", and the descriptions for each variables and constants are 65 * given as well. 66 */ 67 68 #ifndef _AMRREG_H 69 #define _AMRREG_H 70 71 #pragma ident "%Z%%M% %I% %E% SMI" 72 73 #ifdef __cplusplus 74 extern "C" { 75 #endif 76 77 #define AMR_NSEG 26 78 #define AMR_MAX_STATUS_ACK 46 79 80 #define AMR_MAXCMD 255 /* The last CMD is used for Poll only */ 81 82 #define AMR_LIMITCMD 120 /* max count of outstanding commands */ 83 #define AMR_MAXLD 40 84 85 #define AMR_MAX_CHANNELS 4 86 #define AMR_MAX_TARGETS 15 87 #define AMR_MAX_LUNS 7 88 #define AMR_MAX_SCSI_CMDS (AMR_MAX_CHANNELS * AMR_MAX_TARGETS) 89 90 #define AMR_MAX_CDB_LEN 0x0a 91 #define AMR_MAX_EXTCDB_LEN 0x10 92 #define AMR_MAX_REQ_SENSE_LEN 0x20 93 94 #define AMR_BLKSIZE 512 /* constant for all controllers */ 95 96 /* 97 * Array constraints for controllers that support 8 logic drivers 98 */ 99 #define AMR_8LD_MAXDRIVES 8 100 #define AMR_8LD_MAXCHAN 5 101 #define AMR_8LD_MAXTARG 15 102 #define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 103 104 /* 105 * Array constraints for controllers that support 40 logic drivers 106 */ 107 #define AMR_40LD_MAXDRIVES 40 108 #define AMR_40LD_MAXCHAN 16 109 #define AMR_40LD_MAXTARG 16 110 #define AMR_40LD_MAXPHYSDRIVES (AMR_40LD_MAXCHAN * AMR_40LD_MAXTARG) 111 112 /* 113 * The buffer size for enquiry command 114 */ 115 #define AMR_ENQ_BUFFER_SIZE sizeof (union amr_enq_buffer) 116 117 /* 118 * Constants used for poll command 119 */ 120 #define AMR_POLL_COMMAND_ID 0xfe 121 #define AMR_POLL_DEFAULT_NSTATUS 0xff 122 #define AMR_POLL_DEFAULT_STATUS 0xff 123 #define AMR_POLL_ACK 0x77 124 125 #pragma pack(1) 126 127 /* 128 * The AMR mailbox. This is the main interface for 129 * programming the controller. Must be aligned at 130 * a 16-Byte physical address boundary. 131 * 132 * The first sixteen bytes are commands to the controller. 133 * 134 * There are two formats: 135 * 1. Commands for I/O: mb_blkcount/mb_lba are used. 136 * 2. Commands for I/O control: mb_channel/mb_param are used. 137 * 138 */ 139 140 struct amr_mailbox 141 { 142 uint8_t mb_command; /* "Command", OUT, the op */ 143 /* code of the command */ 144 uint8_t mb_ident; /* "CommandID", OUT, the */ 145 /* id for this command */ 146 union { 147 uint16_t mbu_blkcount; /* "NoOfSectors", OUT, the */ 148 /* number of sectors for */ 149 /* this request */ 150 uint8_t mbu_chparam[2]; /* "Channel" and "Param", */ 151 /* OUT, Channel No. and */ 152 /* parameters */ 153 } mb_un1; 154 union { 155 uint32_t mbu_lba; /* "Lba", OUT, the starting */ 156 /* LBA for this request */ 157 uint8_t mbu_pad[4]; 158 } mb_un2; 159 uint32_t mb_physaddr; /* "DataTransferAddress", OUT */ 160 /* physical address for a */ 161 /* non-s/g command or the */ 162 /* physical address of a s/g */ 163 /* list for a s/g command */ 164 uint8_t mb_drive; /* "LogicalDriveNumber", OUT, */ 165 /* the log-drive for which */ 166 /* this request is intended */ 167 uint8_t mb_nsgelem; /* "NoSGElements", OUT, */ 168 /* number of s/g elements */ 169 uint8_t res1; 170 uint8_t mb_busy; /* "mailboxBusy", INOUT, set */ 171 /* to 1 before submit the */ 172 /* command, firmware picks */ 173 /* it and makes this byte 0 */ 174 uint8_t mb_nstatus; /* "NoOfStatus", IN, the */ 175 /* number of status returned */ 176 /* by firmware */ 177 uint8_t mb_status; /* "Status", IN, status for */ 178 /* the IDs in mb_completed[] */ 179 uint8_t mb_completed[AMR_MAX_STATUS_ACK]; 180 /* "CompletedIdList", IN, */ 181 /* finished ID list */ 182 uint8_t mb_poll; /* "Mraid_poll", IN, used for */ 183 /* polling/interrupt-driven */ 184 uint8_t mb_ack; /* "Mraid_ack", IN, used for */ 185 /* polling/interrupt-driver */ 186 uint8_t res2[16]; 187 }; 188 189 /* Fields before mb_nstatus are the portions worth copying for controller */ 190 #define AMR_MBOX_CMDSIZE (size_t)(&((struct amr_mailbox *)(NULL))->mb_nstatus) 191 192 #define mb_blkcount mb_un1.mbu_blkcount 193 #define mb_channel mb_un1.mbu_chparam[0] 194 #define mb_param mb_un1.mbu_chparam[1] 195 #define mb_cmdsub mb_un1.mbu_chparam[0] 196 #define mb_cmdqual mb_un1.mbu_chparam[1] 197 #define mb_lba mb_un2.mbu_lba 198 199 /* 200 * I/O commands expect the physical address of an array 201 * of no more than AMR_NSEGS of scatter/gather table entries 202 * in mb_physaddr. 203 * 204 * sg_addr is a physical address. 205 */ 206 struct amr_sgentry 207 { 208 uint32_t sg_addr; 209 uint32_t sg_count; 210 }; 211 212 /* 213 * Mailbox commands 214 * Note: This is a subset for the command set 215 */ 216 #define AMR_CMD_LREAD 0x01 217 #define AMR_CMD_LWRITE 0x02 218 #define AMR_CMD_PASS 0x03 219 #define AMR_CMD_EXT_ENQUIRY 0x04 220 #define AMR_CMD_ENQUIRY 0x05 221 #define AMR_CMD_FLUSH 0x0a 222 #define AMR_CMD_EXT_ENQUIRY2 0x0c 223 #define AMR_CMD_GET_MACHINEID 0x36 224 #define AMR_CMD_GET_INITIATOR 0x7d 225 #define AMR_CMD_RESET_ADAPTER 0x96 226 #define AMR_CMD_CONFIG 0xa1 227 #define AMR_CMD_MISC_OPCODE 0xa4 228 #define AMR_CMD_EXTPASS 0xe3 229 230 /* 231 * Subcodes for AMR_CMD_CONFIG 232 */ 233 #define AMR_CONFIG_PRODUCT_INFO 0x0e 234 #define AMR_CONFIG_ENQ3 0x0f 235 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 236 #define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 237 #define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 238 239 /* 240 * Subcodes for AMR_CMD_MISC_OPCODE 241 */ 242 #define AMR_MISC_CDB_QUERY 0x16 243 244 /* 245 * Mailbox command results 246 */ 247 #define AMR_STATUS_SUCCESS 0x00 248 #define AMR_STATUS_ABORTED 0x02 249 #define AMR_STATUS_FAILED 0x80 250 251 /* 252 * Adapter Info structure 253 */ 254 struct amr_adapter_info 255 { 256 uint8_t aa_maxio; /* "MaxConcCmds", concurrent */ 257 /* commands supported */ 258 uint8_t aa_rebuild_rate; /* "RbldRate", rebuild rate, */ 259 /* varies from 0%-100% */ 260 uint8_t aa_maxtargchan; /* "MaxTargPerChan", targets */ 261 /* supported per chan */ 262 uint8_t aa_channels; /* "ChanPresent", No. of */ 263 /* Chans present on this */ 264 /* adapter */ 265 uint8_t aa_firmware[4]; /* "FwVer", firmware version */ 266 uint16_t aa_flashage; /* "AgeOfFlash", No. of times */ 267 /* FW has been downloaded */ 268 uint8_t aa_chipsetvalue; /* "ChipSetValue", contents */ 269 /* of 0xC0000832 */ 270 uint8_t aa_memorysize; /* "DramSize", in terms of MB */ 271 uint8_t aa_cacheflush; /* "CacheFlushInterval", in */ 272 /* terms of Seconds */ 273 uint8_t aa_bios[4]; /* "BiosVersion", Bios ver */ 274 uint8_t aa_boardtype; /* "BoardType", board type */ 275 uint8_t aa_scsisensealert; /* "sense_alert" */ 276 uint8_t aa_writeconfigcount; /* "write_config_count", */ 277 /* increase with evry */ 278 /* configuration change */ 279 uint8_t aa_driveinsertioncount; /* "drive_inserted_count", */ 280 /* increase with every drive */ 281 /* inserted */ 282 uint8_t aa_inserteddrive; /* "inserted_drive", Chan:Id */ 283 /* of inserted drive */ 284 uint8_t aa_batterystatus; /* "battery_status", battery */ 285 /* status */ 286 uint8_t res1; /* "dec_fault_bus_info", was */ 287 /* reserved */ 288 }; 289 290 /* 291 * aa_batterystatus values 292 */ 293 #define AMR_BATT_MODULE_MISSING 0x01 294 #define AMR_BATT_LOW_VOLTAGE 0x02 295 #define AMR_BATT_TEMP_HIGH 0x04 296 #define AMR_BATT_PACK_MISSING 0x08 297 #define AMR_BATT_CHARGE_MASK 0x30 298 #define AMR_BATT_CHARGE_DONE 0x00 299 #define AMR_BATT_CHARGE_INPROG 0x10 300 #define AMR_BATT_CHARGE_FAIL 0x20 301 #define AMR_BATT_CYCLES_EXCEEDED 0x40 302 303 /* 304 * Logical Drive info structure 305 */ 306 struct amr_logdrive_info 307 { 308 uint8_t al_numdrives; /* "NumLogDrv", No. of */ 309 /* configured logic drivers */ 310 uint8_t res1[3]; 311 uint32_t al_size[AMR_8LD_MAXDRIVES]; 312 /* "LDrvSize", size of each */ 313 /* logic driver */ 314 uint8_t al_properties[AMR_8LD_MAXDRIVES]; 315 /* "LDrvProp", properties of */ 316 /* each logic driver */ 317 uint8_t al_state[AMR_8LD_MAXDRIVES]; 318 /* "LDrvState", state of */ 319 /* each logic driver */ 320 }; 321 322 /* 323 * Logical drive only: al_properties 324 */ 325 #define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc */ 326 #define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 327 #define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 328 #define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O enabled */ 329 330 /* 331 * Physical Drive info structure 332 */ 333 struct amr_physdrive_info 334 { 335 uint8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; 336 /* "PDrvState", state of each */ 337 /* phy-driver. Low nibble is */ 338 /* current state, high nibble */ 339 /* is previous state */ 340 uint8_t ap_predictivefailure; /* "PredictiveFailure" */ 341 }; 342 343 /* 344 * Physical/logical drive states 345 * 346 * Both logical and physical drives maintain 347 * 'current' and 'previous' states in the low/high 348 * nibble of the _state field. 349 */ 350 #define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 351 #define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 352 353 /* 354 * Logical drives: al_state. 355 */ 356 #define AMR_LDRV_OFFLINE 0x00 357 #define AMR_LDRV_DEGRADED 0x01 358 #define AMR_LDRV_OPTIMAL 0x02 359 360 /* 361 * Physical drives: ap_state. 362 */ 363 #define AMR_PDRV_UNCNF 0x00 364 #define AMR_PDRV_ONLINE 0x03 365 #define AMR_PDRV_FAILED 0x04 366 #define AMR_PDRV_REBUILD 0x05 367 #define AMR_PDRV_HOTSPARE 0x06 368 369 /* 370 * Notify structure 371 */ 372 struct amr_notify 373 { 374 uint32_t an_globalcounter; /* "globalCounter", change */ 375 /* counter */ 376 uint8_t an_paramcounter; /* "paramCounter", parameter */ 377 /* change counter */ 378 uint8_t an_paramid; /* "paramId", param modified */ 379 uint16_t an_paramval; /* "paramVal", new var of */ 380 /* last param modified */ 381 382 uint8_t an_writeconfigcounter; /* "writeConfigCounter", */ 383 /* write config occurred */ 384 uint8_t res1[3]; /* "writeConfigRsvd" */ 385 386 uint8_t an_ldrvopcounter; /* "ldrvOpCounter", logical */ 387 /* drive operation */ 388 uint8_t an_ldrvopid; /* "ldrvOpId", ldrv num */ 389 uint8_t an_ldrvopcmd; /* "ldrvOpCmd", ldrv */ 390 /* operations */ 391 uint8_t an_ldrvopstatus; /* "ldrvOpStatus", status of */ 392 /* the operation */ 393 394 uint8_t an_ldrvstatecounter; /* "ldrvStateCounter", change */ 395 /* of logical drive state */ 396 uint8_t an_ldrvstateid; /* "ldrvStateId", ldrv num */ 397 uint8_t an_ldrvstatenew; /* "ldrvStateNew", new state */ 398 uint8_t an_ldrvstateold; /* "ldrvStateOld", old state */ 399 400 uint8_t an_pdrvstatecounter; /* "pdrvStateCounter", change */ 401 /* of physical drive state */ 402 uint8_t an_pdrvstateid; /* "pdrvStateId", pdrv id */ 403 uint8_t an_pdrvstatenew; /* "pdrvStateNew", new state */ 404 uint8_t an_pdrvstateold; /* "pdrvStateOld", old state */ 405 406 uint8_t an_pdrvfmtcounter; /* "pdrvFmtCounter", pdrv */ 407 /* format started/over */ 408 uint8_t an_pdrvfmtid; /* "pdrvFmtId", pdrv id */ 409 uint8_t an_pdrvfmtval; /* "pdrvFmtVal", format */ 410 /* started/over */ 411 uint8_t res2; /* "pdrvFmtRsvd" */ 412 413 uint8_t an_targxfercounter; /* "targXferCounter", scsi */ 414 /* xfer rate change */ 415 uint8_t an_targxferid; /* "targXferId", pdrv id */ 416 uint8_t an_targxferval; /* "targXferVal", new Xfer */ 417 /* params of last pdrv */ 418 uint8_t res3; /* "targXferRsvd" */ 419 420 uint8_t an_fcloopidcounter; /* "fcLoopIdChgCounter", */ 421 /* FC/AL loop ID changed */ 422 uint8_t an_fcloopidpdrvid; /* "fcLoopIdPdrvId", pdrv id */ 423 uint8_t an_fcloopid0; /* "fcLoopId0", loopid on fc */ 424 /* loop 0 */ 425 uint8_t an_fcloopid1; /* "fcLoopId1", loopid on fc */ 426 /* loop 1 */ 427 428 uint8_t an_fcloopstatecounter; /* "fcLoopStateCounter", */ 429 /* FC/AL loop status changed */ 430 uint8_t an_fcloopstate0; /* "fcLoopState0", state of */ 431 /* fc loop 0 */ 432 uint8_t an_fcloopstate1; /* "fcLoopState1", state of */ 433 /* fc loop 1 */ 434 uint8_t res4; /* "fcLoopStateRsvd" */ 435 uint8_t pad[88]; 436 }; 437 438 /* 439 * an_param values 440 */ 441 #define AMR_PARAM_REBUILD_RATE 0x01 442 #define AMR_PARAM_FLUSH_INTERVAL 0x02 443 #define AMR_PARAM_SENSE_ALERT 0x03 444 #define AMR_PARAM_DRIVE_INSERTED 0x04 445 #define AMR_PARAM_BATTERY_STATUS 0x05 446 447 /* 448 * an_ldrvopcmd values 449 */ 450 #define AMR_LDRVOP_CHECK 0x01 451 #define AMR_LDRVOP_INIT 0x02 452 #define AMR_LDRVOP_REBUILD 0x03 453 454 /* 455 * an_ldrvopstatus: return values after issuing command 456 * via an_ldrvopcmd. 457 */ 458 #define AMR_LDRVOP_SUCCESS 0x00 459 #define AMR_LDRVOP_FAILED 0x01 460 #define AMR_LDRVOP_ABORTED 0x02 461 #define AMR_LDRVOP_CORRECTED 0x03 462 #define AMR_LDRVOP_STARTED 0x04 463 464 /* 465 * an_pdrvfmtval: Formatting commands/return values 466 */ 467 #define AMR_FORMAT_START 0x01 468 #define AMR_FORMAT_COMPLETE 0x02 469 470 /* 471 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 472 * AMR_CMD_EXT_ENQUIRY2. 473 */ 474 struct amr_enquiry 475 { 476 struct amr_adapter_info ae_adapter; 477 struct amr_logdrive_info ae_ldrv; 478 struct amr_physdrive_info ae_pdrv; 479 uint8_t ae_formatting[AMR_8LD_MAXDRIVES]; 480 uint8_t res1[AMR_8LD_MAXDRIVES]; 481 uint32_t ae_extlen; 482 uint16_t ae_subsystem; 483 uint16_t ae_subvendor; 484 uint32_t ae_signature; 485 uint8_t res2[844]; 486 }; 487 488 /* 489 * ae_signature values 490 */ 491 #define AMR_SIG_431 0xfffe0001 492 #define AMR_SIG_438 0xfffd0002 493 #define AMR_SIG_762 0xfffc0003 494 #define AMR_SIG_T5 0xfffb0004 495 #define AMR_SIG_466 0xfffa0005 496 #define AMR_SIG_467 0xfff90006 497 #define AMR_SIG_T7 0xfff80007 498 #define AMR_SIG_490 0xfff70008 499 500 /* 501 * Enquiry3 structure 502 */ 503 struct amr_enquiry3 504 { 505 uint32_t ae_datasize; /* "dataSize", current size */ 506 /* in bytes(resvd excluded) */ 507 struct amr_notify ae_notify; /* "notify", event notify */ 508 /* structure */ 509 uint8_t ae_rebuildrate; /* "rbldRate", current */ 510 /* rebuild rate in % */ 511 uint8_t ae_cacheflush; /* "cacheFlushInterval", */ 512 /* flush interval in seconds */ 513 uint8_t ae_sensealert; /* "senseAlert" */ 514 uint8_t ae_driveinsertcount; /* "driveInsertedCount", */ 515 /* count of inserted drives */ 516 uint8_t ae_batterystatus; /* "batteryStatus" */ 517 uint8_t ae_numldrives; /* "numLDrv", number of logic */ 518 /* drivers configured */ 519 uint8_t ae_reconstate[AMR_40LD_MAXDRIVES/8]; 520 /* "reconState", */ 521 /* reconstruction state */ 522 uint16_t ae_opstatus[AMR_40LD_MAXDRIVES/8]; 523 /* "lDrvOpStatus", operation */ 524 /* state per logic driver */ 525 uint32_t ae_drivesize[AMR_40LD_MAXDRIVES]; 526 /* "lDrvSize", size of each */ 527 /* logic driver */ 528 uint8_t ae_driveprop[AMR_40LD_MAXDRIVES]; 529 /* "lDrvProp", properties of */ 530 /* each logic driver */ 531 uint8_t ae_drivestate[AMR_40LD_MAXDRIVES]; 532 /* "lDrvState", state of */ 533 /* each logic driver */ 534 uint8_t ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; 535 /* "pDrvState", state of each */ 536 /* physical driver */ 537 uint16_t ae_pdriveformat[AMR_40LD_MAXPHYSDRIVES/16]; 538 /* "physDrvFormat" */ 539 uint8_t ae_targxfer[80]; /* "targXfer", physical drive */ 540 /* transfer rates */ 541 uint8_t res1[263]; /* pad to 1024 bytes */ 542 }; 543 544 /* 545 * Product Info structure. Query for this via AMR_CONFIG_PRODUCT_INFO. 546 */ 547 struct amr_prodinfo 548 { 549 uint32_t ap_size; /* "DataSize", current size */ 550 /* in bytes */ 551 uint32_t ap_configsig; /* "ConfigSignature", default */ 552 /* is 0x00282008, indicating */ 553 /* 0x28 max logical drives, */ 554 /* 0x20 maximum stripes and */ 555 /* 0x08 maximum spans */ 556 uint8_t ap_firmware[16]; /* "FwVer", firmware version */ 557 uint8_t ap_bios[16]; /* "BiosVer", Bios version */ 558 uint8_t ap_product[80]; /* "ProductName", prod name */ 559 uint8_t ap_maxio; /* "MaxConcCmds", max number */ 560 /* of concurrent commands */ 561 uint8_t ap_nschan; /* "SCSIChanPresent", number */ 562 /* of SCSI channels present */ 563 uint8_t ap_fcloops; /* "FCLoopPresent", number of */ 564 /* fibre loops present */ 565 uint8_t ap_memtype; /* "memType", memory type */ 566 uint32_t ap_signature; /* "signature" */ 567 uint16_t ap_memsize; /* "DramSize", onboard memory */ 568 /* in MB */ 569 uint16_t ap_subsystem; /* "subSystemID", subsystem */ 570 /* identifier */ 571 uint16_t ap_subvendor; /* "subSystemVendorID" */ 572 uint8_t ap_numnotifyctr; /* "numNotifyCounters", num */ 573 /* of notify counters */ 574 }; 575 576 /* 577 * The union for used enquiry commands 578 */ 579 union amr_enq_buffer 580 { 581 struct amr_enquiry3 aeb_enquiry3; 582 struct amr_enquiry aeb_enquiry; 583 struct amr_prodinfo aeb_prodinfo; 584 }; 585 586 #pragma pack() 587 588 #ifdef _KERNEL 589 590 /* 591 * I/O Port offsets 592 */ 593 #define ACK_BYTE 0x08 594 #define I_CMD_PORT 0x00 595 #define I_ACK_PORT 0x00 596 #define I_TOGGLE_PORT 0x01 597 #define INTR_PORT 0x0a 598 #define ENABLE_INTR_BYTE 0xc0 599 #define DISABLE_INTR_BYTE 0x00 600 #define AMR_QINTR 0x0a 601 #define AMR_QINTR_VALID 0x40 602 603 #define AMR_QGET_ISTAT(sc) pci_config_get8(sc->regsmap_handle, AMR_QINTR) 604 #define AMR_QCLEAR_INTR(sc) pci_config_put8(sc->regsmap_handle, \ 605 I_ACK_PORT, ACK_BYTE) 606 #define AMR_QENABLE_INTR(sc) pci_config_put8(sc->regsmap_handle, \ 607 I_TOGGLE_PORT, ENABLE_INTR_BYTE) 608 #define AMR_QDISABLE_INTR(sc) pci_config_put8(sc->regsmap_handle, \ 609 I_TOGGLE_PORT, DISABLE_INTR_BYTE) 610 #define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 611 #define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 612 #define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 613 614 /* 615 * Doorbell registers 616 */ 617 #define AMR_QIDB 0x20 618 #define AMR_QODB 0x2c 619 #define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 620 #define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 621 #define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 622 623 /* 624 * Initialisation status 625 */ 626 #define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 627 #define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 628 #define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 629 #define AMR_QINIT_INPROG 0xdc /* init in progress */ 630 #define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 631 #define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 632 #define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 633 #define AMR_QINIT_DONE 0x9c /* init successfully done */ 634 635 /* 636 * I/O primitives 637 */ 638 #define AMR_QPUT_IDB(sc, val) pci_config_put32(sc->regsmap_handle, \ 639 AMR_QIDB, val) 640 #define AMR_QGET_IDB(sc) pci_config_get32(sc->regsmap_handle, \ 641 AMR_QIDB) 642 #define AMR_QPUT_ODB(sc, val) pci_config_put32(sc->regsmap_handle, \ 643 AMR_QODB, val) 644 #define AMR_QGET_ODB(sc) pci_config_get32(sc->regsmap_handle, \ 645 AMR_QODB) 646 647 /* 648 * I/O registers 649 */ 650 #define AMR_SCMD 0x10 /* command/ack register (write) */ 651 #define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 652 #define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 653 #define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 654 #define AMR_SMBOX_1 0x15 655 #define AMR_SMBOX_2 0x16 656 #define AMR_SMBOX_3 0x17 /* high byte */ 657 #define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 658 #define AMR_SINTR 0x1a /* interrupt status */ 659 660 /* 661 * I/O magic numbers 662 */ 663 #define AMR_SCMD_POST 0x10 /* SCMD to initiate action on mailbox */ 664 #define AMR_SCMD_ACKINTR 0x08 /* SCMD to ack mailbox retrieved */ 665 #define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 666 #define AMR_SINTR_VALID 0x40 /* in SINTR */ 667 #define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 668 #define AMR_SMBOX_ADDR 0x00 /* SMBOX_ENABLE */ 669 670 /* 671 * Initialisation status 672 */ 673 #define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 674 #define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 675 #define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 676 #define AMR_SINIT_INPROG 0x11 /* init in progress */ 677 #define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 678 #define AMR_SINIT_DONE 0x99 /* init successfully done */ 679 680 /* 681 * I/O primitives 682 */ 683 #define AMR_SPUT_ISTAT(sc, val) pci_config_put8(sc->regsmap_handle, \ 684 AMR_SINTR, val) 685 #define AMR_SGET_ISTAT(sc) pci_config_get8(sc->regsmap_handle, AMR_SINTR) 686 #define AMR_SACK_INTERRUPT(sc) pci_config_put8(sc->regsmap_handle, \ 687 AMR_SCMD, AMR_SCMD_ACKINTR) 688 #define AMR_SPOST_COMMAND(sc) pci_config_put8(sc->regsmap_handle, AMR_SCMD, \ 689 AMR_SCMD_POST) 690 #define AMR_SGET_MBSTAT(sc) pci_config_get8(sc->regsmap_handle, \ 691 AMR_SMBOX_BUSY) 692 693 #define AMR_SENABLE_INTR(sc) \ 694 pci_config_put8(sc->regsmap_handle, AMR_STOGGLE, \ 695 pci_config_get8(sc->regsmap_handle, AMR_STOGGLE) \ 696 | AMR_STOGL_IENABLE) 697 698 #define AMR_SDISABLE_INTR(sc) \ 699 pci_config_put8(sc->regsmap_handle, AMR_STOGGLE, \ 700 pci_config_get8(sc->regsmap_handle, AMR_STOGGLE) \ 701 & ~AMR_STOGL_IENABLE) 702 703 #define AMR_SBYTE_SET(sc, reg, val) pci_config_put8(sc->regsmap_handle, \ 704 reg, val) 705 706 #endif /* _KERNEL */ 707 708 #ifdef __cplusplus 709 } 710 #endif 711 712 #endif /* _AMRREG_H */ 713