1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef AMD8111S_MAIN_H 28 #define AMD8111S_MAIN_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions are met: 37 * 38 * + Redistributions of source code must retain the above copyright notice, 39 * + this list of conditions and the following disclaimer. 40 * 41 * + Redistributions in binary form must reproduce the above copyright 42 * + notice, this list of conditions and the following disclaimer in the 43 * + documentation and/or other materials provided with the distribution. 44 * 45 * + Neither the name of Advanced Micro Devices, Inc. nor the names of its 46 * + contributors may be used to endorse or promote products derived from 47 * + this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 50 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 51 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 52 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 53 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR 54 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 57 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 60 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 61 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * Import/Export/Re-Export/Use/Release/Transfer Restrictions and 64 * Compliance with Applicable Laws. Notice is hereby given that 65 * the software may be subject to restrictions on use, release, 66 * transfer, importation, exportation and/or re-exportation under 67 * the laws and regulations of the United States or other 68 * countries ("Applicable Laws"), which include but are not 69 * limited to U.S. export control laws such as the Export 70 * Administration Regulations and national security controls as 71 * defined thereunder, as well as State Department controls under 72 * the U.S. Munitions List. Permission to use and/or 73 * redistribute the software is conditioned upon compliance with 74 * all Applicable Laws, including U.S. export control laws 75 * regarding specifically designated persons, countries and 76 * nationals of countries subject to national security controls. 77 */ 78 79 80 #pragma ident "@(#)$RCSfile: odl.h,v $ $Revision: 1.1 $ " \ 81 "$Date: 2004/04/22 15:22:52 $ AMD" 82 83 #include <sys/types.h> 84 #include <sys/errno.h> 85 #include <sys/kmem.h> 86 #include <sys/conf.h> 87 #include <sys/stat.h> 88 #include <sys/note.h> 89 #include <sys/modctl.h> 90 91 #include <sys/stream.h> 92 #include <sys/strsubr.h> 93 #include <sys/strsun.h> 94 95 #include <sys/dditypes.h> 96 #include <sys/ddi.h> 97 #include <sys/sunddi.h> 98 99 #include <sys/pci.h> 100 101 #include <sys/ethernet.h> 102 #include <sys/dlpi.h> 103 #include <sys/mac.h> 104 #include <sys/mac_ether.h> 105 #include <sys/netlb.h> 106 #include "amd8111s_hw.h" 107 108 #define MEM_REQ_MAX 100 109 #define MEMSET 4 110 111 #define IOC_LINESIZE 40 112 113 /* 114 * Loopback definitions 115 */ 116 #define AMD8111S_LB_NONE 0 117 #define AMD8111S_LB_EXTERNAL_1000 1 118 #define AMD8111S_LB_EXTERNAL_100 2 119 #define AMD8111S_LB_EXTERNAL_10 3 120 #define AMD8111S_LB_INTERNAL_PHY 4 121 #define AMD8111S_LB_INTERNAL_MAC 5 122 123 /* ((2 ^ (32 - 1)) * 8) / (10 ^ 8) >= 100 */ 124 #define AMD8111S_DUMP_MIB_SECONDS_THRESHOLD 100 125 #define AMD8111S_DUMP_MIB_BYTES_THRESHOLD 0x80000000 126 127 /* Bit flags for 'attach_progress' */ 128 #define AMD8111S_ATTACH_PCI 0x0001 /* pci_config_setup() */ 129 #define AMD8111S_ATTACH_RESOURCE 0x0002 /* odlInit() */ 130 #define AMD8111S_ATTACH_REGS 0x0004 /* ddi_regs_map_setup() */ 131 #define AMD8111S_ATTACH_INTRADDED 0x0010 /* intr_add() */ 132 #define AMD8111S_ATTACH_MACREGED 0x0020 /* mac_register() */ 133 #define AMD8111S_ATTACH_RESCHED 0x0040 /* soft_intr() */ 134 135 #define AMD8111S_TRY_SEND 0x0001 136 #define AMD8111S_SEND_READY 0x0002 137 138 #define NEXT(buf, ptr) \ 139 (buf.ptr + 1 >= buf.msg_buf + \ 140 buf.ring_size ? \ 141 buf.msg_buf : \ 142 buf.ptr + 1) 143 /* 144 * (Internal) return values from ioctl subroutines 145 */ 146 enum ioc_reply { 147 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 148 IOC_DONE, /* OK, reply sent */ 149 IOC_ACK, /* OK, just send ACK */ 150 IOC_REPLY, /* OK, just send reply */ 151 IOC_RESTART_ACK, /* OK, restart & ACK */ 152 IOC_RESTART_REPLY /* OK, restart & reply */ 153 }; 154 155 typedef int (*TIMERfUNC) (struct LayerPointers *); 156 157 struct TimerStructure { 158 int Type; 159 int Period; /* in milliseconds */ 160 timeout_id_t TimerHandle; 161 int (*TimerFunptr)(struct LayerPointers *); 162 struct LayerPointers *pLayerPointers; 163 }; 164 165 struct amd8111s_statistics 166 { 167 uint64_t intr_TINT0; /* # of TINT0 (Tx interrupts) */ 168 uint64_t intr_RINT0; /* # of RINT0 (Rx interrupts) */ 169 uint64_t intr_STINT; /* # of STINT (Software Timer Intr) */ 170 uint64_t intr_OTHER; /* Intr caused by other device */ 171 172 uint64_t tx_ok_packets; 173 uint64_t tx_no_descriptor; 174 uint64_t tx_no_buffer; 175 uint64_t tx_rescheduled; 176 uint64_t tx_unrescheduled; 177 178 /* # of call amd8111s_dump_mib function */ 179 uint64_t mib_dump_counter; 180 181 /* 182 * From MIB registers (TX) 183 */ 184 uint64_t tx_mib_packets; /* # of packets */ 185 uint64_t tx_mib_multicst_packets; /* # of multicast packets */ 186 uint64_t tx_mib_broadcst_packets; /* # of broadcast packets */ 187 uint64_t tx_mib_flowctrl_packets; /* # of flow ctrl packets */ 188 189 uint64_t tx_mib_bytes; /* # of all Tx bytes */ 190 191 /* Packet drop due to Tx FIFO underrun */ 192 uint64_t tx_mib_underrun_packets; 193 uint64_t tx_mib_collision_packets; 194 /* Packets successfully transmitted after experiencing one collision */ 195 uint64_t tx_mib_one_coll_packets; 196 uint64_t tx_mib_multi_coll_packets; 197 /* # of late collisions that occur */ 198 uint64_t tx_mib_late_coll_packets; 199 uint64_t tx_mib_ex_coll_packets; /* excessive collision */ 200 uint64_t tx_mib_oversize_packets; 201 uint64_t tx_mib_defer_trans_packets; /* defer transmit */ 202 203 204 /* 205 * Some error counter after "ifconfig amd8111sX unplumb" 206 */ 207 /* 208 * Count Tx mp number from GLD even after NIC has been unplumbed. 209 * This value should always be 0. 210 */ 211 uint64_t tx_afterunplumb; 212 /* 213 * We drain all pending tx packets during unplumb operation. This 214 * variable is to count the drain time. 215 * 30 means success; =30 means fail 216 */ 217 uint64_t tx_draintime; 218 219 uint64_t rx_ok_packets; /* # of all good packets */ 220 uint64_t rx_allocfail; /* alloc memory fail during Rx */ 221 uint64_t rx_error_zerosize; 222 223 uint64_t rx_0_packets; 224 uint64_t rx_1_15_packets; 225 uint64_t rx_16_31_packets; 226 uint64_t rx_32_47_packets; 227 uint64_t rx_48_63_packets; 228 uint64_t rx_double_overflow; 229 230 uint64_t rx_desc_err; 231 uint64_t rx_desc_err_FRAM; /* Framing error */ 232 uint64_t rx_desc_err_OFLO; /* Overflow error */ 233 uint64_t rx_desc_err_CRC; /* CRC error */ 234 uint64_t rx_desc_err_BUFF; /* BCRC error */ 235 236 /* 237 * From MIB registers (RX) 238 */ 239 uint64_t rx_mib_unicst_packets; /* # of unicast packets */ 240 uint64_t rx_mib_multicst_packets; /* # of multicast packets */ 241 uint64_t rx_mib_broadcst_packets; /* # of broadcast packets */ 242 uint64_t rx_mib_macctrl_packets; /* # of mac ctrl packets */ 243 uint64_t rx_mib_flowctrl_packets; /* # of flow ctrl packets */ 244 245 uint64_t rx_mib_bytes; /* # of all Rx bytes */ 246 uint64_t rx_mib_good_bytes; /* # of all Rx bytes */ 247 /* 248 * The total number of valid frames received that are less than 64 249 * bytes long (include the FCS). 250 */ 251 uint64_t rx_mib_undersize_packets; 252 /* 253 * The total number of valid frames received that are greater than the 254 * maximum valid frame size (include the FCS). 255 */ 256 uint64_t rx_mib_oversize_packets; 257 258 uint64_t rx_mib_align_err_packets; 259 uint64_t rx_mib_fcs_err_packets; /* has a bad FCS */ 260 /* Invalid data symbol (RX_ER) */ 261 uint64_t rx_mib_symbol_err_packets; 262 /* Packets that were dropped because no descriptor was available */ 263 uint64_t rx_mib_drop_packets; 264 /* 265 * Packets that were dropped due to lack of resources. This includes 266 * the number of times a packet was dropped due to receive FIFO 267 * overflow and lack of receive descriptor. 268 */ 269 uint64_t rx_mib_miss_packets; 270 }; 271 272 struct amd8111s_msgbuf { 273 uint64_t phy_addr; 274 caddr_t vir_addr; 275 uint32_t msg_size; 276 ddi_dma_handle_t p_hdl; 277 uint32_t offset; 278 }; 279 280 struct amd8111s_dma_ringbuf { 281 ddi_dma_handle_t *dma_hdl; 282 ddi_acc_handle_t *acc_hdl; 283 ddi_dma_cookie_t *dma_cookie; 284 caddr_t *trunk_addr; 285 uint32_t buf_sz; 286 uint32_t trunk_sz; 287 uint32_t trunk_num; 288 struct amd8111s_msgbuf *msg_buf; 289 uint32_t ring_size; 290 uint32_t dma_buf_sz; 291 struct amd8111s_msgbuf *free; 292 struct amd8111s_msgbuf *next; 293 struct amd8111s_msgbuf *curr; 294 295 kmutex_t ring_lock; 296 }; 297 298 struct odl { 299 dev_info_t *devinfo; 300 301 mac_handle_t mh; /* mac module handle */ 302 mac_resource_handle_t mrh; 303 304 struct amd8111s_statistics statistics; 305 306 /* Locks */ 307 kmutex_t mdlSendLock; 308 kmutex_t mdlRcvLock; 309 kmutex_t timer_lock; 310 kmutex_t send_cv_lock; 311 kcondvar_t send_cv; 312 313 ddi_softintr_t drain_id; 314 /* 315 * The chip_lock assures that the Rx/Tx process must be stopped while 316 * other functions change the hardware configuration, such as attach() 317 * detach() etc are executed. 318 */ 319 krwlock_t chip_lock; 320 321 /* 322 * HW operators and parameters on attach period 323 */ 324 ddi_iblock_cookie_t iblock; /* HW: interrupt block cookie */ 325 ddi_acc_handle_t MemBasehandle; 326 327 /* For pci configuration */ 328 ddi_acc_handle_t pci_handle; /* HW: access handle of PCI space */ 329 uint16_t vendor_id; 330 uint16_t device_id; 331 332 /* 333 * FreeQ: Transfer Rx Buffer parameters from top layer to low layers. 334 * Format of parameter: 335 * (struct RxBufInfo *, physical address) 336 */ 337 unsigned long FreeQ[2 * RX_RING_SIZE]; 338 unsigned long *FreeQStart; 339 unsigned long *FreeQEnd; 340 long *FreeQWrite; 341 long *FreeQRead; 342 343 /* For Rx descriptors */ 344 ddi_dma_handle_t rx_desc_dma_handle; 345 ddi_acc_handle_t rx_desc_acc_handle; 346 ddi_dma_cookie_t rx_desc_dma_cookie; 347 348 /* For Tx descriptors */ 349 ddi_dma_handle_t tx_desc_dma_handle; 350 ddi_acc_handle_t tx_desc_acc_handle; 351 ddi_dma_cookie_t tx_desc_dma_cookie; 352 353 /* For Tx buffers */ 354 struct amd8111s_dma_ringbuf tx_buf; 355 356 /* For Rx buffers */ 357 struct amd8111s_dma_ringbuf rx_buf; 358 359 ether_addr_t MacAddress; /* Mac address */ 360 361 /* Multicast addresses table */ 362 UCHAR MulticastAddresses 363 [MAX_MULTICAST_ADDRESSES][ETH_LENGTH_OF_ADDRESS]; 364 365 link_state_t LinkStatus; 366 367 /* Timer */ 368 timeout_id_t Timer_id; 369 int (*TimerFunc)(struct LayerPointers *); 370 int timer_run; 371 int timer_linkdown; 372 373 unsigned int dump_mib_seconds; 374 375 uint32_t loopback_mode; 376 unsigned int rx_fcs_stripped; 377 378 unsigned int rx_overflow_counter; 379 unsigned int pause_interval; 380 381 }; 382 383 #endif /* AMD8111S_MAIN_H */ 384