1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef AMD8111S_HW_H 28 #define AMD8111S_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions are met: 37 * 38 * + Redistributions of source code must retain the above copyright notice, 39 * + this list of conditions and the following disclaimer. 40 * 41 * + Redistributions in binary form must reproduce the above copyright 42 * + notice, this list of conditions and the following disclaimer in the 43 * + documentation and/or other materials provided with the distribution. 44 * 45 * + Neither the name of Advanced Micro Devices, Inc. nor the names of its 46 * + contributors may be used to endorse or promote products derived from 47 * + this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 50 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 51 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 52 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 53 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR 54 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 57 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 60 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 61 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * Import/Export/Re-Export/Use/Release/Transfer Restrictions and 64 * Compliance with Applicable Laws. Notice is hereby given that 65 * the software may be subject to restrictions on use, release, 66 * transfer, importation, exportation and/or re-exportation under 67 * the laws and regulations of the United States or other 68 * countries ("Applicable Laws"), which include but are not 69 * limited to U.S. export control laws such as the Export 70 * Administration Regulations and national security controls as 71 * defined thereunder, as well as State Department controls under 72 * the U.S. Munitions List. Permission to use and/or 73 * redistribute the software is conditioned upon compliance with 74 * all Applicable Laws, including U.S. export control laws 75 * regarding specifically designated persons, countries and 76 * nationals of countries subject to national security controls. 77 */ 78 79 80 /* Definitions for the type of Memory allocations needed */ 81 82 #define ETH_LENGTH_OF_ADDRESS 6 83 #define ETH_MAC_HDR_SIZE 14 84 85 86 #define ADD_MULTICAST 1 87 88 #define ENABLE_MULTICAST 2 89 #define DISABLE_MULTICAST 3 90 91 #define ENABLE_ALL_MULTICAST 4 92 #define DISABLE_ALL_MULTICAST 5 93 94 #define ENABLE_BROADCAST 6 95 #define DISABLE_BROADCAST 7 96 97 #define ADD_WAKE_UP_PATTERN 8 98 #define REMOVE_WAKE_UP_PATTERN 9 99 #define ENABLE_MAGIC_PACKET_WAKE_UP 10 100 101 #define SET_SINGLE_MULTICAST 11 102 #define UNSET_SINGLE_MULTICAST 12 103 #define DELETE_MULTICAST 13 104 105 #define LINK_DOWN 1 106 #define LINK_UP 2 107 #define LINK_UNKNOWN 3 108 109 /* Setting the MODE */ 110 #define PROMISCOUS 1 111 #define DISABLE_PROM 2 112 113 #define VIRTUAL 1 114 115 #define ALIGNMENT 0x0f 116 117 #define TX_RING_LEN_BITS 10 /* 1024 descriptors */ 118 #define RX_RING_LEN_BITS 10 /* 1024 descriptors */ 119 #define TX_BUF_SIZE 2048 120 #define RX_BUF_SIZE 2048 121 122 #define TX_RING_SIZE (1 << (TX_RING_LEN_BITS)) 123 #define TX_COALESC_SIZE (1 << 11) 124 #define TX_RING_MOD_MASK (2 * TX_RING_SIZE - 1) 125 126 #define TX_RESCHEDULE_THRESHOLD (TX_RING_SIZE >> 1) 127 128 #define RX_RING_SIZE (1 << (RX_RING_LEN_BITS)) 129 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) 130 131 #define MAX_MULTICAST_ADDRESSES 32 132 #define JUMBO_ENABLED 0 133 #define JUMBO_DISABLED 1 134 135 /* Default value of IPG convergence time */ 136 #define MIN_IPG_DEFAULT 96 137 #define MAX_IPG_DEFAULT 255 138 #define MAX_BUFFER_COUNT 8 /* full coalesce */ 139 140 #define ULONG unsigned long 141 #define UCHAR unsigned char 142 143 /* Generic MII registers. */ 144 #define MII_BMCR 0x00 /* Basic mode control register */ 145 #define MII_BMSR 0x01 /* Basic mode status register */ 146 #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 147 #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 148 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 149 #define MII_LPA 0x05 /* Link partner ability reg */ 150 #define MII_EXPANSION 0x06 /* Expansion register */ 151 #define MII_DCOUNTER 0x12 /* Disconnect counter */ 152 #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 153 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 154 #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 155 #define MII_SREVISION 0x16 /* Silicon revision */ 156 #define MII_RESV1 0x17 /* Reserved... */ 157 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 158 #define MII_PHYADDR 0x19 /* PHY address */ 159 #define MII_RESV2 0x1a /* Reserved... */ 160 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 161 #define MII_NCONFIG 0x1c /* Network interface config */ 162 163 164 #define DEVICE_ID 0x744b 165 #define VENDOR_ID 0x1022 166 167 /* L4 Chip Name */ 168 #define DEVICE_CHIPNAME "Memory_Map_L7 AMDIDC" 169 170 /* Error Status Registers */ 171 #define MIB_OFFSET 0x28 172 173 /* 174 * MIB counter definitions 175 */ 176 #define RcvMissPkts 0x00 177 #define RcvOctets 0x01 178 #define RcvBroadCastPkts 0x02 179 #define RcvMultiCastPkts 0x03 180 #define RcvUndersizePkts 0x04 181 #define RcvOversizePkts 0x05 182 #define RcvFragments 0x06 183 #define RcvJabbers 0x07 184 #define RcvUniCastPkts 0x08 185 #define RcvAlignmentErrors 0x09 186 #define RcvFCSErrors 0x0a 187 #define RcvGoodOctets 0x0b 188 #define RcvMACCtrl 0x0c 189 #define RcvFlowCtrl 0x0d 190 #define RcvPkts64Octets 0x0e 191 #define RcvPkts65to127Octets 0x0f 192 #define RcvPkts128to255Octets 0x10 193 #define RcvPkts256to511Octets 0x11 194 #define RcvPkts512to1023Octets 0x12 195 #define RcvPkts1024to1518Octets 0x13 196 #define RcvUnsupportedOpcode 0x14 197 #define RcvSymbolErrors 0x15 198 #define RcvDropPktsRing0 0x16 199 200 #define XmtUnderrunPkts 0x20 201 #define XmtOctets 0x21 202 #define XmtPackets 0x22 203 #define XmtBroadCastPkts 0x23 204 #define XmtMultiCastPkts 0x24 205 #define XmtCollisions 0x25 206 #define XmtUniCastPkts 0x26 207 #define XmtOneCollision 0x27 208 #define XmtMultipleCollision 0x28 209 #define XmtDeferredTransmit 0x29 210 #define XmtLateCollision 0x2a 211 #define XmtExcessiveDefer 0x2b 212 #define XmtLossCarrier 0x2c 213 #define XmtExcessiveCollision 0x2d 214 #define XmtBackPressure 0x2e 215 #define XmtFlowCtrl 0x2f 216 #define XmtPkts64Octets 0x30 217 #define XmtPkts65to127Octets 0x31 218 #define XmtPkts128to255Octets 0x32 219 #define XmtPkts256to511Octets 0x33 220 #define XmtPkts512to1023Octets 0x34 221 #define XmtPkts1024to1518Octets 0x35 222 #define XmtOversizePkts 0x36 223 224 /* Link Status */ 225 #define SPEED_MASK 0x0380 /* B9 .. B7 */ 226 #define SPEED_100Mbps 0x0180 227 #define SPEED_10Mbps 0x0100 228 229 230 /* PMR (Pattern Match RAM) */ 231 #define MAX_ALLOWED_PATTERNS 8 232 #define MAX_PATTERNS 1024 233 #define ALL_MULTI B16_MASK 234 #define ONLY_MULTI B15_MASK 235 236 #define B31_MASK 0x80000000 237 #define B30_MASK 0x40000000 238 #define B29_MASK 0x20000000 239 #define B28_MASK 0x10000000 240 #define B27_MASK 0x08000000 241 #define B26_MASK 0x04000000 242 #define B25_MASK 0x02000000 243 #define B24_MASK 0x01000000 244 #define B23_MASK 0x00800000 245 #define B22_MASK 0x00400000 246 #define B21_MASK 0x00200000 247 #define B20_MASK 0x00100000 248 #define B19_MASK 0x00080000 249 #define B18_MASK 0x00040000 250 #define B17_MASK 0x00020000 251 #define B16_MASK 0x00010000 252 253 #define B15_MASK 0x8000 254 #define B14_MASK 0x4000 255 #define B13_MASK 0x2000 256 #define B12_MASK 0x1000 257 #define B11_MASK 0x0800 258 #define B10_MASK 0x0400 259 #define B9_MASK 0x0200 260 #define B8_MASK 0x0100 261 #define B7_MASK 0x0080 262 #define B6_MASK 0x0040 263 #define B5_MASK 0x0020 264 #define B4_MASK 0x0010 265 #define B3_MASK 0x0008 266 #define B2_MASK 0x0004 267 #define B1_MASK 0x0002 268 #define B0_MASK 0x0001 269 270 /* PCI register offset */ 271 /* required by odl in getting the Memory Base Address */ 272 #define MEMBASE_MASK 0xFFFFF000 273 #define PCI_CAP_ID_REG_OFFSET 0x34 274 #define PCI_PMC_REG_OFFSET 0x36 275 #define PCI_PMCSR_REG_OFFSET 0x38 276 #define MIB_OFFSET 0x28 277 #define STAT_ASF 0x00 /* 32bit register */ 278 279 #define FORCED_PHY_MASK 0xFF07 280 281 /* Offset of Drifrent Registers */ 282 #define AP_VALUE 0x98 /* 32bit register */ 283 #define AUTOPOLL0 0x88 /* 16bit register */ 284 #define AUTOPOLL1 0x8A /* 16bit register */ 285 #define AUTOPOLL2 0x8C /* 16bit register */ 286 #define AUTOPOLL3 0x8E /* 16bit register */ 287 #define AUTOPOLL4 0x90 /* 16bit register */ 288 #define AUTOPOLL5 0x92 /* 16bit register */ 289 /* Receive Ring Base Address Registers . */ 290 #define RCV_RING_BASE_ADDR0 0x120 /* 64bit register */ 291 /* Transmit Ring Base Address */ 292 #define XMT_RING_BASE_ADDR0 0x100 /* 64bit register */ 293 #define XMT_RING_BASE_ADDR1 0x108 /* 64bit register */ 294 #define XMT_RING_BASE_ADDR2 0x110 /* 64bit register */ 295 #define XMT_RING_BASE_ADDR3 0x118 /* 64bit register */ 296 /* CAM ADDRESS */ 297 #define CAM_ADDR 0x1A0 /* 16bit register */ 298 #define CAM_DATA 0x198 /* 64bit register */ 299 /* CHIP ID */ 300 #define CHIPID 0x004 /* 32bit register */ 301 /* COMMAND STYLE REGISTERS */ 302 #define CMD0 0x48 /* 32bit register */ 303 #define CMD2 0x50 /* 32bit register */ 304 #define CMD3 0x54 /* 32bit register */ 305 #define CMD7 0x64 /* 32bit register */ 306 /* CONTRIOL REGISTER */ 307 #define CTRL1 0x6C /* 32bit register */ 308 #define CTRL2 0x70 /* 32bit register */ 309 /* DELAY INTERRUPT REGISTER */ 310 #define DLY_INT_A 0xA8 /* 32bit register */ 311 #define DLY_INT_B 0xAC /* 32bit register */ 312 /* FLOW CONTROL REGISTER */ 313 #define FLOW_CONTROL 0xC8 /* 32bit register */ 314 /* INTER FRAME SPACING */ 315 #define IFS 0x18E /* 16bit register */ 316 #define IFS1 0x18C /* 8bit register */ 317 /* INTERRUPT REGISTER */ 318 #define INT0 0x38 /* 32bit register */ 319 #define INTEN0 0x40 /* 32bit register */ 320 /* LOGICAL ADDRESS */ 321 #define LADRF1 0x168 /* 64bit register */ 322 /* MIB ADDRESS REGISTER */ 323 #define MIB_ADDR 0x14 /* 16bit register */ 324 #define MIB_DATA 0x10 /* 32bit register */ 325 /* MAC ADDRESS */ 326 #define PADR 0x160 /* 48bit register */ 327 /* PHY ADDRESS */ 328 #define PHY_ACCESS 0xD0 /* 32bit register */ 329 /* PATTERN REGISTER */ 330 #define PMAT0 0x190 /* 32bit register */ 331 #define PMAT1 0x194 /* 32bit register */ 332 /* RECEIVE RING LENGTH OFFSET */ 333 #define RCV_RING_LEN0 0x150 /* 16bit register */ 334 /* SRAM BOUNDARY */ 335 #define SRAM_BOUNDARY 0x17A /* 16bit register */ 336 #define SRAM_SIZE 0x178 /* 16bit register */ 337 /* STATUS REGISTER */ 338 #define STAT0 0x30 /* 32bit register */ 339 #define STVAL 0xD8 /* 32bit register */ 340 #define TEST0 0x1A8 /* 32bit register */ 341 #define XMT_RING_LEN0 0x140 /* 16bit register */ 342 #define XMT_RING_LEN1 0x144 /* 16bit register */ 343 #define XMT_RING_LEN2 0x148 /* 16bit register */ 344 #define XMT_RING_LEN3 0x14C /* 16bit register */ 345 #define XMT_RING_LIMIT 0x7C /* 32bit register */ 346 347 348 349 #define RCV_RING_LEN1 0x154 /* 16bit register */ 350 #define RCV_RING_LEN2 0x158 /* 16bit register */ 351 #define RCV_RING_LEN3 0x15C /* 16bit register */ 352 #define FFC_THRESH 0xCC /* 32bit register */ 353 #define RCV_RING_BASE_ADDR1 0x128 /* 64bit register */ 354 #define RCV_RING_BASE_ADDR2 0x130 /* 64bit register */ 355 #define RCV_RING_BASE_ADDR3 0x138 /* 64bit register */ 356 #define RCV_RING_CFG 0x78 /* 16bit register */ 357 #define PCS_ANEG 0x9C /* 32bit register */ 358 #define PCS_RCFG 0xA0 /* 32bit register */ 359 #define PCS_XCFG 0xA4 /* 32bit register */ 360 #define DFC_INDEX2 0xB8 /* 16bit register */ 361 #define DFC_INDEX3 0xBA /* 16bit register */ 362 #define DFC_INDEX0 0xBC /* 16bit register */ 363 #define DFC_INDEX1 0xBE /* 16bit register */ 364 #define DFC_THRESH2 0xC0 /* 16bit register */ 365 #define DFC_THRESH3 0xC2 /* 16bit register */ 366 #define DFC_THRESH0 0xC4 /* 16bit register */ 367 #define DFC_THRESH1 0xC6 /* 16bit register */ 368 #define PAUSE_CNT 0xDE /* 32bit register */ 369 #define LED0 0xE0 /* 16bit register */ 370 #define LED1 0xE2 /* 16bit register */ 371 #define LED2 0xE4 /* 16bit register */ 372 #define LED3 0xE6 /* 16bit register */ 373 374 375 #define EEPROM_ACC 0x17C /* 16bit register */ 376 377 378 /* Register Bit Definitions */ 379 /* STAT_ASF 0x00, 32bit register */ 380 #define ASF_INIT_DONE B1_MASK 381 #define ASF_INIT_PRESENT B0_MASK 382 383 /* MIB_ADDR 0x14, 16bit register */ 384 #define MIB_CMD_ACTIVE B15_MASK 385 #define MIB_RD_CMD B13_MASK 386 #define MIB_CLEAR B12_MASK 387 #define MIB_ADDRESS 0x0000003F /* 5:0 */ 388 389 /* QOS_ADDR 0x1C, 16bit register */ 390 #define QOS_CMD_ACTIVE B15_MASK 391 #define QOS_WR_CMD B14_MASK 392 #define QOS_RD_CMD B13_MASK 393 #define QOS_ADDRESS 0x0000001F /* 4:0 */ 394 395 /* STAT0 0x30, 32bit register */ 396 #define PAUSE_PEND B14_MASK 397 #define PAUSING B13_MASK 398 #define PMAT_DET B12_MASK 399 #define MP_DET B11_MASK 400 #define LC_DET B10_MASK 401 #define SPEED_MASK 0x0380 /* 9:7 */ 402 #define FULL_DPLX B6_MASK 403 #define LINK_STAT B5_MASK 404 #define AUTONEG_COMPLETE B4_MASK 405 /* #define MIIPD B3_MASK */ 406 #define RX_SUSPENDED B2_MASK 407 #define TX_SUSPENDED B1_MASK 408 #define RUNNING B0_MASK 409 410 411 /* INTEN0 0x40, 32bit register */ 412 413 #define VAL3 B31_MASK 414 #define VAL2 B23_MASK 415 #define VAL1 B15_MASK 416 #define VAL0 B7_MASK 417 418 /* VAL3 */ 419 #define PSCINTEN B28_MASK 420 #define LCINTEN B27_MASK 421 #define APINT5EN B26_MASK 422 #define APINT4EN B25_MASK 423 #define APINT3EN B24_MASK 424 425 /* VAL2 */ 426 #define APINT2EN B22_MASK 427 #define APINT1EN B21_MASK 428 #define APINT0EN B20_MASK 429 #define MIIPDTINTEN B19_MASK 430 #define MCCIINTEN B18_MASK 431 #define MCCINTEN B17_MASK 432 #define MREINTEN B16_MASK 433 434 /* VAL1 */ 435 #define SPNDINTEN B14_MASK 436 #define MPINTEN B13_MASK 437 #define SINTEN B12_MASK 438 #define TINTEN3 B11_MASK 439 #define TINTEN2 B10_MASK 440 #define TINTEN1 B9_MASK 441 #define TINTEN0 B8_MASK 442 443 /* VAL0 */ 444 #define STINTEN B4_MASK 445 #define RINTEN3 B3_MASK 446 #define RINTEN2 B2_MASK 447 #define RINTEN1 B1_MASK 448 #define RINTEN0 B0_MASK 449 450 /* CMD0 0x48, 32bit register */ 451 /* VAL2 */ 452 #define RDMD3 B19_MASK 453 #define RDMD2 B18_MASK 454 #define RDMD1 B17_MASK 455 #define RDMD0 B16_MASK 456 457 /* VAL1 */ 458 #define TDMD3 B11_MASK 459 #define TDMD2 B10_MASK 460 #define TDMD1 B9_MASK 461 #define TDMD0 B8_MASK 462 463 /* VAL0 */ 464 #define UINTCMD B6_MASK 465 #define RX_FAST_SPND B5_MASK 466 #define TX_FAST_SPND B4_MASK 467 #define RX_SPND B3_MASK 468 #define TX_SPND B2_MASK 469 #define INTREN B1_MASK 470 #define RUN B0_MASK 471 472 /* CMD2 0x50, 32bit register */ 473 /* VAL3 */ 474 #define CONDUIT_MODE B29_MASK 475 #define PREF_QTAG B28_MASK 476 #define ALT_PRI_OK B27_MASK 477 478 /* VAL2 */ 479 #define CAM_ENABLE B22_MASK 480 #define QOS_ENABLE B21_MASK 481 #define HASH_ENABLE B20_MASK 482 #define RPA B19_MASK 483 #define DRCVPA B18_MASK 484 #define DRCVBC B17_MASK 485 #define PROM B16_MASK 486 487 /* VAL1 */ 488 #define ASTRIP_RCV B13_MASK 489 #define CMD2_RCV_DROP0 B12_MASK 490 #define EMBA B11_MASK 491 #define DXMT2PD B10_MASK 492 #define LTINTEN B9_MASK 493 #define DXMTFCS B8_MASK 494 495 /* VAL0 */ 496 #define APAD_XMT B6_MASK 497 #define DRTY B5_MASK 498 #define INLOOP B4_MASK 499 #define EXLOOP B3_MASK 500 #define REX_RTRY B2_MASK 501 #define REX_UFLO B1_MASK 502 #define REX_LCOL B0_MASK 503 504 /* CMD3 0x54, 32bit register */ 505 506 /* VAL3 */ 507 #define ASF_INIT_DONE_ALIAS B29_MASK 508 509 /* VAL2 */ 510 #define JUMBO B21_MASK 511 #define VSIZE B20_MASK 512 #define VLONLY B19_MASK 513 #define VL_TAG_DEL B18_MASK 514 515 /* VAL1 */ 516 #define EN_PMGR B14_MASK 517 #define INTLEVEL B13_MASK 518 #define FORCE_FULL_DUPLEX B12_MASK 519 #define FORCE_LINK_STATUS B11_MASK 520 #define APEP B10_MASK 521 #define MPPLBA B9_MASK 522 523 /* VAL0 */ 524 #define RESET_PHY_PULSE B2_MASK 525 #define RESET_PHY B1_MASK 526 #define PHY_RST_POL B0_MASK 527 528 /* CMD7 0x64, 32bit register */ 529 /* VAL0 */ 530 #define PMAT_SAVE_MATCH B4_MASK 531 #define PMAT_MODE B3_MASK 532 #define MPEN_SW B1_MASK 533 #define LCMODE_SW B0_MASK 534 535 /* CTRL0 0x68, 32bit register */ 536 #define PHY_SEL 0x03000000 /* 25:24 */ 537 #define RESET_PHY_WIDTH 0x00FF0000 /* 23:16 */ 538 #define BSWP_REGS B10_MASK 539 #define BSWP_DESC B9_MASK 540 #define BSWP_DATA B8_MASK 541 #define CACHE_ALIGN B4_MASK 542 #define BURST_LIMIT 0x0000000F /* 3:0 */ 543 544 /* CTRL1 0x6C, 32bit register */ 545 #define SLOTMOD_MASK 0x03000000 /* 25:24 */ 546 #define XMTSP_MASK 0x300 /* 17:16 */ 547 #define XMTSP_128 0x200 548 #define XMTSP_64 0x100 549 550 /* CTRL2 0x70, 32bit register */ 551 #define FS_MASK 0x00070000 /* 18:16 */ 552 #define FMDC_MASK 0x00000300 /* 9:8 */ 553 #define XPHYRST B7_MASK 554 #define XPHYANE B6_MASK 555 #define XPHYFD B5_MASK 556 #define XPHYSP_100 B3_MASK /* 4:3, 100 Mbps */ 557 #define APDW_MASK 0x00000007 /* 2:0 */ 558 559 /* RCV_RING_CFG 0x78, 16bit register */ 560 #define RCV_DROP3 B11_MASK 561 #define RCV_DROP2 B10_MASK 562 #define RCV_DROP1 B9_MASK 563 #define RCV_DROP0 B8_MASK 564 #define RCV_RING_DEFAULT 0x0030 /* 5:4 */ 565 #define RCV_RING3_EN B3_MASK 566 #define RCV_RING2_EN B2_MASK 567 #define RCV_RING1_EN B1_MASK 568 #define RCV_RING0_EN B0_MASK 569 570 /* XMT_RING_LIMIT 0x7C, 32bit register */ 571 #define XMT_RING2_LIMIT 0x00FF0000 /* 23:16 */ 572 #define XMT_RING1_LIMIT 0x0000FF00 /* 15:8 */ 573 #define XMT_RING0_LIMIT 0x000000FF /* 7:0 */ 574 575 /* AUTOPOLL0 0x88, 16bit register */ 576 #define AP_REG0_EN B15_MASK 577 #define AP_REG0_ADDR_MASK 0x1F00 /* 12:8 */ 578 #define AP_PHY0_ADDR_MASK 0x001F /* 4:0 */ 579 580 /* AUTOPOLL1 0x8A, 16bit register */ 581 #define AP_REG1_EN B15_MASK 582 #define AP_REG1_ADDR_MASK 0x1F00 /* 12:8 */ 583 #define AP_PRE_SUP1 B6_MASK 584 #define AP_PHY1_DFLT B5_MASK 585 #define AP_PHY1_ADDR_MASK 0x001F /* 4:0 */ 586 587 /* AUTOPOLL2 0x8C, 16bit register */ 588 #define AP_REG2_EN B15_MASK 589 #define AP_REG2_ADDR_MASK 0x1F00 /* 12:8 */ 590 #define AP_PRE_SUP2 B6_MASK 591 #define AP_PHY2_DFLT B5_MASK 592 #define AP_PHY2_ADDR_MASK 0x001F /* 4:0 */ 593 594 /* AUTOPOLL3 0x8E, 16bit register */ 595 #define AP_REG3_EN B15_MASK 596 #define AP_REG3_ADDR_MASK 0x1F00 /* 12:8 */ 597 #define AP_PRE_SUP3 B6_MASK 598 #define AP_PHY3_DFLT B5_MASK 599 #define AP_PHY3_ADDR_MASK 0x001F /* 4:0 */ 600 601 /* AUTOPOLL4 0x90, 16bit register */ 602 #define AP_REG4_EN B15_MASK 603 #define AP_REG4_ADDR_MASK 0x1F00 /* 12:8 */ 604 #define AP_PRE_SUP4 B6_MASK 605 #define AP_PHY4_DFLT B5_MASK 606 #define AP_PHY4_ADDR_MASK 0x001F /* 4:0 */ 607 608 /* AUTOPOLL5 0x92, 16bit register */ 609 #define AP_REG5_EN B15_MASK 610 #define AP_REG5_ADDR_MASK 0x1F00 /* 12:8 */ 611 #define AP_PRE_SUP5 B6_MASK 612 #define AP_PHY5_DFLT B5_MASK 613 #define AP_PHY5_ADDR_MASK 0x001F /* 4:0 */ 614 615 /* AP_VALUE 0x98, 32bit ragister */ 616 #define AP_VAL_ACTIVE B31_MASK 617 #define AP_VAL_RD_CMD B29_MASK 618 #define AP_ADDR 0x00070000 /* 18:16 */ 619 #define AP_VAL 0x0000FFFF /* 15:0 */ 620 621 /* PCS_ANEG 0x9C, 32bit register */ 622 #define SYNC_LOST B10_MASK 623 #define IMATCH B9_MASK 624 #define CMATCH B8_MASK 625 #define PCS_AN_IDLE B1_MASK 626 #define PCS_AN_CFG B0_MASK 627 628 /* DLY_INT_A 0xA8, 32bit register */ 629 #define DLY_INT_A_R3 B31_MASK 630 #define DLY_INT_A_R2 B30_MASK 631 #define DLY_INT_A_R1 B29_MASK 632 #define DLY_INT_A_R0 B28_MASK 633 #define DLY_INT_A_T3 B27_MASK 634 #define DLY_INT_A_T2 B26_MASK 635 #define DLY_INT_A_T1 B25_MASK 636 #define DLY_INT_A_T0 B24_MASK 637 #define EVENT_COUNT_A 0x00FF0000 /* 20:16 */ 638 #define MAX_DELAY_TIME_A 0x000007FF /* 10:0 */ 639 640 /* DLY_INT_B 0xAC, 32bit register */ 641 #define DLY_INT_B_R3 B31_MASK 642 #define DLY_INT_B_R2 B30_MASK 643 #define DLY_INT_B_R1 B29_MASK 644 #define DLY_INT_B_R0 B28_MASK 645 #define DLY_INT_B_T3 B27_MASK 646 #define DLY_INT_B_T2 B26_MASK 647 #define DLY_INT_B_T1 B25_MASK 648 #define DLY_INT_B_T0 B24_MASK 649 #define EVENT_COUNT_B 0x00FF0000 /* 20:16 */ 650 #define MAX_DELAY_TIME_B 0x000007FF /* 10:0 */ 651 652 /* DFC_THRESH2 0xC0, 16bit register */ 653 #define DFC_THRESH2_HIGH 0xFF00 /* 15:8 */ 654 #define DFC_THRESH2_LOW 0x00FF /* 7:0 */ 655 656 /* DFC_THRESH3 0xC2, 16bit register */ 657 #define DFC_THRESH3_HIGH 0xFF00 /* 15:8 */ 658 #define DFC_THRESH3_LOW 0x00FF /* 7:0 */ 659 660 /* DFC_THRESH0 0xC4, 16bit register */ 661 #define DFC_THRESH0_HIGH 0xFF00 /* 15:8 */ 662 #define DFC_THRESH0_LOW 0x00FF /* 7:0 */ 663 664 /* DFC_THRESH1 0xC6, 16bit register */ 665 #define DFC_THRESH1_HIGH 0xFF00 /* 15:8 */ 666 #define DFC_THRESH1_LOW 0x00FF /* 7:0 */ 667 668 /* FLOW_CONTROL 0xC8, 32bit register */ 669 #define PAUSE_LEN_CHG B30_MASK 670 #define FFC_EN B28_MASK 671 #define DFC_RING3_EN B27_MASK 672 #define DFC_RING2_EN B26_MASK 673 #define DFC_RING1_EN B25_MASK 674 #define DFC_RING0_EN B24_MASK 675 #define FIXP_CONGEST B21_MASK 676 #define NAPA B20_MASK 677 #define NPA B19_MASK 678 #define FIXP B18_MASK 679 #define FCPEN B17_MASK 680 #define FCCMD B16_MASK 681 #define PAUSE_LEN 0x0000FFFF /* 15:0 */ 682 683 /* FFC THRESH 0xCC, 32bit register */ 684 #define FFC_HIGH 0xFFFF0000 /* 31:16 */ 685 #define FFC_LOW 0x0000FFFF /* 15:0 */ 686 687 /* PHY_ACCESS 0xD0, 32bit register */ 688 #define PHY_CMD_ACTIVE B31_MASK 689 #define PHY_WR_CMD B30_MASK 690 #define PHY_RD_CMD B29_MASK 691 #define PHY_RD_ERR B28_MASK 692 #define PHY_PRE_SUP B27_MASK 693 #define PHY_ADDR 0x03E00000 /* 25:21 */ 694 #define PHY_REG_ADDR 0x001F0000 /* 20:16 */ 695 #define PHY_DATA 0x0000FFFF /* 15:0 */ 696 #define PHY_ADDR_SHIFT 21 697 #define PHY_REG_ADDR_SHIFT 16 698 699 #define PHY_MAX_RETRY 30 700 701 702 /* EEPROM_ACC 0x17C, 16bit register */ 703 #define PVALID B15_MASK 704 #define PREAD B14_MASK 705 #define EEDET B13_MASK 706 #define EEN B4_MASK 707 #define ECS B2_MASK 708 #define EESK B1_MASK 709 #define EDI_EDO B0_MASK 710 711 /* PMAT0 0x190, 32bit register */ 712 #define PMR_ACTIVE B31_MASK 713 #define PMR_WR_CMD B30_MASK 714 #define PMR_RD_CMD B29_MASK 715 #define PMR_BANK B28_MASK 716 #define PMR_ADDR 0x007F0000 /* 22:16 */ 717 #define PMR_B4 0x000000FF /* 15:0 */ 718 719 /* PMAT1 0x194, 32bit register */ 720 #define PMR_B3 0xFF000000 /* 31:24 */ 721 #define PMR_B2 0x00FF0000 /* 23:16 */ 722 #define PMR_B1 0x0000FF00 /* 15:8 */ 723 #define PMR_B0 0x000000FF /* 7:0 */ 724 725 /* CAMDATA 0x198, 16bit register */ 726 #define CAM_DATA_MASK 0x000000FFFFFFFFFFFF 727 728 /* CAM_ADDR 0x1A0, 16bit register */ 729 #define CAM_CMD_ACTIVE B15_MASK 730 #define CAM_WR_CMD B14_MASK 731 #define CAM_RD_CMD B13_MASK 732 #define CAM_CLEAR B12_MASK 733 #define CAM_ADDRESS 0x001F 734 735 /* INT0 0x38, 32bit register */ 736 #define INTR B31_MASK 737 #define LCINT B27_MASK 738 #define TINT0 B8_MASK 739 #define STINT B4_MASK 740 #define RINT0 B0_MASK 741 742 /* TEST0 0x1A8, 32bit register */ 743 744 /* VAL1 */ 745 #define MFSM_RESET B10_MASK 746 #define BFD_SCALE_DOWN B9_MASK 747 748 /* VAL0 */ 749 #define LEDCNTTST B5_MASK 750 #define RTYTST_RANGEN B2_MASK 751 #define RTYTST_SLOT B1_MASK 752 #define SERRLEVEL B0_MASK 753 754 #define CABLE_CHK_TIME 100 755 756 #define PCI_IOMAP_BASE_REG 0x00 757 #define PCI_MEM_BASE_REG 0x10 758 759 #define XPHYFD B5_MASK 760 #define XPHYSP B3_MASK /* 4:3 */ 761 762 #define TX_RATE 0x1 763 #define RX_RATE 0x2 764 #define RX_BYTES 0xb 765 #define TX_BYTES 0xc 766 767 #define LOW_COALESC 1 768 #define MEDIUM_COALESC 2 769 #define HIGH_COALESC 3 770 #define NO_COALESC 4 771 772 #define CLIENT 0x1 773 #define SERVER 0x2 774 #define DISABLE 0x3 775 #define PCI_OPT 0x4 776 777 #define MULTICAST_BITMAP_ARRAY_SIZE 64 778 779 #define PHY_AUTO_NEGOTIATION 0 780 #define PHY_FORCE_HD_100 1 /* HD: Half Duplex */ 781 #define PHY_FORCE_FD_100 2 /* FD: Full Duplex */ 782 #define PHY_FORCE_HD_10 3 783 #define PHY_FORCE_FD_10 4 784 785 struct tx_desc { 786 unsigned int Tx_BCNT :16; /* Buffer Byte Count */ 787 unsigned int Tx_RES4 :6; /* RESVERD 6 bits */ 788 /* 789 * This bit causes the transmission of the corresponding frame to be 790 * aborted. If the transmitter has not started sending the frame at the 791 * time that the descriptor 792 */ 793 unsigned int KILL :1; 794 unsigned int Tx_RES3 :1; /* RESVERD 1 bits */ 795 /* End Of packet to indicates the last Buffer */ 796 unsigned int Tx_EOP :1; 797 unsigned int Tx_SOP :1; /* Defer to Transmit */ 798 unsigned int Tx_RES2 :2; 799 unsigned int Tx_LTINT :1; /* Start of packet for the Buffer */ 800 /* 801 * ADD_FCS dynamically controls the generation of FCS on a frame by 802 * frame basis. 803 */ 804 unsigned int Tx_ADD_FCS :1; 805 unsigned int Tx_RES1 :1; /* Reserved Location */ 806 unsigned int Tx_OWN :1; /* Own Bit for the Transmit */ 807 unsigned int TCI :16; /* VLAN Tag Control Command. */ 808 unsigned int TCC :2; /* Tag Control Information. */ 809 unsigned int Tx_RES0 :14; /* Resvered Location */ 810 /* 811 * TBADR[31:0] Transmit Buffer Address. This field contains the address 812 * of the Transmit buffer that is associated with this descriptor 813 */ 814 unsigned int Tx_Base_Addr :32; 815 unsigned int Tx_USPACE :32; /* User Space */ 816 }; 817 818 /* Receive Descriptor For the L7 */ 819 struct rx_desc { 820 821 /* User Reserved amar - Its just reservered. */ 822 unsigned int Rx_USPACE :32; 823 /* 824 * Message Byte Count is the number of bytes of the received message 825 * written 826 */ 827 unsigned int Rx_MCNT :16; 828 unsigned int TCI :16; 829 /* 830 * Buffer Byte Count is the length of the buffer pointed to by this 831 * descriptor 832 */ 833 unsigned int Rx_BCNT :16; 834 unsigned int Rx_RES1 :2; /* Reserved Location */ 835 /* 836 * VLAN Tag Type. Indicates what type of VLAN tag, if any, is included 837 * in the received 838 */ 839 unsigned int TT :2; 840 /* 841 * Broadcast Address Match is set by the Am79C976 controller when it 842 * accepts the reveice buffer 843 */ 844 unsigned int Rx_BAM :1; 845 /* 846 * Logical Address Filter Match is set by the Am79C976 controller 847 * to the Receive Buffer 848 */ 849 unsigned int Rx_LAFM :1; 850 /* Physical Address Match is set by the Am79C976 controller */ 851 unsigned int Rx_PAM :1; 852 unsigned int Rx_RES0 :1; /* Resvered Location */ 853 /* End Of packet to indicates the last Buffer */ 854 unsigned int Rx_EOP :1; 855 unsigned int Rx_SOP :1; /* Start of packet for the Buffer */ 856 unsigned int Rx_BUFF :1; /* Reserved location */ 857 /* 858 * CRC indicates that the receiver has detected a CRC (FCS) error on the 859 * incoming frame. 860 */ 861 unsigned int Rx_CRC :1; 862 /* 863 * Overflow error indicates that the receiver has lost all or part of 864 * the incoming frame. 865 */ 866 unsigned int Rx_OFLO :1; 867 unsigned int Rx_FRAM :1; /* Framing Error */ 868 unsigned int Rx_ERR :1; /* Error is Set By the Controller */ 869 unsigned int Rx_OWN :1; /* Own Bit of Descriptor */ 870 /* 871 * RBADR[31:0] Receive Buffer Address. This field contains the address 872 * of the receive buffer that is associated with this descriptor. 873 */ 874 unsigned int Rx_Base_Addr:32; 875 }; 876 877 878 /* Initialization Block (SSIZE32 = 1) */ 879 struct init_block { 880 unsigned int MODE :16; /* Mode */ 881 unsigned int RES1 :4; /* Reserved Location */ 882 /* Receive software structure is defined for 16 bit */ 883 unsigned int RLEN :4; 884 unsigned int RES2 :4; /* Reserved bits */ 885 /* Transmit software structure is defined for the 16 bit */ 886 unsigned int TLEN :4; 887 unsigned int PADDR0 :8; 888 unsigned int PADDR1 :8; 889 unsigned int PADDR2 :8; 890 unsigned int PADDR3 :8; 891 unsigned int PADDR4 :8; 892 unsigned int PADDR5 :8; 893 unsigned int RES3 :16; 894 unsigned char LADRF[8]; 895 /* RDRA indicate where the receive descriptor ring begins */ 896 unsigned int RDRA :32; 897 /* TDRA indicate where the transmit descriptor ring begins */ 898 unsigned int TDRA :32; 899 }; 900 901 /* MDL Physical and Normal Structure */ 902 struct mdl { 903 ULONG Io_Address; 904 ULONG Mem_Address; 905 906 volatile int CSR; 907 volatile int CardStatus; 908 909 /* PMR (Pattern Match RAM) */ 910 /* 911 * An array to store the indexes of each of the patterns in 912 * Pattern List. 913 */ 914 unsigned int *PMR_PtrList; 915 /* An array of pattern controls and pattern data bytes */ 916 unsigned char *PatternList; 917 unsigned int *PatternLength; 918 int EnableMulticast; 919 /* The begining of the free area in the PatternList array */ 920 unsigned short PatternList_FreeIndex; 921 /* The total number of patterns present in the PMR */ 922 unsigned short TotalPatterns; 923 unsigned short PatternEnableBit; 924 925 unsigned char Mac[6]; 926 unsigned char TEMP_MAC[6]; 927 unsigned int FLAGS; 928 unsigned char TempLADRF[8]; 929 930 ULONG Speed; 931 ULONG FullDuplex; 932 933 struct init_block *init_blk; 934 935 int tmpPtrArray[8]; 936 937 int MulticastBitMapArray[MULTICAST_BITMAP_ARRAY_SIZE]; 938 int External_Phy; 939 unsigned int phy_id; 940 941 /* For interrupt delay */ 942 /* Unit is 10 us. Its value must < 0x800 (2^11) */ 943 unsigned int rx_intrcoalesc_time; 944 /* Its value must < 32 (2^5) */ 945 unsigned int rx_intrcoalesc_events; 946 unsigned int tx_intrcoalesc_time; 947 unsigned int tx_intrcoalesc_events; 948 int IntrCoalescFlag; 949 950 int RxRingLenBits; 951 int TxRingLenBits; 952 int TxRingSize; 953 int RxRingSize; 954 955 int IpgValue; 956 }; 957 958 struct Rx_Buf_Desc { 959 struct rx_desc *descriptor; 960 long *USpaceMap; 961 }; 962 963 struct nonphysical 964 { 965 /* Tx descriptors queue */ 966 struct tx_desc *TxDescQRead; /* The next ring entry to be freed */ 967 struct tx_desc *TxDescQWrite; /* The next free ring entry */ 968 struct tx_desc *TxDescQStart; /* The start of the ring entries */ 969 struct tx_desc *TxDescQEnd; /* The end of the ring entries */ 970 971 /* struct Rx_Buf_Desc * queue */ 972 struct Rx_Buf_Desc *RxBufDescQRead; 973 struct Rx_Buf_Desc *RxBufDescQStart; 974 struct Rx_Buf_Desc *RxBufDescQEnd; 975 976 }; 977 978 struct mil 979 { 980 /* 981 * 1) For memory allocation and free 982 */ 983 984 /* 985 * Tx_desc: address of all tx descriptors block 986 * Tx_desc_pa: physical address of Tx_desc 987 */ 988 struct tx_desc *Tx_desc; 989 unsigned int Tx_desc_pa; 990 /* Original address, because Tx_desc needs 16 bytes alignment */ 991 ULONG Tx_desc_original; 992 993 struct rx_desc *Rx_desc; 994 unsigned int Rx_desc_pa; 995 /* Original address, because Rx_desc needs 16 bytes alignment */ 996 ULONG Rx_desc_original; 997 998 long *USpaceMapArray; /* Queue of struct rxBufInfo * */ 999 1000 /* 1001 * 2) For descriptor queue/buffer queue operation 1002 */ 1003 struct nonphysical *pNonphysical; 1004 1005 /* 1006 * 3) Parameters 1007 */ 1008 int RxRingSize; 1009 int TxRingSize; 1010 int RxBufSize; 1011 1012 /* 1013 * 4) Other 1014 */ 1015 int tx_reschedule; 1016 char *name; 1017 }; 1018 1019 struct LayerPointers 1020 { 1021 struct odl *pOdl; 1022 struct mil *pMil; 1023 struct mdl *pMdl; 1024 1025 int instance; 1026 int attach_progress; 1027 int run; /* B_TRUE on plumb; B_FALSE on unplumb */ 1028 }; 1029 1030 /* MIL Function Prototypes. */ 1031 1032 /* 1033 * Initialisation of MIL data structures and External Interface Function 1034 * Pointers. 1035 */ 1036 void milInitGlbds(struct LayerPointers *); 1037 1038 void milInitRxQ(struct LayerPointers *); 1039 1040 void milResetTxQ(struct LayerPointers *); 1041 1042 void milFreeResources(struct LayerPointers *, ULONG *); 1043 1044 void milRequestResources(ULONG *); 1045 void milSetResources(struct LayerPointers *, ULONG *); 1046 1047 /* Open Functions. */ 1048 void mdlOpen(struct LayerPointers *); 1049 1050 void mdlHWReset(struct LayerPointers *); 1051 1052 /* Multicast */ 1053 void mdlDeleteMulticastAddress(struct LayerPointers *, UCHAR *); 1054 void mdlAddMulticastAddress(struct LayerPointers *, UCHAR *); 1055 1056 /* Transmit/Receive Interface provided by MDL */ 1057 void mdlTransmit(struct LayerPointers *); 1058 void mdlReceive(struct LayerPointers *); 1059 1060 unsigned int mdlReadMib(struct LayerPointers *, char); 1061 1062 /* Read Link Status */ 1063 int mdlReadLink(struct LayerPointers *); 1064 1065 /* Interrupt Handling */ 1066 unsigned int mdlReadInterrupt(struct LayerPointers *); 1067 1068 void mdlEnableInterrupt(struct LayerPointers *); 1069 void mdlDisableInterrupt(struct LayerPointers *); 1070 1071 void mdlGetActiveMediaInfo(struct LayerPointers *); 1072 1073 void mdlStartChip(struct LayerPointers *); 1074 void mdlStopChip(struct LayerPointers *); 1075 1076 void mdlGetMacAddress(struct LayerPointers *, unsigned char *); 1077 void mdlSetMacAddress(struct LayerPointers *, unsigned char *); 1078 1079 void mdlAddMulticastAddresses(struct LayerPointers *, int, unsigned char *); 1080 1081 void mdlSetPromiscuous(struct LayerPointers *); 1082 void mdlDisablePromiscuous(struct LayerPointers *); 1083 1084 void mdlSendPause(struct LayerPointers *); 1085 1086 void SetIntrCoalesc(struct LayerPointers *, boolean_t); 1087 void mdlPHYAutoNegotiation(struct LayerPointers *, unsigned int); 1088 void mdlRxFastSuspend(struct LayerPointers *); 1089 void mdlRxFastSuspendClear(struct LayerPointers *); 1090 1091 /* Externs */ 1092 1093 /* ODL functions */ 1094 extern void amd8111s_reset(struct LayerPointers *); 1095 extern unsigned char READ_REG8(struct LayerPointers *, long); 1096 extern void WRITE_REG8(struct LayerPointers *, long, int); 1097 extern int READ_REG16(struct LayerPointers *, long); 1098 extern void WRITE_REG16(struct LayerPointers *, long, int); 1099 extern long READ_REG32(struct LayerPointers *, long); 1100 extern void WRITE_REG32(struct LayerPointers *, long, int); 1101 extern void WRITE_REG64(struct LayerPointers *, long, char *); 1102 1103 #endif /* AMD8111S_HW_H */ 1104