1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 #include <sys/systm.h> 29 #include <sys/conf.h> 30 #include <sys/modctl.h> 31 #include <sys/file.h> 32 #include <sys/stat.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/modctl.h> 36 #include <sys/sunldi.h> 37 #include <sys/pci.h> 38 #include <sys/agpgart.h> 39 #include <sys/agp/agpdefs.h> 40 #include <sys/agp/agptarget_io.h> 41 42 int agptarget_debug_var = 0; 43 #define TARGETDB_PRINT2(fmt) if (agptarget_debug_var >= 1) cmn_err fmt 44 #define INST2NODENUM(inst) (inst) 45 #define DEV2INST(dev) (getminor(dev)) 46 47 typedef struct agp_target_softstate { 48 dev_info_t *tsoft_dip; 49 ddi_acc_handle_t tsoft_pcihdl; 50 uint32_t tsoft_devid; 51 /* The offset of the ACAPID register */ 52 off_t tsoft_acaptr; 53 kmutex_t tsoft_lock; 54 int tsoft_gms_off; /* GMS offset in config */ 55 uint32_t tsoft_gms; 56 }agp_target_softstate_t; 57 58 /* 59 * To get the pre-allocated graphics mem size using Graphics Mode Select 60 * (GMS) value. 61 */ 62 typedef struct gms_mode { 63 uint32_t gm_devid; /* bridge vendor + device id */ 64 off_t gm_regoff; /* mode selection register offset */ 65 uint32_t gm_mask; /* GMS mask */ 66 uint32_t gm_num; /* number of modes in gm_vec */ 67 int *gm_vec; /* modes array */ 68 } gms_mode_t; 69 70 static void *agptarget_glob_soft_handle; 71 72 #define GETSOFTC(instance) ((agp_target_softstate_t *) \ 73 ddi_get_soft_state(agptarget_glob_soft_handle, instance)); 74 75 /* 76 * The AMD8151 bridge is the only supported 64 bit hardware 77 */ 78 static int 79 is_64bit_aper(agp_target_softstate_t *softstate) 80 { 81 return (softstate->tsoft_devid == AMD_BR_8151); 82 } 83 84 /* 85 * Check if it is an intel bridge 86 */ 87 static int 88 is_intel_br(agp_target_softstate_t *softstate) 89 { 90 return ((softstate->tsoft_devid & VENDOR_ID_MASK) == 91 INTEL_VENDOR_ID); 92 } 93 94 /* 95 * agp_target_cap_find() 96 * 97 * Description: 98 * This function searches the linked capability list to find the offset 99 * of the AGP capability register. When it was not found, return 0. 100 * This works for standard AGP chipsets, but not for some Intel chipsets, 101 * like the I830M/I830MP/I852PM/I852GME/I855GME. It will return 0 for 102 * these chipsets even if AGP is supported. So the offset of acapid 103 * should be set manually in thoses cases. 104 * 105 * Arguments: 106 * pci_handle ddi acc handle of pci config 107 * 108 * Returns: 109 * 0 No capability pointer register found 110 * nexcap The AGP capability pointer register offset 111 */ 112 static off_t 113 agp_target_cap_find(ddi_acc_handle_t pci_handle) 114 { 115 off_t nextcap = 0; 116 uint32_t ncapid = 0; 117 uint8_t value = 0; 118 119 /* Check if this device supports the capability pointer */ 120 value = (uint8_t)(pci_config_get16(pci_handle, PCI_CONF_STAT) 121 & PCI_CONF_CAP_MASK); 122 123 if (!value) 124 return (0); 125 /* Get the offset of the first capability pointer from CAPPTR */ 126 nextcap = (off_t)(pci_config_get8(pci_handle, AGP_CONF_CAPPTR)); 127 128 /* Check the AGP capability from the first capability pointer */ 129 while (nextcap) { 130 ncapid = pci_config_get32(pci_handle, nextcap); 131 /* 132 * AGP3.0 rev1.0 127 the capid was assigned by the PCI SIG, 133 * 845 data sheet page 69 134 */ 135 if ((ncapid & PCI_CONF_CAPID_MASK) == 136 AGP_CAP_ID) /* The AGP cap was found */ 137 break; 138 139 nextcap = (off_t)((ncapid & PCI_CONF_NCAPID_MASK) >> 8); 140 } 141 142 return (nextcap); 143 144 } 145 146 /* 147 * agp_target_get_aperbase() 148 * 149 * Description: 150 * This function gets the AGP aperture base address from the AGP target 151 * register, the AGP aperture base register was programmed by the BIOS. 152 * 153 * Arguments: 154 * softstate driver soft state pointer 155 * 156 * Returns: 157 * aper_base AGP aperture base address 158 * 159 * Notes: 160 * If a 64bit bridge device is available, the AGP aperture base address 161 * can be 64 bit. 162 */ 163 static uint64_t 164 agp_target_get_apbase(agp_target_softstate_t *softstate) 165 { 166 uint64_t aper_base; 167 168 if (is_intel_br(softstate)) { 169 aper_base = pci_config_get32(softstate->tsoft_pcihdl, 170 AGP_CONF_APERBASE) & AGP_32_APERBASE_MASK; 171 } else if (is_64bit_aper(softstate)) { 172 aper_base = pci_config_get64(softstate->tsoft_pcihdl, 173 AGP_CONF_APERBASE); 174 /* 32-bit or 64-bit aperbase base pointer */ 175 if ((aper_base & AGP_APER_TYPE_MASK) == 0) 176 aper_base &= AGP_32_APERBASE_MASK; 177 else 178 aper_base &= AGP_64_APERBASE_MASK; 179 } 180 181 return (aper_base); 182 } 183 184 /* 185 * agp_target_get_apsize() 186 * 187 * Description: 188 * This function gets the AGP aperture size by reading the AGP aperture 189 * size register. 190 * Arguments: 191 * softstate driver soft state pointer 192 * 193 * Return: 194 * size The AGP aperture size in megabytes 195 * 0 an unexpected error 196 */ 197 static size_t 198 agp_target_get_apsize(agp_target_softstate_t *softstate) 199 { 200 off_t cap; 201 uint16_t value; 202 size_t size, regsize; 203 204 ASSERT(softstate->tsoft_acaptr); 205 cap = softstate->tsoft_acaptr; 206 207 if (is_intel_br(softstate)) { 208 /* extend this value to 16 bit for later tests */ 209 value = (uint16_t)pci_config_get8(softstate->tsoft_pcihdl, 210 cap + AGP_CONF_APERSIZE) | AGP_APER_SIZE_MASK; 211 } else if (is_64bit_aper(softstate)) { 212 value = pci_config_get16(softstate->tsoft_pcihdl, 213 cap + AGP_CONF_APERSIZE); 214 } 215 216 if (value & AGP_APER_128M_MASK) { 217 switch (value & AGP_APER_128M_MASK) { 218 case AGP_APER_4M: 219 size = 4; /* 4M */ 220 break; 221 case AGP_APER_8M: 222 size = 8; /* 8M */ 223 break; 224 case AGP_APER_16M: 225 size = 16; /* 16M */ 226 break; 227 case AGP_APER_32M: 228 size = 32; /* 32M */ 229 break; 230 case AGP_APER_64M: 231 size = 64; /* 64M */ 232 break; 233 case AGP_APER_128M: 234 size = 128; /* 128M */ 235 break; 236 default: 237 size = 0; /* not true */ 238 } 239 } else { 240 switch (value & AGP_APER_4G_MASK) { 241 case AGP_APER_256M: 242 size = 256; /* 256 M */ 243 break; 244 case AGP_APER_512M: 245 size = 512; /* 512 M */ 246 break; 247 case AGP_APER_1024M: 248 size = 1024; /* 1024 M */ 249 break; 250 case AGP_APER_2048M: 251 size = 2048; /* 2048 M */ 252 break; 253 case AGP_APER_4G: 254 size = 4096; /* 4096 M */ 255 break; 256 default: 257 size = 0; /* not true */ 258 } 259 } 260 /* 261 * In some cases, there is no APSIZE register, so the size value 262 * of 256M could be wrong. Check the value by reading the size of 263 * the first register which was set in the PCI configuration space. 264 */ 265 if (size == 256) { 266 if (ddi_dev_regsize(softstate->tsoft_dip, 267 AGP_TARGET_BAR1, (off_t *)®size) == DDI_FAILURE) 268 return (0); 269 270 if (MB2BYTES(size) != regsize) { 271 TARGETDB_PRINT2((CE_WARN, 272 "APSIZE 256M doesn't match regsize %lx", 273 regsize)); 274 TARGETDB_PRINT2((CE_WARN, "Use regsize instead")); 275 size = BYTES2MB(regsize); 276 } 277 } 278 279 return (size); 280 } 281 282 static void 283 agp_target_set_gartaddr(agp_target_softstate_t *softstate, uint32_t gartaddr) 284 { 285 ASSERT(softstate->tsoft_acaptr); 286 287 /* Disable the GTLB for Intel chipsets */ 288 pci_config_put16(softstate->tsoft_pcihdl, 289 softstate->tsoft_acaptr + AGP_CONF_CONTROL, 0x0000); 290 291 pci_config_put32(softstate->tsoft_pcihdl, 292 softstate->tsoft_acaptr + AGP_CONF_ATTBASE, 293 gartaddr & AGP_ATTBASE_MASK); 294 } 295 296 /* 297 * Pre-allocated graphics memory for every type of Intel north bridge, mem size 298 * are specified in kbytes. 299 */ 300 #define GMS_MB(n) ((n) * 1024) 301 #define GMS_SHIFT 4 302 #define GMS_SIZE(a) (sizeof (a) / sizeof (int)) 303 304 /* 305 * Since value zero always means "No memory pre-allocated", value of (GMS - 1) 306 * is used to index these arrays, i.e. gms_xxx[1] contains the mem size (in kb) 307 * that GMS value 0x1 corresponding to. 308 * 309 * Assuming all "reserved" GMS value as zero bytes of pre-allocated graphics 310 * memory, unless some special BIOS settings exist. 311 */ 312 static int gms_810[12] = {0, 0, 0, 0, 0, 0, 0, 512, 0, 0, 0, GMS_MB(1)}; 313 static int gms_830_845[4] = {0, 512, GMS_MB(1), GMS_MB(8)}; 314 static int gms_855GM[5] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), 315 GMS_MB(32)}; 316 /* There is no modes for 16M in datasheet, but some BIOS add it. */ 317 static int gms_865_915GM[4] = {GMS_MB(1), 0, GMS_MB(8), GMS_MB(16)}; 318 static int gms_915_945_965[3] = {GMS_MB(1), 0, GMS_MB(8)}; 319 static int gms_965GM[7] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), 320 GMS_MB(32), GMS_MB(48), GMS_MB(64)}; 321 static int gms_X33[9] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), 322 GMS_MB(32), GMS_MB(48), GMS_MB(64), GMS_MB(128), GMS_MB(256)}; 323 static int gms_G4X[13] = {0, 0, 0, 0, 324 GMS_MB(32), GMS_MB(48), GMS_MB(64), GMS_MB(128), GMS_MB(256), 325 GMS_MB(96), GMS_MB(160), GMS_MB(224), GMS_MB(352)}; 326 327 static gms_mode_t gms_modes[] = { 328 {INTEL_BR_810, I810_CONF_SMRAM, I810_GMS_MASK, 329 GMS_SIZE(gms_810), gms_810}, 330 {INTEL_BR_810DC, I810_CONF_SMRAM, I810_GMS_MASK, 331 GMS_SIZE(gms_810), gms_810}, 332 {INTEL_BR_810E, I810_CONF_SMRAM, I810_GMS_MASK, 333 GMS_SIZE(gms_810), gms_810}, 334 {INTEL_BR_830M, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 335 GMS_SIZE(gms_830_845), gms_830_845}, 336 {INTEL_BR_845, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 337 GMS_SIZE(gms_830_845), gms_830_845}, 338 {INTEL_BR_855GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 339 GMS_SIZE(gms_855GM), gms_855GM}, 340 {INTEL_BR_865, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 341 GMS_SIZE(gms_865_915GM), gms_865_915GM}, 342 {INTEL_BR_915GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 343 GMS_SIZE(gms_865_915GM), gms_865_915GM}, 344 {INTEL_BR_915, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 345 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 346 {INTEL_BR_945, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 347 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 348 {INTEL_BR_945GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 349 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 350 {INTEL_BR_946GZ, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 351 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 352 {INTEL_BR_965G1, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 353 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 354 {INTEL_BR_965G2, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 355 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 356 {INTEL_BR_965Q, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 357 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 358 {INTEL_BR_965GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 359 GMS_SIZE(gms_965GM), gms_965GM}, 360 {INTEL_BR_965GME, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 361 GMS_SIZE(gms_965GM), gms_965GM}, 362 {INTEL_BR_Q35, I8XX_CONF_GC, IX33_GC_MODE_MASK, 363 GMS_SIZE(gms_X33), gms_X33}, 364 {INTEL_BR_G33, I8XX_CONF_GC, IX33_GC_MODE_MASK, 365 GMS_SIZE(gms_X33), gms_X33}, 366 {INTEL_BR_Q33, I8XX_CONF_GC, IX33_GC_MODE_MASK, 367 GMS_SIZE(gms_X33), gms_X33}, 368 {INTEL_BR_GM45, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 369 GMS_SIZE(gms_965GM), gms_965GM}, 370 {INTEL_BR_EL, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 371 GMS_SIZE(gms_G4X), gms_G4X}, 372 {INTEL_BR_Q45, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 373 GMS_SIZE(gms_G4X), gms_G4X}, 374 {INTEL_BR_G45, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 375 GMS_SIZE(gms_G4X), gms_G4X} 376 }; 377 static int 378 get_chip_gms(uint32_t devid) 379 { 380 int num_modes; 381 int i; 382 383 num_modes = (sizeof (gms_modes) / sizeof (gms_mode_t)); 384 385 for (i = 0; i < num_modes; i++) { 386 if (gms_modes[i].gm_devid == devid) 387 break; 388 } 389 390 return ((i == num_modes) ? -1 : i); 391 } 392 393 /* Returns the size (kbytes) of pre-allocated graphics memory */ 394 static size_t 395 i8xx_biosmem_detect(agp_target_softstate_t *softstate) 396 { 397 uint8_t memval; 398 size_t kbytes; 399 int gms_off; 400 401 kbytes = 0; 402 gms_off = softstate->tsoft_gms_off; 403 404 /* fetch the GMS value from DRAM controller */ 405 memval = pci_config_get8(softstate->tsoft_pcihdl, 406 gms_modes[gms_off].gm_regoff); 407 TARGETDB_PRINT2((CE_NOTE, "i8xx_biosmem_detect: memval = %x", memval)); 408 memval = (memval & gms_modes[gms_off].gm_mask) >> GMS_SHIFT; 409 /* assuming zero byte for 0 or "reserved" GMS values */ 410 if (memval == 0 || memval > gms_modes[gms_off].gm_num) { 411 TARGETDB_PRINT2((CE_WARN, "i8xx_biosmem_detect: " 412 "devid = %x, GMS = %x. assuming zero byte of " 413 "pre-allocated memory", 414 gms_modes[gms_off].gm_devid, memval)); 415 goto done; 416 } 417 memval--; /* use (GMS_value - 1) as index */ 418 kbytes = (gms_modes[gms_off].gm_vec)[memval]; 419 420 done: 421 TARGETDB_PRINT2((CE_NOTE, 422 "i8xx_biosmem_detect: %ldKB BIOS pre-allocated memory detected", 423 kbytes)); 424 return (kbytes); 425 } 426 427 /*ARGSUSED*/ 428 static int agptarget_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, 429 void *arg, void **resultp) 430 { 431 agp_target_softstate_t *st; 432 int instance, rval = DDI_FAILURE; 433 dev_t dev; 434 435 switch (cmd) { 436 case DDI_INFO_DEVT2DEVINFO: 437 dev = (dev_t)arg; 438 instance = DEV2INST(dev); 439 st = ddi_get_soft_state(agptarget_glob_soft_handle, instance); 440 if (st != NULL) { 441 mutex_enter(&st->tsoft_lock); 442 *resultp = st->tsoft_dip; 443 mutex_exit(&st->tsoft_lock); 444 rval = DDI_SUCCESS; 445 } else 446 *resultp = NULL; 447 448 break; 449 case DDI_INFO_DEVT2INSTANCE: 450 dev = (dev_t)arg; 451 instance = DEV2INST(dev); 452 *resultp = (void *)(uintptr_t)instance; 453 rval = DDI_SUCCESS; 454 default: 455 break; 456 } 457 458 return (rval); 459 } 460 461 static int 462 intel_br_resume(agp_target_softstate_t *softstate) 463 { 464 int gms_off; 465 466 gms_off = softstate->tsoft_gms_off; 467 468 /* 469 * We recover the gmch graphics control register here 470 */ 471 pci_config_put16(softstate->tsoft_pcihdl, 472 gms_modes[gms_off].gm_regoff, softstate->tsoft_gms); 473 474 return (DDI_SUCCESS); 475 } 476 static int 477 intel_br_suspend(agp_target_softstate_t *softstate) 478 { 479 int gms_off; 480 481 gms_off = softstate->tsoft_gms_off; 482 softstate->tsoft_gms = pci_config_get16(softstate->tsoft_pcihdl, 483 gms_modes[gms_off].gm_regoff); 484 485 return (DDI_SUCCESS); 486 } 487 488 static int 489 agp_target_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 490 { 491 agp_target_softstate_t *softstate; 492 int instance; 493 int status; 494 495 instance = ddi_get_instance(dip); 496 497 switch (cmd) { 498 case DDI_ATTACH: 499 break; 500 case DDI_RESUME: 501 softstate = 502 ddi_get_soft_state(agptarget_glob_soft_handle, instance); 503 return (intel_br_resume(softstate)); 504 default: 505 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 506 "only attach and resume ops are supported")); 507 return (DDI_FAILURE); 508 } 509 510 if (ddi_soft_state_zalloc(agptarget_glob_soft_handle, 511 instance) != DDI_SUCCESS) { 512 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 513 "soft state zalloc failed")); 514 return (DDI_FAILURE); 515 } 516 517 softstate = ddi_get_soft_state(agptarget_glob_soft_handle, instance); 518 mutex_init(&softstate->tsoft_lock, NULL, MUTEX_DRIVER, NULL); 519 softstate->tsoft_dip = dip; 520 status = pci_config_setup(dip, &softstate->tsoft_pcihdl); 521 if (status != DDI_SUCCESS) { 522 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 523 "pci config setup failed")); 524 ddi_soft_state_free(agptarget_glob_soft_handle, 525 instance); 526 return (DDI_FAILURE); 527 } 528 529 softstate->tsoft_devid = pci_config_get32(softstate->tsoft_pcihdl, 530 PCI_CONF_VENID); 531 softstate->tsoft_gms_off = get_chip_gms(softstate->tsoft_devid); 532 if (softstate->tsoft_gms_off < 0) { 533 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 534 "read gms offset failed")); 535 pci_config_teardown(&softstate->tsoft_pcihdl); 536 ddi_soft_state_free(agptarget_glob_soft_handle, 537 instance); 538 return (DDI_FAILURE); 539 } 540 softstate->tsoft_acaptr = agp_target_cap_find(softstate->tsoft_pcihdl); 541 if (softstate->tsoft_acaptr == 0) { 542 /* Make a correction for some Intel chipsets */ 543 if (is_intel_br(softstate)) 544 softstate->tsoft_acaptr = AGP_CAP_OFF_DEF; 545 else { 546 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 547 "Not a supposed corretion")); 548 pci_config_teardown(&softstate->tsoft_pcihdl); 549 ddi_soft_state_free(agptarget_glob_soft_handle, 550 instance); 551 return (DDI_FAILURE); 552 } 553 } 554 555 status = ddi_create_minor_node(dip, AGPTARGET_NAME, S_IFCHR, 556 INST2NODENUM(instance), DDI_NT_AGP_TARGET, 0); 557 558 if (status != DDI_SUCCESS) { 559 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 560 "Create minor node failed")); 561 pci_config_teardown(&softstate->tsoft_pcihdl); 562 ddi_soft_state_free(agptarget_glob_soft_handle, instance); 563 return (DDI_FAILURE); 564 } 565 566 return (DDI_SUCCESS); 567 } 568 569 /*ARGSUSED*/ 570 static int 571 agp_target_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 572 { 573 int instance; 574 agp_target_softstate_t *softstate; 575 576 instance = ddi_get_instance(dip); 577 softstate = ddi_get_soft_state(agptarget_glob_soft_handle, instance); 578 579 if (cmd == DDI_SUSPEND) { 580 /* get GMS modes list entry */ 581 return (intel_br_suspend(softstate)); 582 } 583 584 if (cmd != DDI_DETACH) { 585 TARGETDB_PRINT2((CE_WARN, "agp_target_detach:" 586 "only detach and suspend ops are supported")); 587 return (DDI_FAILURE); 588 } 589 590 ddi_remove_minor_node(dip, AGPTARGET_NAME); 591 pci_config_teardown(&softstate->tsoft_pcihdl); 592 mutex_destroy(&softstate->tsoft_lock); 593 ddi_soft_state_free(agptarget_glob_soft_handle, instance); 594 return (DDI_SUCCESS); 595 } 596 597 /*ARGSUSED*/ 598 static int 599 agp_target_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 600 cred_t *cred, int *rval) 601 { 602 int instance = DEV2INST(dev); 603 agp_target_softstate_t *st; 604 static char kernel_only[] = 605 "amd64_gart_ioctl: is a kernel only ioctl"; 606 607 if (!(mode & FKIOCTL)) { 608 TARGETDB_PRINT2((CE_CONT, kernel_only)); 609 return (ENXIO); 610 } 611 st = GETSOFTC(instance); 612 613 if (st == NULL) 614 return (ENXIO); 615 616 mutex_enter(&st->tsoft_lock); 617 618 switch (cmd) { 619 case CHIP_DETECT: 620 { 621 int type = 0; 622 623 if (is_intel_br(st)) 624 type = CHIP_IS_INTEL; 625 else if (is_64bit_aper(st)) 626 type = CHIP_IS_AMD; 627 else { 628 type = 0; 629 TARGETDB_PRINT2((CE_WARN, "Unknown bridge!")); 630 } 631 632 if (ddi_copyout(&type, (void *)data, sizeof (int), mode)) { 633 mutex_exit(&st->tsoft_lock); 634 return (EFAULT); 635 } 636 637 break; 638 } 639 case I8XX_GET_PREALLOC_SIZE: 640 { 641 size_t prealloc_size; 642 643 if (!is_intel_br(st)) { 644 mutex_exit(&st->tsoft_lock); 645 return (EINVAL); 646 } 647 648 prealloc_size = i8xx_biosmem_detect(st); 649 if (ddi_copyout(&prealloc_size, (void *)data, 650 sizeof (size_t), mode)) { 651 mutex_exit(&st->tsoft_lock); 652 return (EFAULT); 653 } 654 655 break; 656 } 657 case AGP_TARGET_GETINFO: 658 { 659 i_agp_info_t info; 660 uint32_t value; 661 off_t cap; 662 663 ASSERT(st->tsoft_acaptr); 664 665 cap = st->tsoft_acaptr; 666 value = pci_config_get32(st->tsoft_pcihdl, cap); 667 info.iagp_ver.agpv_major = (uint16_t)((value >> 20) & 0xf); 668 info.iagp_ver.agpv_minor = (uint16_t)((value >> 16) & 0xf); 669 info.iagp_devid = st->tsoft_devid; 670 info.iagp_mode = pci_config_get32(st->tsoft_pcihdl, 671 cap + AGP_CONF_STATUS); 672 info.iagp_aperbase = agp_target_get_apbase(st); 673 info.iagp_apersize = agp_target_get_apsize(st); 674 675 if (ddi_copyout(&info, (void *)data, 676 sizeof (i_agp_info_t), mode)) { 677 mutex_exit(&st->tsoft_lock); 678 return (EFAULT); 679 } 680 break; 681 682 } 683 /* 684 * This ioctl is only for Intel AGP chipsets. 685 * It is not necessary for the AMD8151 AGP bridge, because 686 * this register in the AMD8151 does not control any hardware. 687 * It is only provided for compatibility with an Intel AGP bridge. 688 * Please refer to the <<AMD8151 data sheet>> page 24, 689 * AGP device GART pointer. 690 */ 691 case AGP_TARGET_SET_GATTADDR: 692 { 693 uint32_t gartaddr; 694 695 if (ddi_copyin((void *)data, &gartaddr, 696 sizeof (uint32_t), mode)) { 697 mutex_exit(&st->tsoft_lock); 698 return (EFAULT); 699 } 700 701 agp_target_set_gartaddr(st, gartaddr); 702 break; 703 } 704 case AGP_TARGET_SETCMD: 705 { 706 uint32_t command; 707 708 if (ddi_copyin((void *)data, &command, 709 sizeof (uint32_t), mode)) { 710 mutex_exit(&st->tsoft_lock); 711 return (EFAULT); 712 } 713 714 ASSERT(st->tsoft_acaptr); 715 716 pci_config_put32(st->tsoft_pcihdl, 717 st->tsoft_acaptr + AGP_CONF_COMMAND, 718 command); 719 break; 720 721 } 722 case AGP_TARGET_FLUSH_GTLB: 723 { 724 uint16_t value; 725 726 ASSERT(st->tsoft_acaptr); 727 728 value = pci_config_get16(st->tsoft_pcihdl, 729 st->tsoft_acaptr + AGP_CONF_CONTROL); 730 value &= ~AGPCTRL_GTLBEN; 731 pci_config_put16(st->tsoft_pcihdl, 732 st->tsoft_acaptr + AGP_CONF_CONTROL, value); 733 value |= AGPCTRL_GTLBEN; 734 pci_config_put16(st->tsoft_pcihdl, 735 st->tsoft_acaptr + AGP_CONF_CONTROL, value); 736 737 break; 738 } 739 case AGP_TARGET_CONFIGURE: 740 { 741 uint8_t value; 742 743 ASSERT(st->tsoft_acaptr); 744 745 /* 746 * In Intel agp bridges, agp misc register offset 747 * is indexed from 0 instead of capability register. 748 * AMD agp bridges have no such misc register 749 * to control the aperture access, and they have 750 * similar regsiters in CPU gart devices instead. 751 */ 752 753 if (is_intel_br(st)) { 754 value = pci_config_get8(st->tsoft_pcihdl, 755 st->tsoft_acaptr + AGP_CONF_MISC); 756 value |= AGP_MISC_APEN; 757 pci_config_put8(st->tsoft_pcihdl, 758 st->tsoft_acaptr + AGP_CONF_MISC, value); 759 } 760 break; 761 762 } 763 case AGP_TARGET_UNCONFIG: 764 { 765 uint32_t value1; 766 uint8_t value2; 767 768 ASSERT(st->tsoft_acaptr); 769 770 pci_config_put16(st->tsoft_pcihdl, 771 st->tsoft_acaptr + AGP_CONF_CONTROL, 0x0); 772 773 if (is_intel_br(st)) { 774 value2 = pci_config_get8(st->tsoft_pcihdl, 775 st->tsoft_acaptr + AGP_CONF_MISC); 776 value2 &= ~AGP_MISC_APEN; 777 pci_config_put8(st->tsoft_pcihdl, 778 st->tsoft_acaptr + AGP_CONF_MISC, value2); 779 } 780 781 value1 = pci_config_get32(st->tsoft_pcihdl, 782 st->tsoft_acaptr + AGP_CONF_COMMAND); 783 value1 &= ~AGPCMD_AGPEN; 784 pci_config_put32(st->tsoft_pcihdl, 785 st->tsoft_acaptr + AGP_CONF_COMMAND, 786 value1); 787 788 pci_config_put32(st->tsoft_pcihdl, 789 st->tsoft_acaptr + AGP_CONF_ATTBASE, 0x0); 790 791 break; 792 } 793 794 default: 795 mutex_exit(&st->tsoft_lock); 796 return (ENXIO); 797 } /* end switch */ 798 799 mutex_exit(&st->tsoft_lock); 800 801 return (0); 802 } 803 804 /*ARGSUSED*/ 805 static int 806 agp_target_open(dev_t *devp, int flag, int otyp, cred_t *cred) 807 { 808 int instance = DEV2INST(*devp); 809 agp_target_softstate_t *st; 810 811 if (!(flag & FKLYR)) 812 return (ENXIO); 813 814 st = GETSOFTC(instance); 815 816 if (st == NULL) 817 return (ENXIO); 818 819 return (0); 820 } 821 822 /*ARGSUSED*/ 823 static int 824 agp_target_close(dev_t dev, int flag, int otyp, cred_t *cred) 825 { 826 int instance = DEV2INST(dev); 827 agp_target_softstate_t *st; 828 829 st = GETSOFTC(instance); 830 831 if (st == NULL) 832 return (ENXIO); 833 834 return (0); 835 } 836 837 static struct cb_ops agp_target_cb_ops = { 838 agp_target_open, /* cb_open */ 839 agp_target_close, /* cb_close */ 840 nodev, /* cb_strategy */ 841 nodev, /* cb_print */ 842 nodev, /* cb_dump */ 843 nodev, /* cb_read() */ 844 nodev, /* cb_write() */ 845 agp_target_ioctl, /* cb_ioctl */ 846 nodev, /* cb_devmap */ 847 nodev, /* cb_mmap */ 848 nodev, /* cb_segmap */ 849 nochpoll, /* cb_chpoll */ 850 ddi_prop_op, /* cb_prop_op */ 851 0, /* cb_stream */ 852 D_NEW | D_MP, /* cb_flag */ 853 CB_REV, /* cb_ops version? */ 854 nodev, /* cb_aread() */ 855 nodev, /* cb_awrite() */ 856 }; 857 858 /* device operations */ 859 static struct dev_ops agp_target_ops = { 860 DEVO_REV, /* devo_rev */ 861 0, /* devo_refcnt */ 862 agptarget_getinfo, /* devo_getinfo */ 863 nulldev, /* devo_identify */ 864 nulldev, /* devo_probe */ 865 agp_target_attach, /* devo_attach */ 866 agp_target_detach, /* devo_detach */ 867 nodev, /* devo_reset */ 868 &agp_target_cb_ops, /* devo_cb_ops */ 869 0, /* devo_bus_ops */ 870 0, /* devo_power */ 871 ddi_quiesce_not_supported, /* devo_quiesce */ 872 }; 873 874 static struct modldrv modldrv = { 875 &mod_driverops, 876 "AGP target driver", 877 &agp_target_ops, 878 }; 879 880 static struct modlinkage modlinkage = { 881 MODREV_1, /* MODREV_1 is indicated by manual */ 882 {&modldrv, NULL, NULL, NULL} 883 }; 884 885 int 886 _init(void) 887 { 888 int ret; 889 890 ret = ddi_soft_state_init(&agptarget_glob_soft_handle, 891 sizeof (agp_target_softstate_t), 1); 892 893 if (ret) 894 goto err1; 895 896 if ((ret = mod_install(&modlinkage)) != 0) { 897 goto err2; 898 } 899 900 return (DDI_SUCCESS); 901 err2: 902 ddi_soft_state_fini(&agptarget_glob_soft_handle); 903 err1: 904 return (ret); 905 } 906 907 int 908 _info(struct modinfo *modinfop) 909 { 910 return (mod_info(&modlinkage, modinfop)); 911 } 912 913 int 914 _fini(void) 915 { 916 int ret; 917 918 if ((ret = mod_remove(&modlinkage)) == 0) { 919 ddi_soft_state_fini(&agptarget_glob_soft_handle); 920 } 921 return (ret); 922 } 923