1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/conf.h> 28 #include <sys/kmem.h> 29 #include <sys/ddi_impldefs.h> 30 #include <sys/ddi.h> 31 #include <sys/sunddi.h> 32 #include <sys/ddifm.h> 33 #include <sys/fm/io/ddi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/ontrap.h> 36 37 38 /* 39 * DDI DMA Engine functions for x86. 40 * These functions are more naturally generic, but do not apply to SPARC. 41 */ 42 43 int 44 ddi_dmae_alloc(dev_info_t *dip, int chnl, int (*dmae_waitfp)(), caddr_t arg) 45 { 46 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_ACQUIRE, 47 (off_t *)dmae_waitfp, (size_t *)arg, 48 (caddr_t *)(uintptr_t)chnl, 0)); 49 } 50 51 int 52 ddi_dmae_release(dev_info_t *dip, int chnl) 53 { 54 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_FREE, 0, 0, 55 (caddr_t *)(uintptr_t)chnl, 0)); 56 } 57 58 int 59 ddi_dmae_getlim(dev_info_t *dip, ddi_dma_lim_t *limitsp) 60 { 61 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_GETLIM, 0, 0, 62 (caddr_t *)limitsp, 0)); 63 } 64 65 int 66 ddi_dmae_getattr(dev_info_t *dip, ddi_dma_attr_t *attrp) 67 { 68 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_GETATTR, 0, 0, 69 (caddr_t *)attrp, 0)); 70 } 71 72 int 73 ddi_dmae_1stparty(dev_info_t *dip, int chnl) 74 { 75 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_1STPTY, 0, 0, 76 (caddr_t *)(uintptr_t)chnl, 0)); 77 } 78 79 int 80 ddi_dmae_prog(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, 81 ddi_dma_cookie_t *cookiep, int chnl) 82 { 83 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_PROG, (off_t *)dmaereqp, 84 (size_t *)cookiep, (caddr_t *)(uintptr_t)chnl, 0)); 85 } 86 87 int 88 ddi_dmae_swsetup(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, 89 ddi_dma_cookie_t *cookiep, int chnl) 90 { 91 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_SWSETUP, (off_t *)dmaereqp, 92 (size_t *)cookiep, (caddr_t *)(uintptr_t)chnl, 0)); 93 } 94 95 int 96 ddi_dmae_swstart(dev_info_t *dip, int chnl) 97 { 98 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_SWSTART, 0, 0, 99 (caddr_t *)(uintptr_t)chnl, 0)); 100 } 101 102 int 103 ddi_dmae_stop(dev_info_t *dip, int chnl) 104 { 105 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_STOP, 0, 0, 106 (caddr_t *)(uintptr_t)chnl, 0)); 107 } 108 109 int 110 ddi_dmae_enable(dev_info_t *dip, int chnl) 111 { 112 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_ENABLE, 0, 0, 113 (caddr_t *)(uintptr_t)chnl, 0)); 114 } 115 116 int 117 ddi_dmae_disable(dev_info_t *dip, int chnl) 118 { 119 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_DISABLE, 0, 0, 120 (caddr_t *)(uintptr_t)chnl, 0)); 121 } 122 123 int 124 ddi_dmae_getcnt(dev_info_t *dip, int chnl, int *countp) 125 { 126 return (ddi_dma_mctl(dip, dip, 0, DDI_DMA_E_GETCNT, 0, (size_t *)countp, 127 (caddr_t *)(uintptr_t)chnl, 0)); 128 } 129 130 /* 131 * implementation specific access handle and routines: 132 */ 133 134 static uintptr_t impl_acc_hdl_id = 0; 135 136 /* 137 * access handle allocator 138 */ 139 ddi_acc_hdl_t * 140 impl_acc_hdl_get(ddi_acc_handle_t hdl) 141 { 142 /* 143 * recast to ddi_acc_hdl_t instead of 144 * casting to ddi_acc_impl_t and then return the ah_platform_private 145 * 146 * this optimization based on the ddi_acc_hdl_t is the 147 * first member of the ddi_acc_impl_t. 148 */ 149 return ((ddi_acc_hdl_t *)hdl); 150 } 151 152 ddi_acc_handle_t 153 impl_acc_hdl_alloc(int (*waitfp)(caddr_t), caddr_t arg) 154 { 155 ddi_acc_impl_t *hp; 156 on_trap_data_t *otp; 157 int sleepflag; 158 159 sleepflag = ((waitfp == (int (*)())KM_SLEEP) ? KM_SLEEP : KM_NOSLEEP); 160 /* 161 * Allocate and initialize the data access handle and error status. 162 */ 163 if ((hp = kmem_zalloc(sizeof (ddi_acc_impl_t), sleepflag)) == NULL) 164 goto fail; 165 if ((hp->ahi_err = (ndi_err_t *)kmem_zalloc( 166 sizeof (ndi_err_t), sleepflag)) == NULL) { 167 kmem_free(hp, sizeof (ddi_acc_impl_t)); 168 goto fail; 169 } 170 if ((otp = (on_trap_data_t *)kmem_zalloc( 171 sizeof (on_trap_data_t), sleepflag)) == NULL) { 172 kmem_free(hp->ahi_err, sizeof (ndi_err_t)); 173 kmem_free(hp, sizeof (ddi_acc_impl_t)); 174 goto fail; 175 } 176 hp->ahi_err->err_ontrap = otp; 177 hp->ahi_common.ah_platform_private = (void *)hp; 178 179 return ((ddi_acc_handle_t)hp); 180 fail: 181 if ((waitfp != (int (*)())KM_SLEEP) && 182 (waitfp != (int (*)())KM_NOSLEEP)) 183 ddi_set_callback(waitfp, arg, &impl_acc_hdl_id); 184 return (NULL); 185 } 186 187 void 188 impl_acc_hdl_free(ddi_acc_handle_t handle) 189 { 190 ddi_acc_impl_t *hp; 191 192 /* 193 * The supplied (ddi_acc_handle_t) is actually a (ddi_acc_impl_t *), 194 * because that's what we allocated in impl_acc_hdl_alloc() above. 195 */ 196 hp = (ddi_acc_impl_t *)handle; 197 if (hp) { 198 kmem_free(hp->ahi_err->err_ontrap, sizeof (on_trap_data_t)); 199 kmem_free(hp->ahi_err, sizeof (ndi_err_t)); 200 kmem_free(hp, sizeof (ddi_acc_impl_t)); 201 if (impl_acc_hdl_id) 202 ddi_run_callback(&impl_acc_hdl_id); 203 } 204 } 205 206 /* 207 * Function used to check if a given access handle owns the failing address. 208 * Called by ndi_fmc_error, when we detect a PIO error. 209 */ 210 /* ARGSUSED */ 211 static int 212 impl_acc_check(dev_info_t *dip, const void *handle, const void *addr, 213 const void *not_used) 214 { 215 pfn_t pfn, fault_pfn; 216 ddi_acc_hdl_t *hp; 217 218 hp = impl_acc_hdl_get((ddi_acc_handle_t)handle); 219 220 ASSERT(hp); 221 222 if (addr != NULL) { 223 pfn = hp->ah_pfn; 224 fault_pfn = mmu_btop(*(uint64_t *)addr); 225 if (fault_pfn >= pfn && fault_pfn < (pfn + hp->ah_pnum)) 226 return (DDI_FM_NONFATAL); 227 } 228 return (DDI_FM_UNKNOWN); 229 } 230 231 void 232 impl_acc_err_init(ddi_acc_hdl_t *handlep) 233 { 234 int fmcap; 235 ndi_err_t *errp; 236 on_trap_data_t *otp; 237 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handlep; 238 239 fmcap = ddi_fm_capable(handlep->ah_dip); 240 241 if (handlep->ah_acc.devacc_attr_version < DDI_DEVICE_ATTR_V1 || 242 !DDI_FM_ACC_ERR_CAP(fmcap)) { 243 handlep->ah_acc.devacc_attr_access = DDI_DEFAULT_ACC; 244 } else if (handlep->ah_acc.devacc_attr_access == DDI_FLAGERR_ACC && 245 hp->ahi_scan == NULL) { 246 handlep->ah_acc.devacc_attr_access = DDI_DEFAULT_ACC; 247 } else if (DDI_FM_ACC_ERR_CAP(fmcap)) { 248 if (handlep->ah_acc.devacc_attr_access == DDI_DEFAULT_ACC) { 249 if (handlep->ah_xfermodes) 250 return; 251 i_ddi_drv_ereport_post(handlep->ah_dip, DVR_EFMCAP, 252 NULL, DDI_NOSLEEP); 253 } else { 254 errp = hp->ahi_err; 255 otp = (on_trap_data_t *)errp->err_ontrap; 256 otp->ot_handle = (void *)(hp); 257 otp->ot_prot = OT_DATA_ACCESS; 258 errp->err_status = DDI_FM_OK; 259 errp->err_expected = DDI_FM_ERR_UNEXPECTED; 260 errp->err_cf = impl_acc_check; 261 } 262 } 263 } 264 265 /* ARGSUSED */ 266 int 267 impl_dma_check(dev_info_t *dip, const void *handle, const void *pci_hdl, 268 const void *not_used) 269 { 270 return (DDI_FM_UNKNOWN); 271 } 272 273 void 274 impl_acc_hdl_init(ddi_acc_hdl_t *handlep) 275 { 276 ddi_acc_impl_t *hp; 277 int fmcap; 278 int devacc_attr_access; 279 280 if (!handlep) 281 return; 282 fmcap = ddi_fm_capable(handlep->ah_dip); 283 if (handlep->ah_acc.devacc_attr_version < DDI_DEVICE_ATTR_V1 || 284 !DDI_FM_ACC_ERR_CAP(fmcap)) 285 devacc_attr_access = DDI_DEFAULT_ACC; 286 else 287 devacc_attr_access = handlep->ah_acc.devacc_attr_access; 288 289 hp = (ddi_acc_impl_t *)handlep->ah_platform_private; 290 291 /* 292 * Can only do FLAGERR if scan callback is set up. This should 293 * also guarantee that the peekpoke_mutex and err_mutex are defined. 294 */ 295 if (devacc_attr_access == DDI_FLAGERR_ACC && hp->ahi_scan == NULL) 296 devacc_attr_access = DDI_DEFAULT_ACC; 297 298 switch (devacc_attr_access) { 299 case DDI_CAUTIOUS_ACC: 300 hp->ahi_get8 = i_ddi_caut_get8; 301 hp->ahi_put8 = i_ddi_caut_put8; 302 hp->ahi_rep_get8 = i_ddi_caut_rep_get8; 303 hp->ahi_rep_put8 = i_ddi_caut_rep_put8; 304 hp->ahi_get16 = i_ddi_caut_get16; 305 hp->ahi_get32 = i_ddi_caut_get32; 306 hp->ahi_put16 = i_ddi_caut_put16; 307 hp->ahi_put32 = i_ddi_caut_put32; 308 hp->ahi_rep_get16 = i_ddi_caut_rep_get16; 309 hp->ahi_rep_get32 = i_ddi_caut_rep_get32; 310 hp->ahi_rep_put16 = i_ddi_caut_rep_put16; 311 hp->ahi_rep_put32 = i_ddi_caut_rep_put32; 312 hp->ahi_get64 = i_ddi_caut_get64; 313 hp->ahi_put64 = i_ddi_caut_put64; 314 hp->ahi_rep_get64 = i_ddi_caut_rep_get64; 315 hp->ahi_rep_put64 = i_ddi_caut_rep_put64; 316 break; 317 case DDI_FLAGERR_ACC: 318 if (hp->ahi_acc_attr & DDI_ACCATTR_IO_SPACE) { 319 hp->ahi_get8 = i_ddi_prot_io_get8; 320 hp->ahi_put8 = i_ddi_prot_io_put8; 321 hp->ahi_rep_get8 = i_ddi_prot_io_rep_get8; 322 hp->ahi_rep_put8 = i_ddi_prot_io_rep_put8; 323 324 /* temporary set these 64 functions to no-ops */ 325 hp->ahi_get64 = i_ddi_io_get64; 326 hp->ahi_put64 = i_ddi_io_put64; 327 hp->ahi_rep_get64 = i_ddi_io_rep_get64; 328 hp->ahi_rep_put64 = i_ddi_io_rep_put64; 329 330 /* 331 * check for BIG endian access 332 */ 333 if (handlep->ah_acc.devacc_attr_endian_flags == 334 DDI_STRUCTURE_BE_ACC) { 335 hp->ahi_get16 = i_ddi_prot_io_swap_get16; 336 hp->ahi_get32 = i_ddi_prot_io_swap_get32; 337 hp->ahi_put16 = i_ddi_prot_io_swap_put16; 338 hp->ahi_put32 = i_ddi_prot_io_swap_put32; 339 hp->ahi_rep_get16 = 340 i_ddi_prot_io_swap_rep_get16; 341 hp->ahi_rep_get32 = 342 i_ddi_prot_io_swap_rep_get32; 343 hp->ahi_rep_put16 = 344 i_ddi_prot_io_swap_rep_put16; 345 hp->ahi_rep_put32 = 346 i_ddi_prot_io_swap_rep_put32; 347 } else { 348 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT; 349 hp->ahi_get16 = i_ddi_prot_io_get16; 350 hp->ahi_get32 = i_ddi_prot_io_get32; 351 hp->ahi_put16 = i_ddi_prot_io_put16; 352 hp->ahi_put32 = i_ddi_prot_io_put32; 353 hp->ahi_rep_get16 = i_ddi_prot_io_rep_get16; 354 hp->ahi_rep_get32 = i_ddi_prot_io_rep_get32; 355 hp->ahi_rep_put16 = i_ddi_prot_io_rep_put16; 356 hp->ahi_rep_put32 = i_ddi_prot_io_rep_put32; 357 } 358 359 } else if (hp->ahi_acc_attr & DDI_ACCATTR_CPU_VADDR) { 360 361 hp->ahi_get8 = i_ddi_prot_vaddr_get8; 362 hp->ahi_put8 = i_ddi_prot_vaddr_put8; 363 hp->ahi_rep_get8 = i_ddi_prot_vaddr_rep_get8; 364 hp->ahi_rep_put8 = i_ddi_prot_vaddr_rep_put8; 365 366 /* 367 * check for BIG endian access 368 */ 369 if (handlep->ah_acc.devacc_attr_endian_flags == 370 DDI_STRUCTURE_BE_ACC) { 371 372 hp->ahi_get16 = i_ddi_prot_vaddr_swap_get16; 373 hp->ahi_get32 = i_ddi_prot_vaddr_swap_get32; 374 hp->ahi_get64 = i_ddi_prot_vaddr_swap_get64; 375 hp->ahi_put16 = i_ddi_prot_vaddr_swap_put16; 376 hp->ahi_put32 = i_ddi_prot_vaddr_swap_put32; 377 hp->ahi_put64 = i_ddi_prot_vaddr_swap_put64; 378 hp->ahi_rep_get16 = 379 i_ddi_prot_vaddr_swap_rep_get16; 380 hp->ahi_rep_get32 = 381 i_ddi_prot_vaddr_swap_rep_get32; 382 hp->ahi_rep_get64 = 383 i_ddi_prot_vaddr_swap_rep_get64; 384 hp->ahi_rep_put16 = 385 i_ddi_prot_vaddr_swap_rep_put16; 386 hp->ahi_rep_put32 = 387 i_ddi_prot_vaddr_swap_rep_put32; 388 hp->ahi_rep_put64 = 389 i_ddi_prot_vaddr_swap_rep_put64; 390 } else { 391 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT; 392 hp->ahi_get16 = i_ddi_prot_vaddr_get16; 393 hp->ahi_get32 = i_ddi_prot_vaddr_get32; 394 hp->ahi_get64 = i_ddi_prot_vaddr_get64; 395 hp->ahi_put16 = i_ddi_prot_vaddr_put16; 396 hp->ahi_put32 = i_ddi_prot_vaddr_put32; 397 hp->ahi_put64 = i_ddi_prot_vaddr_put64; 398 hp->ahi_rep_get16 = i_ddi_prot_vaddr_rep_get16; 399 hp->ahi_rep_get32 = i_ddi_prot_vaddr_rep_get32; 400 hp->ahi_rep_get64 = i_ddi_prot_vaddr_rep_get64; 401 hp->ahi_rep_put16 = i_ddi_prot_vaddr_rep_put16; 402 hp->ahi_rep_put32 = i_ddi_prot_vaddr_rep_put32; 403 hp->ahi_rep_put64 = i_ddi_prot_vaddr_rep_put64; 404 } 405 } 406 break; 407 case DDI_DEFAULT_ACC: 408 if (hp->ahi_acc_attr & DDI_ACCATTR_IO_SPACE) { 409 hp->ahi_get8 = i_ddi_io_get8; 410 hp->ahi_put8 = i_ddi_io_put8; 411 hp->ahi_rep_get8 = i_ddi_io_rep_get8; 412 hp->ahi_rep_put8 = i_ddi_io_rep_put8; 413 414 /* temporary set these 64 functions to no-ops */ 415 hp->ahi_get64 = i_ddi_io_get64; 416 hp->ahi_put64 = i_ddi_io_put64; 417 hp->ahi_rep_get64 = i_ddi_io_rep_get64; 418 hp->ahi_rep_put64 = i_ddi_io_rep_put64; 419 420 /* 421 * check for BIG endian access 422 */ 423 if (handlep->ah_acc.devacc_attr_endian_flags == 424 DDI_STRUCTURE_BE_ACC) { 425 hp->ahi_get16 = i_ddi_io_swap_get16; 426 hp->ahi_get32 = i_ddi_io_swap_get32; 427 hp->ahi_put16 = i_ddi_io_swap_put16; 428 hp->ahi_put32 = i_ddi_io_swap_put32; 429 hp->ahi_rep_get16 = i_ddi_io_swap_rep_get16; 430 hp->ahi_rep_get32 = i_ddi_io_swap_rep_get32; 431 hp->ahi_rep_put16 = i_ddi_io_swap_rep_put16; 432 hp->ahi_rep_put32 = i_ddi_io_swap_rep_put32; 433 } else { 434 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT; 435 hp->ahi_get16 = i_ddi_io_get16; 436 hp->ahi_get32 = i_ddi_io_get32; 437 hp->ahi_put16 = i_ddi_io_put16; 438 hp->ahi_put32 = i_ddi_io_put32; 439 hp->ahi_rep_get16 = i_ddi_io_rep_get16; 440 hp->ahi_rep_get32 = i_ddi_io_rep_get32; 441 hp->ahi_rep_put16 = i_ddi_io_rep_put16; 442 hp->ahi_rep_put32 = i_ddi_io_rep_put32; 443 } 444 445 } else if (hp->ahi_acc_attr & DDI_ACCATTR_CPU_VADDR) { 446 447 hp->ahi_get8 = i_ddi_vaddr_get8; 448 hp->ahi_put8 = i_ddi_vaddr_put8; 449 hp->ahi_rep_get8 = i_ddi_vaddr_rep_get8; 450 hp->ahi_rep_put8 = i_ddi_vaddr_rep_put8; 451 452 /* 453 * check for BIG endian access 454 */ 455 if (handlep->ah_acc.devacc_attr_endian_flags == 456 DDI_STRUCTURE_BE_ACC) { 457 458 hp->ahi_get16 = i_ddi_vaddr_swap_get16; 459 hp->ahi_get32 = i_ddi_vaddr_swap_get32; 460 hp->ahi_get64 = i_ddi_vaddr_swap_get64; 461 hp->ahi_put16 = i_ddi_vaddr_swap_put16; 462 hp->ahi_put32 = i_ddi_vaddr_swap_put32; 463 hp->ahi_put64 = i_ddi_vaddr_swap_put64; 464 hp->ahi_rep_get16 = i_ddi_vaddr_swap_rep_get16; 465 hp->ahi_rep_get32 = i_ddi_vaddr_swap_rep_get32; 466 hp->ahi_rep_get64 = i_ddi_vaddr_swap_rep_get64; 467 hp->ahi_rep_put16 = i_ddi_vaddr_swap_rep_put16; 468 hp->ahi_rep_put32 = i_ddi_vaddr_swap_rep_put32; 469 hp->ahi_rep_put64 = i_ddi_vaddr_swap_rep_put64; 470 } else { 471 hp->ahi_acc_attr |= DDI_ACCATTR_DIRECT; 472 hp->ahi_get16 = i_ddi_vaddr_get16; 473 hp->ahi_get32 = i_ddi_vaddr_get32; 474 hp->ahi_get64 = i_ddi_vaddr_get64; 475 hp->ahi_put16 = i_ddi_vaddr_put16; 476 hp->ahi_put32 = i_ddi_vaddr_put32; 477 hp->ahi_put64 = i_ddi_vaddr_put64; 478 hp->ahi_rep_get16 = i_ddi_vaddr_rep_get16; 479 hp->ahi_rep_get32 = i_ddi_vaddr_rep_get32; 480 hp->ahi_rep_get64 = i_ddi_vaddr_rep_get64; 481 hp->ahi_rep_put16 = i_ddi_vaddr_rep_put16; 482 hp->ahi_rep_put32 = i_ddi_vaddr_rep_put32; 483 hp->ahi_rep_put64 = i_ddi_vaddr_rep_put64; 484 } 485 } 486 break; 487 } 488 hp->ahi_fault_check = i_ddi_acc_fault_check; 489 hp->ahi_fault_notify = i_ddi_acc_fault_notify; 490 hp->ahi_fault = 0; 491 impl_acc_err_init(handlep); 492 } 493 494 /* 495 * The followings are low-level routines for data access. 496 * 497 * All of these routines should be implemented in assembly. Those 498 * that have been rewritten be found in ~ml/ddi_i86_asm.s 499 */ 500 501 /*ARGSUSED*/ 502 uint16_t 503 i_ddi_vaddr_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr) 504 { 505 return (ddi_swap16(*addr)); 506 } 507 508 /*ARGSUSED*/ 509 uint16_t 510 i_ddi_io_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr) 511 { 512 return (ddi_swap16(inw((uintptr_t)addr))); 513 } 514 515 /*ARGSUSED*/ 516 uint32_t 517 i_ddi_vaddr_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr) 518 { 519 return (ddi_swap32(*addr)); 520 } 521 522 /*ARGSUSED*/ 523 uint32_t 524 i_ddi_io_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr) 525 { 526 return (ddi_swap32(inl((uintptr_t)addr))); 527 } 528 529 /*ARGSUSED*/ 530 uint64_t 531 i_ddi_vaddr_swap_get64(ddi_acc_impl_t *hdlp, uint64_t *addr) 532 { 533 return (ddi_swap64(*addr)); 534 } 535 536 /*ARGSUSED*/ 537 void 538 i_ddi_vaddr_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) 539 { 540 *addr = ddi_swap16(value); 541 } 542 543 /*ARGSUSED*/ 544 void 545 i_ddi_io_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) 546 { 547 outw((uintptr_t)addr, ddi_swap16(value)); 548 } 549 550 /*ARGSUSED*/ 551 void 552 i_ddi_vaddr_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value) 553 { 554 *addr = ddi_swap32(value); 555 } 556 557 /*ARGSUSED*/ 558 void 559 i_ddi_io_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value) 560 { 561 outl((uintptr_t)addr, ddi_swap32(value)); 562 } 563 564 /*ARGSUSED*/ 565 void 566 i_ddi_vaddr_swap_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, uint64_t value) 567 { 568 *addr = ddi_swap64(value); 569 } 570 571 /*ARGSUSED*/ 572 void 573 i_ddi_vaddr_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, 574 uint8_t *dev_addr, size_t repcount, uint_t flags) 575 { 576 uint8_t *h, *d; 577 578 h = host_addr; 579 d = dev_addr; 580 581 if (flags == DDI_DEV_AUTOINCR) 582 for (; repcount; repcount--) 583 *h++ = *d++; 584 else 585 for (; repcount; repcount--) 586 *h++ = *d; 587 } 588 589 /*ARGSUSED*/ 590 void 591 i_ddi_vaddr_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 592 uint16_t *dev_addr, size_t repcount, uint_t flags) 593 { 594 uint16_t *h, *d; 595 596 h = host_addr; 597 d = dev_addr; 598 599 if (flags == DDI_DEV_AUTOINCR) 600 for (; repcount; repcount--) 601 *h++ = *d++; 602 else 603 for (; repcount; repcount--) 604 *h++ = *d; 605 } 606 607 /*ARGSUSED*/ 608 void 609 i_ddi_vaddr_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 610 uint16_t *dev_addr, size_t repcount, uint_t flags) 611 { 612 uint16_t *h, *d; 613 614 h = host_addr; 615 d = dev_addr; 616 617 if (flags == DDI_DEV_AUTOINCR) 618 for (; repcount; repcount--) 619 *h++ = ddi_swap16(*d++); 620 else 621 for (; repcount; repcount--) 622 *h++ = ddi_swap16(*d); 623 } 624 625 /*ARGSUSED*/ 626 void 627 i_ddi_io_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 628 uint16_t *dev_addr, size_t repcount, uint_t flags) 629 { 630 uint16_t *h; 631 uintptr_t port; 632 633 h = host_addr; 634 port = (uintptr_t)dev_addr; 635 636 if (flags == DDI_DEV_AUTOINCR) 637 for (; repcount; repcount--, port += 2) 638 *h++ = ddi_swap16(inw(port)); 639 else 640 for (; repcount; repcount--) 641 *h++ = ddi_swap16(inw(port)); 642 } 643 644 /*ARGSUSED*/ 645 void 646 i_ddi_vaddr_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 647 uint32_t *dev_addr, size_t repcount, uint_t flags) 648 { 649 uint32_t *h, *d; 650 651 h = host_addr; 652 d = dev_addr; 653 654 if (flags == DDI_DEV_AUTOINCR) 655 for (; repcount; repcount--) 656 *h++ = *d++; 657 else 658 for (; repcount; repcount--) 659 *h++ = *d; 660 } 661 662 /*ARGSUSED*/ 663 void 664 i_ddi_vaddr_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 665 uint32_t *dev_addr, size_t repcount, uint_t flags) 666 { 667 uint32_t *h, *d; 668 669 h = host_addr; 670 d = dev_addr; 671 672 if (flags == DDI_DEV_AUTOINCR) 673 for (; repcount; repcount--) 674 *h++ = ddi_swap32(*d++); 675 else 676 for (; repcount; repcount--) 677 *h++ = ddi_swap32(*d); 678 } 679 680 /*ARGSUSED*/ 681 void 682 i_ddi_io_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 683 uint32_t *dev_addr, size_t repcount, uint_t flags) 684 { 685 uint32_t *h; 686 uintptr_t port; 687 688 h = host_addr; 689 port = (uintptr_t)dev_addr; 690 691 if (flags == DDI_DEV_AUTOINCR) 692 for (; repcount; repcount--, port += 4) 693 *h++ = ddi_swap32(inl(port)); 694 else 695 for (; repcount; repcount--) 696 *h++ = ddi_swap32(inl(port)); 697 } 698 699 /*ARGSUSED*/ 700 void 701 i_ddi_vaddr_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 702 uint64_t *dev_addr, size_t repcount, uint_t flags) 703 { 704 uint64_t *h, *d; 705 706 h = host_addr; 707 d = dev_addr; 708 709 if (flags == DDI_DEV_AUTOINCR) 710 for (; repcount; repcount--) 711 *h++ = *d++; 712 else 713 for (; repcount; repcount--) 714 *h++ = *d; 715 } 716 717 /*ARGSUSED*/ 718 void 719 i_ddi_vaddr_swap_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 720 uint64_t *dev_addr, size_t repcount, uint_t flags) 721 { 722 uint64_t *h, *d; 723 724 h = host_addr; 725 d = dev_addr; 726 727 if (flags == DDI_DEV_AUTOINCR) 728 for (; repcount; repcount--) 729 *h++ = ddi_swap64(*d++); 730 else 731 for (; repcount; repcount--) 732 *h++ = ddi_swap64(*d); 733 } 734 735 /*ARGSUSED*/ 736 void 737 i_ddi_vaddr_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, 738 uint8_t *dev_addr, size_t repcount, uint_t flags) 739 { 740 uint8_t *h, *d; 741 742 h = host_addr; 743 d = dev_addr; 744 745 if (flags == DDI_DEV_AUTOINCR) 746 for (; repcount; repcount--) 747 *d++ = *h++; 748 else 749 for (; repcount; repcount--) 750 *d = *h++; 751 } 752 753 /*ARGSUSED*/ 754 void 755 i_ddi_vaddr_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 756 uint16_t *dev_addr, size_t repcount, uint_t flags) 757 { 758 uint16_t *h, *d; 759 760 h = host_addr; 761 d = dev_addr; 762 763 if (flags == DDI_DEV_AUTOINCR) 764 for (; repcount; repcount--) 765 *d++ = *h++; 766 else 767 for (; repcount; repcount--) 768 *d = *h++; 769 } 770 771 /*ARGSUSED*/ 772 void 773 i_ddi_vaddr_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 774 uint16_t *dev_addr, size_t repcount, uint_t flags) 775 { 776 uint16_t *h, *d; 777 778 h = host_addr; 779 d = dev_addr; 780 781 if (flags == DDI_DEV_AUTOINCR) 782 for (; repcount; repcount--) 783 *d++ = ddi_swap16(*h++); 784 else 785 for (; repcount; repcount--) 786 *d = ddi_swap16(*h++); 787 } 788 789 /*ARGSUSED*/ 790 void 791 i_ddi_io_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 792 uint16_t *dev_addr, size_t repcount, uint_t flags) 793 { 794 uint16_t *h; 795 uintptr_t port; 796 797 h = host_addr; 798 port = (uintptr_t)dev_addr; 799 800 if (flags == DDI_DEV_AUTOINCR) 801 for (; repcount; repcount--, port += 2) 802 outw(port, ddi_swap16(*h++)); 803 else 804 for (; repcount; repcount--) 805 outw(port, ddi_swap16(*h++)); 806 } 807 808 /*ARGSUSED*/ 809 void 810 i_ddi_vaddr_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 811 uint32_t *dev_addr, size_t repcount, uint_t flags) 812 { 813 uint32_t *h, *d; 814 815 h = host_addr; 816 d = dev_addr; 817 818 if (flags == DDI_DEV_AUTOINCR) 819 for (; repcount; repcount--) 820 *d++ = *h++; 821 else 822 for (; repcount; repcount--) 823 *d = *h++; 824 } 825 826 /*ARGSUSED*/ 827 void 828 i_ddi_vaddr_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 829 uint32_t *dev_addr, size_t repcount, uint_t flags) 830 { 831 uint32_t *h, *d; 832 833 h = host_addr; 834 d = dev_addr; 835 836 if (flags == DDI_DEV_AUTOINCR) 837 for (; repcount; repcount--) 838 *d++ = ddi_swap32(*h++); 839 else 840 for (; repcount; repcount--) 841 *d = ddi_swap32(*h++); 842 } 843 844 /*ARGSUSED*/ 845 void 846 i_ddi_io_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 847 uint32_t *dev_addr, size_t repcount, uint_t flags) 848 { 849 uint32_t *h; 850 uintptr_t port; 851 852 h = host_addr; 853 port = (uintptr_t)dev_addr; 854 855 if (flags == DDI_DEV_AUTOINCR) 856 for (; repcount; repcount--, port += 4) 857 outl(port, ddi_swap32(*h++)); 858 else 859 for (; repcount; repcount--) 860 outl(port, ddi_swap32(*h++)); 861 } 862 863 /*ARGSUSED*/ 864 void 865 i_ddi_vaddr_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 866 uint64_t *dev_addr, size_t repcount, uint_t flags) 867 { 868 uint64_t *h, *d; 869 870 h = host_addr; 871 d = dev_addr; 872 873 if (flags == DDI_DEV_AUTOINCR) 874 for (; repcount; repcount--) 875 *d++ = *h++; 876 else 877 for (; repcount; repcount--) 878 *d = *h++; 879 } 880 881 /*ARGSUSED*/ 882 void 883 i_ddi_vaddr_swap_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 884 uint64_t *dev_addr, size_t repcount, uint_t flags) 885 { 886 uint64_t *h, *d; 887 888 h = host_addr; 889 d = dev_addr; 890 891 if (flags == DDI_DEV_AUTOINCR) 892 for (; repcount; repcount--) 893 *d++ = ddi_swap64(*h++); 894 else 895 for (; repcount; repcount--) 896 *d = ddi_swap64(*h++); 897 } 898 899 /*ARGSUSED*/ 900 uint64_t 901 i_ddi_io_get64(ddi_acc_impl_t *hdlp, uint64_t *addr) 902 { 903 panic("ddi_get64 from i/o space"); 904 /*NOTREACHED*/ 905 return (0); 906 } 907 908 /*ARGSUSED*/ 909 void 910 i_ddi_io_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, uint64_t value) 911 { 912 panic("ddi_put64 to i/o space"); 913 /*NOTREACHED*/ 914 } 915 916 void 917 do_scan(ddi_acc_impl_t *hdlp) 918 { 919 ddi_fm_error_t de; 920 ndi_err_t *errp = (ndi_err_t *)hdlp->ahi_err; 921 922 bzero(&de, sizeof (ddi_fm_error_t)); 923 de.fme_version = DDI_FME_VERSION; 924 de.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 925 de.fme_flag = DDI_FM_ERR_UNEXPECTED; 926 927 mutex_enter(hdlp->ahi_err_mutexp); 928 hdlp->ahi_scan(hdlp->ahi_scan_dip, &de); 929 if (de.fme_status != DDI_FM_OK) { 930 errp->err_ena = de.fme_ena; 931 errp->err_expected = de.fme_flag; 932 errp->err_status = DDI_FM_NONFATAL; 933 } 934 mutex_exit(hdlp->ahi_err_mutexp); 935 } 936 937 /*ARGSUSED*/ 938 uint8_t 939 i_ddi_prot_vaddr_get8(ddi_acc_impl_t *hdlp, uint8_t *addr) 940 { 941 uint8_t val; 942 943 mutex_enter(hdlp->ahi_peekpoke_mutexp); 944 val = *addr; 945 if (val == 0xff) 946 do_scan(hdlp); 947 mutex_exit(hdlp->ahi_peekpoke_mutexp); 948 949 return (val); 950 } 951 952 /*ARGSUSED*/ 953 uint16_t 954 i_ddi_prot_vaddr_get16(ddi_acc_impl_t *hdlp, uint16_t *addr) 955 { 956 uint16_t val; 957 958 mutex_enter(hdlp->ahi_peekpoke_mutexp); 959 val = *addr; 960 if (val == 0xffff) 961 do_scan(hdlp); 962 mutex_exit(hdlp->ahi_peekpoke_mutexp); 963 964 return (val); 965 } 966 967 /*ARGSUSED*/ 968 uint32_t 969 i_ddi_prot_vaddr_get32(ddi_acc_impl_t *hdlp, uint32_t *addr) 970 { 971 uint32_t val; 972 973 mutex_enter(hdlp->ahi_peekpoke_mutexp); 974 val = *addr; 975 if (val == 0xffffffff) 976 do_scan(hdlp); 977 mutex_exit(hdlp->ahi_peekpoke_mutexp); 978 979 return (val); 980 } 981 982 /*ARGSUSED*/ 983 uint64_t 984 i_ddi_prot_vaddr_get64(ddi_acc_impl_t *hdlp, uint64_t *addr) 985 { 986 uint64_t val; 987 988 mutex_enter(hdlp->ahi_peekpoke_mutexp); 989 val = *addr; 990 if (val == 0xffffffffffffffff) 991 do_scan(hdlp); 992 mutex_exit(hdlp->ahi_peekpoke_mutexp); 993 994 return (val); 995 } 996 997 /*ARGSUSED*/ 998 uint8_t 999 i_ddi_prot_io_get8(ddi_acc_impl_t *hdlp, uint8_t *addr) 1000 { 1001 uint8_t val; 1002 1003 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1004 val = inb((uintptr_t)addr); 1005 if (val == 0xff) 1006 do_scan(hdlp); 1007 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1008 1009 return (val); 1010 } 1011 1012 /*ARGSUSED*/ 1013 uint16_t 1014 i_ddi_prot_io_get16(ddi_acc_impl_t *hdlp, uint16_t *addr) 1015 { 1016 uint16_t val; 1017 1018 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1019 val = inw((uintptr_t)addr); 1020 if (val == 0xffff) 1021 do_scan(hdlp); 1022 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1023 1024 return (val); 1025 } 1026 1027 /*ARGSUSED*/ 1028 uint32_t 1029 i_ddi_prot_io_get32(ddi_acc_impl_t *hdlp, uint32_t *addr) 1030 { 1031 uint32_t val; 1032 1033 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1034 val = inl((uintptr_t)addr); 1035 if (val == 0xffffffff) 1036 do_scan(hdlp); 1037 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1038 1039 return (val); 1040 } 1041 1042 /*ARGSUSED*/ 1043 uint16_t 1044 i_ddi_prot_vaddr_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr) 1045 { 1046 uint16_t val; 1047 1048 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1049 val = ddi_swap16(*addr); 1050 if (val == 0xffff) 1051 do_scan(hdlp); 1052 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1053 1054 return (val); 1055 } 1056 1057 /*ARGSUSED*/ 1058 uint16_t 1059 i_ddi_prot_io_swap_get16(ddi_acc_impl_t *hdlp, uint16_t *addr) 1060 { 1061 uint16_t val; 1062 1063 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1064 val = ddi_swap16(inw((uintptr_t)addr)); 1065 if (val == 0xffff) 1066 do_scan(hdlp); 1067 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1068 1069 return (val); 1070 } 1071 1072 /*ARGSUSED*/ 1073 uint32_t 1074 i_ddi_prot_vaddr_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr) 1075 { 1076 uint32_t val; 1077 1078 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1079 val = ddi_swap32(*addr); 1080 if (val == 0xffffffff) 1081 do_scan(hdlp); 1082 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1083 1084 return (val); 1085 } 1086 1087 /*ARGSUSED*/ 1088 uint32_t 1089 i_ddi_prot_io_swap_get32(ddi_acc_impl_t *hdlp, uint32_t *addr) 1090 { 1091 uint32_t val; 1092 1093 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1094 val = ddi_swap32(inl((uintptr_t)addr)); 1095 if (val == 0xffffffff) 1096 do_scan(hdlp); 1097 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1098 1099 return (val); 1100 } 1101 1102 /*ARGSUSED*/ 1103 uint64_t 1104 i_ddi_prot_vaddr_swap_get64(ddi_acc_impl_t *hdlp, uint64_t *addr) 1105 { 1106 uint64_t val; 1107 1108 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1109 val = ddi_swap64(*addr); 1110 if (val == 0xffffffffffffffff) 1111 do_scan(hdlp); 1112 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1113 1114 return (val); 1115 } 1116 1117 /*ARGSUSED*/ 1118 void 1119 i_ddi_prot_vaddr_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value) 1120 { 1121 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1122 *addr = value; 1123 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1124 } 1125 1126 /*ARGSUSED*/ 1127 void 1128 i_ddi_prot_io_put8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value) 1129 { 1130 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1131 outb((uintptr_t)addr, value); 1132 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1133 } 1134 1135 /*ARGSUSED*/ 1136 void 1137 i_ddi_prot_vaddr_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) 1138 { 1139 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1140 *addr = value; 1141 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1142 } 1143 1144 /*ARGSUSED*/ 1145 void 1146 i_ddi_prot_io_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) 1147 { 1148 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1149 outw((uintptr_t)addr, value); 1150 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1151 } 1152 1153 /*ARGSUSED*/ 1154 void 1155 i_ddi_prot_vaddr_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, 1156 uint32_t value) 1157 { 1158 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1159 *addr = value; 1160 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1161 } 1162 1163 /*ARGSUSED*/ 1164 void 1165 i_ddi_prot_io_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value) 1166 { 1167 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1168 outl((uintptr_t)addr, value); 1169 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1170 } 1171 1172 /*ARGSUSED*/ 1173 void 1174 i_ddi_prot_vaddr_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, 1175 uint64_t value) 1176 { 1177 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1178 *addr = value; 1179 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1180 } 1181 1182 /*ARGSUSED*/ 1183 void 1184 i_ddi_prot_vaddr_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, 1185 uint16_t value) 1186 { 1187 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1188 *addr = ddi_swap16(value); 1189 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1190 } 1191 1192 /*ARGSUSED*/ 1193 void 1194 i_ddi_prot_io_swap_put16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value) 1195 { 1196 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1197 outw((uintptr_t)addr, ddi_swap16(value)); 1198 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1199 } 1200 1201 /*ARGSUSED*/ 1202 void 1203 i_ddi_prot_vaddr_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, 1204 uint32_t value) 1205 { 1206 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1207 *addr = ddi_swap32(value); 1208 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1209 } 1210 1211 /*ARGSUSED*/ 1212 void 1213 i_ddi_prot_io_swap_put32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value) 1214 { 1215 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1216 outl((uintptr_t)addr, ddi_swap32(value)); 1217 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1218 } 1219 1220 /*ARGSUSED*/ 1221 void 1222 i_ddi_prot_vaddr_swap_put64(ddi_acc_impl_t *hdlp, uint64_t *addr, 1223 uint64_t value) 1224 { 1225 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1226 *addr = ddi_swap64(value); 1227 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1228 } 1229 1230 /*ARGSUSED*/ 1231 void 1232 i_ddi_prot_io_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, 1233 uint8_t *dev_addr, size_t repcount, uint_t flags) 1234 { 1235 int fail = 0; 1236 uint8_t *h; 1237 uintptr_t port; 1238 1239 h = host_addr; 1240 port = (uintptr_t)dev_addr; 1241 1242 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1243 if (flags == DDI_DEV_AUTOINCR) { 1244 for (; repcount; repcount--, port++) 1245 if ((*h++ = inb(port)) == 0xff) 1246 fail = 1; 1247 } else { 1248 for (; repcount; repcount--) 1249 if ((*h++ = inb(port)) == 0xff) 1250 fail = 1; 1251 } 1252 if (fail == 1) 1253 do_scan(hdlp); 1254 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1255 } 1256 1257 /*ARGSUSED*/ 1258 void 1259 i_ddi_prot_io_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1260 uint16_t *dev_addr, size_t repcount, uint_t flags) 1261 { 1262 int fail = 0; 1263 uint16_t *h; 1264 uintptr_t port; 1265 1266 h = host_addr; 1267 port = (uintptr_t)dev_addr; 1268 1269 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1270 if (flags == DDI_DEV_AUTOINCR) { 1271 for (; repcount; repcount--, port += 2) 1272 if ((*h++ = inw(port)) == 0xffff) 1273 fail = 1; 1274 } else { 1275 for (; repcount; repcount--) 1276 if ((*h++ = inw(port)) == 0xffff) 1277 fail = 1; 1278 } 1279 if (fail == 1) 1280 do_scan(hdlp); 1281 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1282 } 1283 1284 /*ARGSUSED*/ 1285 void 1286 i_ddi_prot_io_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1287 uint32_t *dev_addr, size_t repcount, uint_t flags) 1288 { 1289 int fail = 0; 1290 uint32_t *h; 1291 uintptr_t port; 1292 1293 h = host_addr; 1294 port = (uintptr_t)dev_addr; 1295 1296 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1297 if (flags == DDI_DEV_AUTOINCR) { 1298 for (; repcount; repcount--, port += 4) 1299 if ((*h++ = inl(port)) == 0xffffffff) 1300 fail = 1; 1301 } else { 1302 for (; repcount; repcount--) 1303 if ((*h++ = inl(port)) == 0xffffffff) 1304 fail = 1; 1305 } 1306 if (fail == 1) 1307 do_scan(hdlp); 1308 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1309 } 1310 1311 /*ARGSUSED*/ 1312 void 1313 i_ddi_prot_vaddr_rep_get8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, 1314 uint8_t *dev_addr, size_t repcount, uint_t flags) 1315 { 1316 int fail = 0; 1317 uint8_t *h, *d; 1318 1319 h = host_addr; 1320 d = dev_addr; 1321 1322 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1323 if (flags == DDI_DEV_AUTOINCR) { 1324 for (; repcount; repcount--) 1325 if ((*h++ = *d++) == 0xff) 1326 fail = 1; 1327 } else { 1328 for (; repcount; repcount--) 1329 if ((*h++ = *d) == 0xff) 1330 fail = 1; 1331 } 1332 if (fail == 1) 1333 do_scan(hdlp); 1334 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1335 } 1336 1337 /*ARGSUSED*/ 1338 void 1339 i_ddi_prot_vaddr_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1340 uint16_t *dev_addr, size_t repcount, uint_t flags) 1341 { 1342 int fail = 0; 1343 uint16_t *h, *d; 1344 1345 h = host_addr; 1346 d = dev_addr; 1347 1348 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1349 if (flags == DDI_DEV_AUTOINCR) { 1350 for (; repcount; repcount--) 1351 if ((*h++ = *d++) == 0xffff) 1352 fail = 1; 1353 } else { 1354 for (; repcount; repcount--) 1355 if ((*h++ = *d) == 0xffff) 1356 fail = 1; 1357 } 1358 if (fail == 1) 1359 do_scan(hdlp); 1360 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1361 } 1362 1363 /*ARGSUSED*/ 1364 void 1365 i_ddi_prot_vaddr_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1366 uint16_t *dev_addr, size_t repcount, uint_t flags) 1367 { 1368 int fail = 0; 1369 uint16_t *h, *d; 1370 1371 h = host_addr; 1372 d = dev_addr; 1373 1374 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1375 if (flags == DDI_DEV_AUTOINCR) { 1376 for (; repcount; repcount--) 1377 if ((*h++ = ddi_swap16(*d++)) == 0xffff) 1378 fail = 1; 1379 } else { 1380 for (; repcount; repcount--) 1381 if ((*h++ = ddi_swap16(*d)) == 0xffff) 1382 fail = 1; 1383 } 1384 if (fail == 1) 1385 do_scan(hdlp); 1386 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1387 } 1388 1389 /*ARGSUSED*/ 1390 void 1391 i_ddi_prot_io_swap_rep_get16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1392 uint16_t *dev_addr, size_t repcount, uint_t flags) 1393 { 1394 int fail = 0; 1395 uint16_t *h; 1396 uintptr_t port; 1397 1398 h = host_addr; 1399 port = (uintptr_t)dev_addr; 1400 1401 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1402 if (flags == DDI_DEV_AUTOINCR) { 1403 for (; repcount; repcount--, port += 2) 1404 if ((*h++ = ddi_swap16(inw(port))) == 0xffff) 1405 fail = 1; 1406 } else { 1407 for (; repcount; repcount--) 1408 if ((*h++ = ddi_swap16(inw(port))) == 0xffff) 1409 fail = 1; 1410 } 1411 if (fail == 1) 1412 do_scan(hdlp); 1413 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1414 } 1415 1416 /*ARGSUSED*/ 1417 void 1418 i_ddi_prot_vaddr_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1419 uint32_t *dev_addr, size_t repcount, uint_t flags) 1420 { 1421 int fail = 0; 1422 uint32_t *h, *d; 1423 1424 h = host_addr; 1425 d = dev_addr; 1426 1427 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1428 if (flags == DDI_DEV_AUTOINCR) { 1429 for (; repcount; repcount--) 1430 if ((*h++ = *d++) == 0xffffffff) 1431 fail = 1; 1432 } else { 1433 for (; repcount; repcount--) 1434 if ((*h++ = *d) == 0xffffffff) 1435 fail = 1; 1436 } 1437 if (fail == 1) 1438 do_scan(hdlp); 1439 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1440 } 1441 1442 /*ARGSUSED*/ 1443 void 1444 i_ddi_prot_vaddr_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1445 uint32_t *dev_addr, size_t repcount, uint_t flags) 1446 { 1447 int fail = 0; 1448 uint32_t *h, *d; 1449 1450 h = host_addr; 1451 d = dev_addr; 1452 1453 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1454 if (flags == DDI_DEV_AUTOINCR) { 1455 for (; repcount; repcount--) 1456 if ((*h++ = ddi_swap32(*d++)) == 0xffffffff) 1457 fail = 1; 1458 } else { 1459 for (; repcount; repcount--) 1460 if ((*h++ = ddi_swap32(*d)) == 0xffffffff) 1461 fail = 1; 1462 } 1463 if (fail == 1) 1464 do_scan(hdlp); 1465 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1466 } 1467 1468 /*ARGSUSED*/ 1469 void 1470 i_ddi_prot_io_swap_rep_get32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1471 uint32_t *dev_addr, size_t repcount, uint_t flags) 1472 { 1473 int fail = 0; 1474 uint32_t *h; 1475 uintptr_t port; 1476 1477 h = host_addr; 1478 port = (uintptr_t)dev_addr; 1479 1480 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1481 if (flags == DDI_DEV_AUTOINCR) { 1482 for (; repcount; repcount--, port += 4) 1483 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff) 1484 fail = 1; 1485 } else { 1486 for (; repcount; repcount--) 1487 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff) 1488 fail = 1; 1489 } 1490 if (fail == 1) 1491 do_scan(hdlp); 1492 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1493 } 1494 1495 /*ARGSUSED*/ 1496 void 1497 i_ddi_prot_vaddr_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 1498 uint64_t *dev_addr, size_t repcount, uint_t flags) 1499 { 1500 int fail = 0; 1501 uint64_t *h, *d; 1502 1503 h = host_addr; 1504 d = dev_addr; 1505 1506 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1507 if (flags == DDI_DEV_AUTOINCR) { 1508 for (; repcount; repcount--) 1509 if ((*h++ = *d++) == 0xffffffffffffffff) 1510 fail = 1; 1511 } else { 1512 for (; repcount; repcount--) 1513 if ((*h++ = *d) == 0xffffffffffffffff) 1514 fail = 1; 1515 } 1516 if (fail == 1) 1517 do_scan(hdlp); 1518 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1519 } 1520 1521 /*ARGSUSED*/ 1522 void 1523 i_ddi_prot_vaddr_swap_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 1524 uint64_t *dev_addr, size_t repcount, uint_t flags) 1525 { 1526 int fail = 0; 1527 uint64_t *h, *d; 1528 1529 h = host_addr; 1530 d = dev_addr; 1531 1532 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1533 if (flags == DDI_DEV_AUTOINCR) { 1534 for (; repcount; repcount--) 1535 if ((*h++ = ddi_swap64(*d++)) == 0xffffffffffffffff) 1536 fail = 1; 1537 } else { 1538 for (; repcount; repcount--) 1539 if ((*h++ = ddi_swap64(*d)) == 0xffffffffffffffff) 1540 fail = 1; 1541 } 1542 if (fail == 1) 1543 do_scan(hdlp); 1544 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1545 } 1546 1547 /*ARGSUSED*/ 1548 void 1549 i_ddi_prot_vaddr_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, 1550 uint8_t *dev_addr, size_t repcount, uint_t flags) 1551 { 1552 uint8_t *h, *d; 1553 1554 h = host_addr; 1555 d = dev_addr; 1556 1557 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1558 if (flags == DDI_DEV_AUTOINCR) 1559 for (; repcount; repcount--) 1560 *d++ = *h++; 1561 else 1562 for (; repcount; repcount--) 1563 *d = *h++; 1564 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1565 } 1566 1567 /*ARGSUSED*/ 1568 void 1569 i_ddi_prot_io_rep_put8(ddi_acc_impl_t *hdlp, uint8_t *host_addr, 1570 uint8_t *dev_addr, size_t repcount, uint_t flags) 1571 { 1572 uint8_t *h; 1573 uintptr_t port; 1574 1575 h = host_addr; 1576 port = (uintptr_t)dev_addr; 1577 1578 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1579 if (flags == DDI_DEV_AUTOINCR) 1580 for (; repcount; repcount--, port++) 1581 outb(port, *h++); 1582 else 1583 for (; repcount; repcount--) 1584 outb(port, *h++); 1585 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1586 } 1587 1588 /*ARGSUSED*/ 1589 void 1590 i_ddi_prot_vaddr_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1591 uint16_t *dev_addr, size_t repcount, uint_t flags) 1592 { 1593 uint16_t *h, *d; 1594 1595 h = host_addr; 1596 d = dev_addr; 1597 1598 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1599 if (flags == DDI_DEV_AUTOINCR) 1600 for (; repcount; repcount--) 1601 *d++ = *h++; 1602 else 1603 for (; repcount; repcount--) 1604 *d = *h++; 1605 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1606 } 1607 1608 /*ARGSUSED*/ 1609 void 1610 i_ddi_prot_io_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1611 uint16_t *dev_addr, size_t repcount, uint_t flags) 1612 { 1613 uint16_t *h; 1614 uintptr_t port; 1615 1616 h = host_addr; 1617 port = (uintptr_t)dev_addr; 1618 1619 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1620 if (flags == DDI_DEV_AUTOINCR) 1621 for (; repcount; repcount--, port += 2) 1622 outw(port, *h++); 1623 else 1624 for (; repcount; repcount--) 1625 outw(port, *h++); 1626 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1627 } 1628 1629 /*ARGSUSED*/ 1630 void 1631 i_ddi_prot_vaddr_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1632 uint16_t *dev_addr, size_t repcount, uint_t flags) 1633 { 1634 uint16_t *h, *d; 1635 1636 h = host_addr; 1637 d = dev_addr; 1638 1639 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1640 if (flags == DDI_DEV_AUTOINCR) 1641 for (; repcount; repcount--) 1642 *d++ = ddi_swap16(*h++); 1643 else 1644 for (; repcount; repcount--) 1645 *d = ddi_swap16(*h++); 1646 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1647 } 1648 1649 /*ARGSUSED*/ 1650 void 1651 i_ddi_prot_io_swap_rep_put16(ddi_acc_impl_t *hdlp, uint16_t *host_addr, 1652 uint16_t *dev_addr, size_t repcount, uint_t flags) 1653 { 1654 uint16_t *h; 1655 uintptr_t port; 1656 1657 h = host_addr; 1658 port = (uintptr_t)dev_addr; 1659 1660 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1661 if (flags == DDI_DEV_AUTOINCR) 1662 for (; repcount; repcount--, port += 2) 1663 outw(port, ddi_swap16(*h++)); 1664 else 1665 for (; repcount; repcount--) 1666 outw(port, ddi_swap16(*h++)); 1667 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1668 } 1669 1670 /*ARGSUSED*/ 1671 void 1672 i_ddi_prot_vaddr_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1673 uint32_t *dev_addr, size_t repcount, uint_t flags) 1674 { 1675 uint32_t *h, *d; 1676 1677 h = host_addr; 1678 d = dev_addr; 1679 1680 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1681 if (flags == DDI_DEV_AUTOINCR) 1682 for (; repcount; repcount--) 1683 *d++ = *h++; 1684 else 1685 for (; repcount; repcount--) 1686 *d = *h++; 1687 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1688 } 1689 1690 /*ARGSUSED*/ 1691 void 1692 i_ddi_prot_io_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1693 uint32_t *dev_addr, size_t repcount, uint_t flags) 1694 { 1695 uint32_t *h; 1696 uintptr_t port; 1697 1698 h = host_addr; 1699 port = (uintptr_t)dev_addr; 1700 1701 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1702 if (flags == DDI_DEV_AUTOINCR) 1703 for (; repcount; repcount--, port += 4) 1704 outl(port, *h++); 1705 else 1706 for (; repcount; repcount--) 1707 outl(port, *h++); 1708 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1709 } 1710 1711 /*ARGSUSED*/ 1712 void 1713 i_ddi_prot_vaddr_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1714 uint32_t *dev_addr, size_t repcount, uint_t flags) 1715 { 1716 uint32_t *h, *d; 1717 1718 h = host_addr; 1719 d = dev_addr; 1720 1721 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1722 if (flags == DDI_DEV_AUTOINCR) 1723 for (; repcount; repcount--) 1724 *d++ = ddi_swap32(*h++); 1725 else 1726 for (; repcount; repcount--) 1727 *d = ddi_swap32(*h++); 1728 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1729 } 1730 1731 /*ARGSUSED*/ 1732 void 1733 i_ddi_prot_io_swap_rep_put32(ddi_acc_impl_t *hdlp, uint32_t *host_addr, 1734 uint32_t *dev_addr, size_t repcount, uint_t flags) 1735 { 1736 uint32_t *h; 1737 uintptr_t port; 1738 1739 h = host_addr; 1740 port = (uintptr_t)dev_addr; 1741 1742 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1743 if (flags == DDI_DEV_AUTOINCR) 1744 for (; repcount; repcount--, port += 4) 1745 outl(port, ddi_swap32(*h++)); 1746 else 1747 for (; repcount; repcount--) 1748 outl(port, ddi_swap32(*h++)); 1749 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1750 } 1751 1752 /*ARGSUSED*/ 1753 void 1754 i_ddi_prot_vaddr_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 1755 uint64_t *dev_addr, size_t repcount, uint_t flags) 1756 { 1757 uint64_t *h, *d; 1758 1759 h = host_addr; 1760 d = dev_addr; 1761 1762 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1763 if (flags == DDI_DEV_AUTOINCR) 1764 for (; repcount; repcount--) 1765 *d++ = *h++; 1766 else 1767 for (; repcount; repcount--) 1768 *d = *h++; 1769 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1770 } 1771 1772 /*ARGSUSED*/ 1773 void 1774 i_ddi_prot_vaddr_swap_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 1775 uint64_t *dev_addr, size_t repcount, uint_t flags) 1776 { 1777 uint64_t *h, *d; 1778 1779 h = host_addr; 1780 d = dev_addr; 1781 1782 mutex_enter(hdlp->ahi_peekpoke_mutexp); 1783 if (flags == DDI_DEV_AUTOINCR) 1784 for (; repcount; repcount--) 1785 *d++ = ddi_swap64(*h++); 1786 else 1787 for (; repcount; repcount--) 1788 *d = ddi_swap64(*h++); 1789 mutex_exit(hdlp->ahi_peekpoke_mutexp); 1790 } 1791 1792 void 1793 ddi_io_rep_get8(ddi_acc_handle_t handle, 1794 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount) 1795 { 1796 (((ddi_acc_impl_t *)handle)->ahi_rep_get8) 1797 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1798 repcount, DDI_DEV_NO_AUTOINCR); 1799 } 1800 1801 void 1802 ddi_io_rep_get16(ddi_acc_handle_t handle, 1803 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount) 1804 { 1805 (((ddi_acc_impl_t *)handle)->ahi_rep_get16) 1806 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1807 repcount, DDI_DEV_NO_AUTOINCR); 1808 } 1809 1810 void 1811 ddi_io_rep_get32(ddi_acc_handle_t handle, 1812 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount) 1813 { 1814 (((ddi_acc_impl_t *)handle)->ahi_rep_get32) 1815 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1816 repcount, DDI_DEV_NO_AUTOINCR); 1817 } 1818 1819 /*ARGSUSED*/ 1820 void 1821 i_ddi_io_rep_get64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 1822 uint64_t *dev_addr, size_t repcount, uint_t flags) 1823 { 1824 cmn_err(CE_PANIC, "ddi_rep_get64 from i/o space"); 1825 } 1826 1827 void 1828 ddi_io_rep_put8(ddi_acc_handle_t handle, 1829 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount) 1830 { 1831 (((ddi_acc_impl_t *)handle)->ahi_rep_put8) 1832 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1833 repcount, DDI_DEV_NO_AUTOINCR); 1834 } 1835 1836 void 1837 ddi_io_rep_put16(ddi_acc_handle_t handle, 1838 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount) 1839 { 1840 (((ddi_acc_impl_t *)handle)->ahi_rep_put16) 1841 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1842 repcount, DDI_DEV_NO_AUTOINCR); 1843 } 1844 1845 void 1846 ddi_io_rep_put32(ddi_acc_handle_t handle, 1847 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount) 1848 { 1849 (((ddi_acc_impl_t *)handle)->ahi_rep_put32) 1850 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1851 repcount, DDI_DEV_NO_AUTOINCR); 1852 } 1853 1854 /*ARGSUSED*/ 1855 void 1856 i_ddi_io_rep_put64(ddi_acc_impl_t *hdlp, uint64_t *host_addr, 1857 uint64_t *dev_addr, size_t repcount, uint_t flags) 1858 { 1859 cmn_err(CE_PANIC, "ddi_rep_put64 to i/o space"); 1860 } 1861 1862 /* 1863 * We need to separate the old interfaces from the new ones and leave them 1864 * in here for a while. Previous versions of the OS defined the new interfaces 1865 * to the old interfaces. This way we can fix things up so that we can 1866 * eventually remove these interfaces. 1867 * e.g. A 3rd party module/driver using ddi_io_rep_get8 and built against S10 1868 * or earlier will actually have a reference to ddi_io_rep_getb in the binary. 1869 */ 1870 #ifdef _ILP32 1871 void 1872 ddi_io_rep_getb(ddi_acc_handle_t handle, 1873 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount) 1874 { 1875 (((ddi_acc_impl_t *)handle)->ahi_rep_get8) 1876 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1877 repcount, DDI_DEV_NO_AUTOINCR); 1878 } 1879 1880 void 1881 ddi_io_rep_getw(ddi_acc_handle_t handle, 1882 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount) 1883 { 1884 (((ddi_acc_impl_t *)handle)->ahi_rep_get16) 1885 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1886 repcount, DDI_DEV_NO_AUTOINCR); 1887 } 1888 1889 void 1890 ddi_io_rep_getl(ddi_acc_handle_t handle, 1891 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount) 1892 { 1893 (((ddi_acc_impl_t *)handle)->ahi_rep_get32) 1894 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1895 repcount, DDI_DEV_NO_AUTOINCR); 1896 } 1897 1898 void 1899 ddi_io_rep_putb(ddi_acc_handle_t handle, 1900 uint8_t *host_addr, uint8_t *dev_addr, size_t repcount) 1901 { 1902 (((ddi_acc_impl_t *)handle)->ahi_rep_put8) 1903 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1904 repcount, DDI_DEV_NO_AUTOINCR); 1905 } 1906 1907 void 1908 ddi_io_rep_putw(ddi_acc_handle_t handle, 1909 uint16_t *host_addr, uint16_t *dev_addr, size_t repcount) 1910 { 1911 (((ddi_acc_impl_t *)handle)->ahi_rep_put16) 1912 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1913 repcount, DDI_DEV_NO_AUTOINCR); 1914 } 1915 1916 void 1917 ddi_io_rep_putl(ddi_acc_handle_t handle, 1918 uint32_t *host_addr, uint32_t *dev_addr, size_t repcount) 1919 { 1920 (((ddi_acc_impl_t *)handle)->ahi_rep_put32) 1921 ((ddi_acc_impl_t *)handle, host_addr, dev_addr, 1922 repcount, DDI_DEV_NO_AUTOINCR); 1923 } 1924 #endif /* _ILP32 */ 1925 1926 /* 1927 * These next two functions could be translated into assembler someday 1928 */ 1929 int 1930 ddi_check_acc_handle(ddi_acc_handle_t handle) 1931 { 1932 ddi_acc_impl_t *hdlp = (ddi_acc_impl_t *)handle; 1933 return (((*hdlp->ahi_fault_check)(hdlp) == DDI_SUCCESS) ? DDI_SUCCESS : 1934 DDI_FAILURE); 1935 } 1936 1937 int 1938 i_ddi_acc_fault_check(ddi_acc_impl_t *hdlp) 1939 { 1940 /* Default version, just returns flag value */ 1941 return (hdlp->ahi_fault); 1942 } 1943 1944 /*ARGSUSED*/ 1945 void 1946 i_ddi_acc_fault_notify(ddi_acc_impl_t *hdlp) 1947 { 1948 /* Default version, does nothing for now */ 1949 } 1950 1951 void 1952 i_ddi_acc_set_fault(ddi_acc_handle_t handle) 1953 { 1954 ddi_acc_impl_t *hdlp = (ddi_acc_impl_t *)handle; 1955 1956 if (!hdlp->ahi_fault) { 1957 hdlp->ahi_fault = 1; 1958 (*hdlp->ahi_fault_notify)(hdlp); 1959 } 1960 } 1961 1962 void 1963 i_ddi_acc_clr_fault(ddi_acc_handle_t handle) 1964 { 1965 ddi_acc_impl_t *hdlp = (ddi_acc_impl_t *)handle; 1966 1967 if (hdlp->ahi_fault) { 1968 hdlp->ahi_fault = 0; 1969 (*hdlp->ahi_fault_notify)(hdlp); 1970 } 1971 } 1972