1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * x86-specific routines used by the CPU Performance counter driver. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/time.h> 35 #include <sys/atomic.h> 36 #include <sys/regset.h> 37 #include <sys/privregs.h> 38 #include <sys/x86_archext.h> 39 #include <sys/cpuvar.h> 40 #include <sys/machcpuvar.h> 41 #include <sys/archsystm.h> 42 #include <sys/cpc_pcbe.h> 43 #include <sys/cpc_impl.h> 44 #include <sys/x_call.h> 45 #include <sys/cmn_err.h> 46 #include <sys/chip.h> 47 #include <sys/spl.h> 48 #include <io/pcplusmp/apic.h> 49 50 static const uint64_t allstopped = 0; 51 static kcpc_ctx_t *(*overflow_intr_handler)(caddr_t); 52 53 int kcpc_hw_overflow_intr_installed; /* set by APIC code */ 54 extern kcpc_ctx_t *kcpc_overflow_intr(caddr_t arg, uint64_t bitmap); 55 56 extern int kcpc_counts_include_idle; /* Project Private /etc/system variable */ 57 58 void (*kcpc_hw_enable_cpc_intr)(void); /* set by APIC code */ 59 60 int 61 kcpc_hw_add_ovf_intr(kcpc_ctx_t *(*handler)(caddr_t)) 62 { 63 if (x86_type != X86_TYPE_P6) 64 return (0); 65 overflow_intr_handler = handler; 66 return (ipltospl(APIC_PCINT_IPL)); 67 } 68 69 void 70 kcpc_hw_rem_ovf_intr(void) 71 { 72 overflow_intr_handler = NULL; 73 } 74 75 /* 76 * Hook used on P4 systems to catch online/offline events. 77 */ 78 /*ARGSUSED*/ 79 static int 80 kcpc_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 81 { 82 chip_t *chp = cpu[cpuid]->cpu_chip; 83 84 if (what != CPU_ON) 85 return (0); 86 87 /* 88 * If any CPU-bound contexts exist, we don't need to invalidate 89 * anything, as no per-LWP contexts can coexist. 90 */ 91 if (kcpc_cpuctx) 92 return (0); 93 94 /* 95 * If this chip now has more than 1 active cpu, we must invalidate all 96 * contexts in the system. 97 */ 98 if (chp->chip_ncpu > 1) 99 kcpc_invalidate_all(); 100 101 return (0); 102 } 103 104 static kmutex_t cpu_setup_lock; /* protects setup_registered */ 105 static int setup_registered; 106 107 void 108 kcpc_hw_init(cpu_t *cp) 109 { 110 kthread_t *t = cp->cpu_idle_thread; 111 112 if (x86_feature & X86_HTT) { 113 mutex_enter(&cpu_setup_lock); 114 if (setup_registered == 0) { 115 mutex_enter(&cpu_lock); 116 register_cpu_setup_func(kcpc_cpu_setup, NULL); 117 mutex_exit(&cpu_lock); 118 setup_registered = 1; 119 } 120 mutex_exit(&cpu_setup_lock); 121 } 122 123 mutex_init(&cp->cpu_cpc_ctxlock, "cpu_cpc_ctxlock", MUTEX_DEFAULT, 0); 124 125 if (kcpc_counts_include_idle) 126 return; 127 128 installctx(t, cp, kcpc_idle_save, kcpc_idle_restore, 129 NULL, NULL, NULL, NULL); 130 } 131 132 #define BITS(v, u, l) \ 133 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 134 135 #define PCBE_NAMELEN 30 /* Enough Room for pcbe.manuf.model.family.stepping */ 136 137 /* 138 * Examine the processor and load an appropriate PCBE. 139 */ 140 int 141 kcpc_hw_load_pcbe(void) 142 { 143 return (kcpc_pcbe_tryload(cpuid_getvendorstr(CPU), cpuid_getfamily(CPU), 144 cpuid_getmodel(CPU), cpuid_getstep(CPU))); 145 } 146 147 static int 148 kcpc_remotestop_func(void) 149 { 150 ASSERT(CPU->cpu_cpc_ctx != NULL); 151 pcbe_ops->pcbe_allstop(); 152 atomic_or_uint(&CPU->cpu_cpc_ctx->kc_flags, KCPC_CTX_INVALID_STOPPED); 153 154 return (0); 155 } 156 157 /* 158 * Ensure the counters are stopped on the given processor. 159 * 160 * Callers must ensure kernel preemption is disabled. 161 */ 162 void 163 kcpc_remote_stop(cpu_t *cp) 164 { 165 cpuset_t set; 166 167 CPUSET_ZERO(set); 168 169 CPUSET_ADD(set, cp->cpu_id); 170 171 xc_sync(0, 0, 0, X_CALL_HIPRI, set, (xc_func_t)kcpc_remotestop_func); 172 } 173 174 /* 175 * Called by the generic framework to check if it's OK to bind a set to a CPU. 176 */ 177 int 178 kcpc_hw_cpu_hook(processorid_t cpuid, ulong_t *kcpc_cpumap) 179 { 180 cpu_t *p, *cpu; 181 182 if ((x86_feature & X86_HTT) == 0) 183 return (0); 184 185 /* 186 * Only one logical CPU on each Pentium 4 HT CPU may be bound to at 187 * once. 188 * 189 * This loop is protected by holding cpu_lock, in order to properly 190 * access the cpu_t of the desired cpu. This also guarantees that the 191 * per chip cpu lists will not change whilst we look at them. 192 */ 193 mutex_enter(&cpu_lock); 194 if ((cpu = cpu_get(cpuid)) == NULL) { 195 mutex_exit(&cpu_lock); 196 return (-1); 197 } 198 199 for (p = cpu->cpu_next_chip; p != cpu; p = p->cpu_next_chip) { 200 if (BT_TEST(kcpc_cpumap, p->cpu_id)) { 201 mutex_exit(&cpu_lock); 202 return (-1); 203 } 204 } 205 206 mutex_exit(&cpu_lock); 207 return (0); 208 } 209 210 /* 211 * Called by the generic framework to check if it's OK to bind a set to an LWP. 212 */ 213 int 214 kcpc_hw_lwp_hook(void) 215 { 216 chip_t *p; 217 218 if ((x86_feature & X86_HTT) == 0) 219 return (0); 220 221 /* 222 * Only one CPU per chip may be online. 223 */ 224 mutex_enter(&cpu_lock); 225 p = CPU->cpu_chip; 226 do { 227 if (p->chip_ncpu > 1) { 228 mutex_exit(&cpu_lock); 229 return (-1); 230 } 231 p = p->chip_next; 232 } while (p != CPU->cpu_chip); 233 mutex_exit(&cpu_lock); 234 return (0); 235 } 236