1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/vmparam.h> 35 #include <sys/systm.h> 36 #include <sys/signal.h> 37 #include <sys/stack.h> 38 #include <sys/regset.h> 39 #include <sys/privregs.h> 40 #include <sys/frame.h> 41 #include <sys/proc.h> 42 #include <sys/psw.h> 43 #include <sys/siginfo.h> 44 #include <sys/cpuvar.h> 45 #include <sys/asm_linkage.h> 46 #include <sys/kmem.h> 47 #include <sys/errno.h> 48 #include <sys/bootconf.h> 49 #include <sys/archsystm.h> 50 #include <sys/debug.h> 51 #include <sys/elf.h> 52 #include <sys/spl.h> 53 #include <sys/time.h> 54 #include <sys/atomic.h> 55 #include <sys/sysmacros.h> 56 #include <sys/cmn_err.h> 57 #include <sys/modctl.h> 58 #include <sys/kobj.h> 59 #include <sys/panic.h> 60 #include <sys/reboot.h> 61 #include <sys/time.h> 62 #include <sys/fp.h> 63 #include <sys/x86_archext.h> 64 #include <sys/auxv.h> 65 #include <sys/auxv_386.h> 66 #include <sys/dtrace.h> 67 #include <sys/brand.h> 68 #include <sys/machbrand.h> 69 70 extern const struct fnsave_state x87_initial; 71 extern const struct fxsave_state sse_initial; 72 73 /* 74 * Map an fnsave-formatted save area into an fxsave-formatted save area. 75 * 76 * Most fields are the same width, content and semantics. However 77 * the tag word is compressed. 78 */ 79 static void 80 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx) 81 { 82 uint_t i, tagbits; 83 84 fx->fx_fcw = fn->f_fcw; 85 fx->fx_fsw = fn->f_fsw; 86 87 /* 88 * copy element by element (because of holes) 89 */ 90 for (i = 0; i < 8; i++) 91 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0], 92 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */ 93 94 /* 95 * synthesize compressed tag bits 96 */ 97 fx->fx_fctw = 0; 98 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2) 99 if ((tagbits & 3) != 3) 100 fx->fx_fctw |= (1 << i); 101 102 fx->fx_fop = fn->f_fop; 103 104 #if defined(__amd64) 105 fx->fx_rip = (uint64_t)fn->f_eip; 106 fx->fx_rdp = (uint64_t)fn->f_dp; 107 #else 108 fx->fx_eip = fn->f_eip; 109 fx->fx_cs = fn->f_cs; 110 fx->__fx_ign0 = 0; 111 fx->fx_dp = fn->f_dp; 112 fx->fx_ds = fn->f_ds; 113 fx->__fx_ign1 = 0; 114 #endif 115 } 116 117 /* 118 * Map from an fxsave-format save area to an fnsave-format save area. 119 */ 120 static void 121 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn) 122 { 123 uint_t i, top, tagbits; 124 125 fn->f_fcw = fx->fx_fcw; 126 fn->__f_ign0 = 0; 127 fn->f_fsw = fx->fx_fsw; 128 fn->__f_ign1 = 0; 129 130 top = (fx->fx_fsw & FPS_TOP) >> 11; 131 132 /* 133 * copy element by element (because of holes) 134 */ 135 for (i = 0; i < 8; i++) 136 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0], 137 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */ 138 139 /* 140 * synthesize uncompressed tag bits 141 */ 142 fn->f_ftw = 0; 143 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) { 144 uint_t ibit, expo; 145 const uint16_t *fpp; 146 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 }; 147 148 if ((tagbits & 1) == 0) { 149 fn->f_ftw |= 3 << (i << 1); /* empty */ 150 continue; 151 } 152 153 /* 154 * (tags refer to *physical* registers) 155 */ 156 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0]; 157 ibit = fpp[3] >> 15; 158 expo = fpp[4] & 0x7fff; 159 160 if (ibit && expo != 0 && expo != 0x7fff) 161 continue; /* valid fp number */ 162 163 if (bcmp(fpp, &zero, sizeof (zero))) 164 fn->f_ftw |= 2 << (i << 1); /* NaN */ 165 else 166 fn->f_ftw |= 1 << (i << 1); /* fp zero */ 167 } 168 169 fn->f_fop = fx->fx_fop; 170 171 fn->__f_ign2 = 0; 172 #if defined(__amd64) 173 fn->f_eip = (uint32_t)fx->fx_rip; 174 fn->f_cs = U32CS_SEL; 175 fn->f_dp = (uint32_t)fx->fx_rdp; 176 fn->f_ds = UDS_SEL; 177 #else 178 fn->f_eip = fx->fx_eip; 179 fn->f_cs = fx->fx_cs; 180 fn->f_dp = fx->fx_dp; 181 fn->f_ds = fx->fx_ds; 182 #endif 183 fn->__f_ign3 = 0; 184 } 185 186 /* 187 * Map from an fpregset_t into an fxsave-format save area 188 */ 189 static void 190 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx) 191 { 192 #if defined(__amd64) 193 bcopy(fp, fx, sizeof (*fx)); 194 #else 195 const struct fpchip_state *fc = &fp->fp_reg_set.fpchip_state; 196 197 fnsave_to_fxsave((const struct fnsave_state *)fc, fx); 198 fx->fx_mxcsr = fc->mxcsr; 199 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm)); 200 #endif 201 /* 202 * avoid useless #gp exceptions - mask reserved bits 203 */ 204 fx->fx_mxcsr &= sse_mxcsr_mask; 205 } 206 207 /* 208 * Map from an fxsave-format save area into a fpregset_t 209 */ 210 static void 211 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp) 212 { 213 #if defined(__amd64) 214 bcopy(fx, fp, sizeof (*fx)); 215 #else 216 struct fpchip_state *fc = &fp->fp_reg_set.fpchip_state; 217 218 fxsave_to_fnsave(fx, (struct fnsave_state *)fc); 219 fc->mxcsr = fx->fx_mxcsr; 220 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm)); 221 #endif 222 } 223 224 #if defined(_SYSCALL32_IMPL) 225 static void 226 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx) 227 { 228 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state; 229 230 fnsave_to_fxsave((const struct fnsave_state *)fc, fx); 231 /* 232 * avoid useless #gp exceptions - mask reserved bits 233 */ 234 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr; 235 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm)); 236 } 237 238 static void 239 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp) 240 { 241 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state; 242 243 fxsave_to_fnsave(fx, (struct fnsave_state *)fc); 244 fc->mxcsr = fx->fx_mxcsr; 245 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm)); 246 } 247 248 static void 249 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst) 250 { 251 fxsave_to_fpregset32((struct fxsave_state *)src, dst); 252 dst->fp_reg_set.fpchip_state.status = 253 src->fp_reg_set.fpchip_state.status; 254 dst->fp_reg_set.fpchip_state.xstatus = 255 src->fp_reg_set.fpchip_state.xstatus; 256 } 257 258 static void 259 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst) 260 { 261 fpregset32_to_fxsave(src, (struct fxsave_state *)dst); 262 dst->fp_reg_set.fpchip_state.status = 263 src->fp_reg_set.fpchip_state.status; 264 dst->fp_reg_set.fpchip_state.xstatus = 265 src->fp_reg_set.fpchip_state.xstatus; 266 } 267 #endif 268 269 /* 270 * Set floating-point registers from a native fpregset_t. 271 */ 272 void 273 setfpregs(klwp_t *lwp, fpregset_t *fp) 274 { 275 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu; 276 277 if (fpu->fpu_flags & FPU_EN) { 278 if (!(fpu->fpu_flags & FPU_VALID)) { 279 /* 280 * FPU context is still active, release the 281 * ownership. 282 */ 283 fp_free(fpu, 0); 284 } 285 #if !defined(__amd64) 286 if (fp_kind == __FP_SSE) { 287 #endif 288 fpregset_to_fxsave(fp, &fpu->fpu_regs.kfpu_u.kfpu_fx); 289 fpu->fpu_regs.kfpu_xstatus = 290 fp->fp_reg_set.fpchip_state.xstatus; 291 #if !defined(__amd64) 292 } else 293 bcopy(fp, &fpu->fpu_regs.kfpu_u.kfpu_fn, 294 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn)); 295 #endif 296 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status; 297 fpu->fpu_flags |= FPU_VALID; 298 } else { 299 /* 300 * If we are trying to change the FPU state of a thread which 301 * hasn't yet initialized floating point, store the state in 302 * the pcb and indicate that the state is valid. When the 303 * thread enables floating point, it will use this state instead 304 * of the default state. 305 */ 306 #if !defined(__amd64) 307 if (fp_kind == __FP_SSE) { 308 #endif 309 fpregset_to_fxsave(fp, &fpu->fpu_regs.kfpu_u.kfpu_fx); 310 fpu->fpu_regs.kfpu_xstatus = 311 fp->fp_reg_set.fpchip_state.xstatus; 312 #if !defined(__amd64) 313 } else 314 bcopy(fp, &fpu->fpu_regs.kfpu_u.kfpu_fn, 315 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn)); 316 #endif 317 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status; 318 fpu->fpu_flags |= FPU_VALID; 319 } 320 } 321 322 /* 323 * Get floating-point registers into a native fpregset_t. 324 */ 325 void 326 getfpregs(klwp_t *lwp, fpregset_t *fp) 327 { 328 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu; 329 330 kpreempt_disable(); 331 if (fpu->fpu_flags & FPU_EN) { 332 /* 333 * If we have FPU hw and the thread's pcb doesn't have 334 * a valid FPU state then get the state from the hw. 335 */ 336 if (fpu_exists && ttolwp(curthread) == lwp && 337 !(fpu->fpu_flags & FPU_VALID)) 338 fp_save(fpu); /* get the current FPU state */ 339 } 340 341 /* 342 * There are 3 possible cases we have to be aware of here: 343 * 344 * 1. FPU is enabled. FPU state is stored in the current LWP. 345 * 346 * 2. FPU is not enabled, and there have been no intervening /proc 347 * modifications. Return initial FPU state. 348 * 349 * 3. FPU is not enabled, but a /proc consumer has modified FPU state. 350 * FPU state is stored in the current LWP. 351 */ 352 if ((fpu->fpu_flags & FPU_EN) || (fpu->fpu_flags & FPU_VALID)) { 353 /* 354 * Cases 1 and 3. 355 */ 356 #if !defined(__amd64) 357 if (fp_kind == __FP_SSE) { 358 #endif 359 fxsave_to_fpregset(&fpu->fpu_regs.kfpu_u.kfpu_fx, fp); 360 fp->fp_reg_set.fpchip_state.xstatus = 361 fpu->fpu_regs.kfpu_xstatus; 362 #if !defined(__amd64) 363 } else 364 bcopy(&fpu->fpu_regs.kfpu_u.kfpu_fn, fp, 365 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn)); 366 #endif 367 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status; 368 } else { 369 /* 370 * Case 2. 371 */ 372 #if !defined(__amd64) 373 if (fp_kind == __FP_SSE) { 374 #endif 375 fxsave_to_fpregset(&sse_initial, fp); 376 fp->fp_reg_set.fpchip_state.xstatus = 377 fpu->fpu_regs.kfpu_xstatus; 378 #if !defined(__amd64) 379 } else 380 bcopy(&x87_initial, fp, sizeof (x87_initial)); 381 #endif 382 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status; 383 } 384 kpreempt_enable(); 385 } 386 387 #if defined(_SYSCALL32_IMPL) 388 389 /* 390 * Set floating-point registers from an fpregset32_t. 391 */ 392 void 393 setfpregs32(klwp_t *lwp, fpregset32_t *fp) 394 { 395 fpregset_t fpregs; 396 397 fpregset_32ton(fp, &fpregs); 398 setfpregs(lwp, &fpregs); 399 } 400 401 /* 402 * Get floating-point registers into an fpregset32_t. 403 */ 404 void 405 getfpregs32(klwp_t *lwp, fpregset32_t *fp) 406 { 407 fpregset_t fpregs; 408 409 getfpregs(lwp, &fpregs); 410 fpregset_nto32(&fpregs, fp); 411 } 412 413 #endif /* _SYSCALL32_IMPL */ 414 415 /* 416 * Return the general registers 417 */ 418 void 419 getgregs(klwp_t *lwp, gregset_t grp) 420 { 421 struct regs *rp = lwptoregs(lwp); 422 #if defined(__amd64) 423 struct pcb *pcb = &lwp->lwp_pcb; 424 int thisthread = lwptot(lwp) == curthread; 425 426 grp[REG_RDI] = rp->r_rdi; 427 grp[REG_RSI] = rp->r_rsi; 428 grp[REG_RDX] = rp->r_rdx; 429 grp[REG_RCX] = rp->r_rcx; 430 grp[REG_R8] = rp->r_r8; 431 grp[REG_R9] = rp->r_r9; 432 grp[REG_RAX] = rp->r_rax; 433 grp[REG_RBX] = rp->r_rbx; 434 grp[REG_RBP] = rp->r_rbp; 435 grp[REG_R10] = rp->r_r10; 436 grp[REG_R11] = rp->r_r11; 437 grp[REG_R12] = rp->r_r12; 438 grp[REG_R13] = rp->r_r13; 439 grp[REG_R14] = rp->r_r14; 440 grp[REG_R15] = rp->r_r15; 441 grp[REG_FSBASE] = pcb->pcb_fsbase; 442 grp[REG_GSBASE] = pcb->pcb_gsbase; 443 if (thisthread) 444 kpreempt_disable(); 445 if (pcb->pcb_rupdate == 1) { 446 grp[REG_DS] = pcb->pcb_ds; 447 grp[REG_ES] = pcb->pcb_es; 448 grp[REG_FS] = pcb->pcb_fs; 449 grp[REG_GS] = pcb->pcb_gs; 450 } else { 451 grp[REG_DS] = rp->r_ds; 452 grp[REG_ES] = rp->r_es; 453 grp[REG_FS] = rp->r_fs; 454 grp[REG_GS] = rp->r_gs; 455 } 456 if (thisthread) 457 kpreempt_enable(); 458 grp[REG_TRAPNO] = rp->r_trapno; 459 grp[REG_ERR] = rp->r_err; 460 grp[REG_RIP] = rp->r_rip; 461 grp[REG_CS] = rp->r_cs; 462 grp[REG_SS] = rp->r_ss; 463 grp[REG_RFL] = rp->r_rfl; 464 grp[REG_RSP] = rp->r_rsp; 465 #else 466 bcopy(&rp->r_gs, grp, sizeof (gregset_t)); 467 #endif 468 } 469 470 #if defined(_SYSCALL32_IMPL) 471 472 void 473 getgregs32(klwp_t *lwp, gregset32_t grp) 474 { 475 struct regs *rp = lwptoregs(lwp); 476 struct pcb *pcb = &lwp->lwp_pcb; 477 int thisthread = lwptot(lwp) == curthread; 478 479 if (thisthread) 480 kpreempt_disable(); 481 if (pcb->pcb_rupdate == 1) { 482 grp[GS] = (uint16_t)pcb->pcb_gs; 483 grp[FS] = (uint16_t)pcb->pcb_fs; 484 grp[DS] = (uint16_t)pcb->pcb_ds; 485 grp[ES] = (uint16_t)pcb->pcb_es; 486 } else { 487 grp[GS] = (uint16_t)rp->r_gs; 488 grp[FS] = (uint16_t)rp->r_fs; 489 grp[DS] = (uint16_t)rp->r_ds; 490 grp[ES] = (uint16_t)rp->r_es; 491 } 492 if (thisthread) 493 kpreempt_enable(); 494 grp[EDI] = (greg32_t)rp->r_rdi; 495 grp[ESI] = (greg32_t)rp->r_rsi; 496 grp[EBP] = (greg32_t)rp->r_rbp; 497 grp[ESP] = 0; 498 grp[EBX] = (greg32_t)rp->r_rbx; 499 grp[EDX] = (greg32_t)rp->r_rdx; 500 grp[ECX] = (greg32_t)rp->r_rcx; 501 grp[EAX] = (greg32_t)rp->r_rax; 502 grp[TRAPNO] = (greg32_t)rp->r_trapno; 503 grp[ERR] = (greg32_t)rp->r_err; 504 grp[EIP] = (greg32_t)rp->r_rip; 505 grp[CS] = (uint16_t)rp->r_cs; 506 grp[EFL] = (greg32_t)rp->r_rfl; 507 grp[UESP] = (greg32_t)rp->r_rsp; 508 grp[SS] = (uint16_t)rp->r_ss; 509 } 510 511 void 512 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst) 513 { 514 mcontext_t *dmc = &dst->uc_mcontext; 515 const mcontext32_t *smc = &src->uc_mcontext; 516 517 bzero(dst, sizeof (*dst)); 518 dst->uc_flags = src->uc_flags; 519 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link; 520 521 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask)); 522 523 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp; 524 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size; 525 dst->uc_stack.ss_flags = src->uc_stack.ss_flags; 526 527 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS]; 528 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS]; 529 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES]; 530 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS]; 531 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI]; 532 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI]; 533 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP]; 534 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX]; 535 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX]; 536 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX]; 537 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX]; 538 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO]; 539 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR]; 540 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP]; 541 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS]; 542 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL]; 543 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP]; 544 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS]; 545 546 /* 547 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set 548 * otherwise there is no guarantee that anything in fpregs is valid. 549 */ 550 if (src->uc_flags & UC_FPU) 551 fpregset_32ton(&src->uc_mcontext.fpregs, 552 &dst->uc_mcontext.fpregs); 553 } 554 555 #endif /* _SYSCALL32_IMPL */ 556 557 /* 558 * Return the user-level PC. 559 * If in a system call, return the address of the syscall trap. 560 */ 561 greg_t 562 getuserpc() 563 { 564 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc; 565 uint32_t insn; 566 567 if (curthread->t_sysnum == 0) 568 return (upc); 569 570 /* 571 * We might've gotten here from sysenter (0xf 0x34), 572 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0). 573 * 574 * Go peek at the binary to figure it out.. 575 */ 576 if (fuword32((void *)(upc - 2), &insn) != -1 && 577 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f) 578 return (upc - 2); 579 return (upc - 7); 580 } 581 582 /* 583 * Protect segment registers from non-user privilege levels and GDT selectors 584 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment 585 * selector is non-null and not USER_CS/USER_DS, we make sure that the 586 * TI bit is set to point into the LDT and that the RPL is set to 3. 587 * 588 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we 589 * also explicitly zero the top 16 bits since they may be coming from the 590 * user's address space via setcontext(2) or /proc. 591 * 592 * Note about null selector. When running on the hypervisor if we allow a 593 * process to set its %cs to null selector with RPL of 0 the hypervisor will 594 * crash the domain. If running on bare metal we would get a #gp fault and 595 * be able to kill the process and continue on. Therefore we make sure to 596 * force RPL to SEL_UPL even for null selector when setting %cs. 597 */ 598 599 #if defined(IS_CS) || defined(IS_NOT_CS) 600 #error "IS_CS and IS_NOT_CS already defined" 601 #endif 602 603 #define IS_CS 1 604 #define IS_NOT_CS 0 605 606 /*ARGSUSED*/ 607 static greg_t 608 fix_segreg(greg_t sr, int iscs, model_t datamodel) 609 { 610 kthread_t *t = curthread; 611 612 switch (sr &= 0xffff) { 613 614 case 0: 615 if (iscs == IS_CS) 616 return (0 | SEL_UPL); 617 else 618 return (0); 619 620 #if defined(__amd64) 621 /* 622 * If lwp attempts to switch data model then force their 623 * code selector to be null selector. 624 */ 625 case U32CS_SEL: 626 if (datamodel == DATAMODEL_NATIVE) 627 return (0 | SEL_UPL); 628 else 629 return (sr); 630 631 case UCS_SEL: 632 if (datamodel == DATAMODEL_ILP32) 633 return (0 | SEL_UPL); 634 #elif defined(__i386) 635 case UCS_SEL: 636 #endif 637 /*FALLTHROUGH*/ 638 case UDS_SEL: 639 case LWPFS_SEL: 640 case LWPGS_SEL: 641 case SEL_UPL: 642 return (sr); 643 default: 644 break; 645 } 646 647 /* 648 * Allow this process's brand to do any necessary segment register 649 * manipulation. 650 */ 651 if (PROC_IS_BRANDED(t->t_procp) && BRMOP(t->t_procp)->b_fixsegreg) { 652 greg_t bsr = BRMOP(t->t_procp)->b_fixsegreg(sr, datamodel); 653 654 if (bsr == 0 && iscs == IS_CS) 655 return (0 | SEL_UPL); 656 else 657 return (bsr); 658 } 659 660 /* 661 * Force it into the LDT in ring 3 for 32-bit processes, which by 662 * default do not have an LDT, so that any attempt to use an invalid 663 * selector will reference the (non-existant) LDT, and cause a #gp 664 * fault for the process. 665 * 666 * 64-bit processes get the null gdt selector since they 667 * are not allowed to have a private LDT. 668 */ 669 #if defined(__amd64) 670 if (datamodel == DATAMODEL_ILP32) { 671 return (sr | SEL_TI_LDT | SEL_UPL); 672 } else { 673 if (iscs == IS_CS) 674 return (0 | SEL_UPL); 675 else 676 return (0); 677 } 678 679 #elif defined(__i386) 680 return (sr | SEL_TI_LDT | SEL_UPL); 681 #endif 682 } 683 684 /* 685 * Set general registers. 686 */ 687 void 688 setgregs(klwp_t *lwp, gregset_t grp) 689 { 690 struct regs *rp = lwptoregs(lwp); 691 model_t datamodel = lwp_getdatamodel(lwp); 692 693 #if defined(__amd64) 694 struct pcb *pcb = &lwp->lwp_pcb; 695 int thisthread = lwptot(lwp) == curthread; 696 697 if (datamodel == DATAMODEL_NATIVE) { 698 699 if (thisthread) 700 (void) save_syscall_args(); /* copy the args */ 701 702 rp->r_rdi = grp[REG_RDI]; 703 rp->r_rsi = grp[REG_RSI]; 704 rp->r_rdx = grp[REG_RDX]; 705 rp->r_rcx = grp[REG_RCX]; 706 rp->r_r8 = grp[REG_R8]; 707 rp->r_r9 = grp[REG_R9]; 708 rp->r_rax = grp[REG_RAX]; 709 rp->r_rbx = grp[REG_RBX]; 710 rp->r_rbp = grp[REG_RBP]; 711 rp->r_r10 = grp[REG_R10]; 712 rp->r_r11 = grp[REG_R11]; 713 rp->r_r12 = grp[REG_R12]; 714 rp->r_r13 = grp[REG_R13]; 715 rp->r_r14 = grp[REG_R14]; 716 rp->r_r15 = grp[REG_R15]; 717 rp->r_trapno = grp[REG_TRAPNO]; 718 rp->r_err = grp[REG_ERR]; 719 rp->r_rip = grp[REG_RIP]; 720 /* 721 * Setting %cs or %ss to anything else is quietly but 722 * quite definitely forbidden! 723 */ 724 rp->r_cs = UCS_SEL; 725 rp->r_ss = UDS_SEL; 726 rp->r_rsp = grp[REG_RSP]; 727 728 if (thisthread) 729 kpreempt_disable(); 730 731 pcb->pcb_ds = UDS_SEL; 732 pcb->pcb_es = UDS_SEL; 733 734 /* 735 * 64-bit processes -are- allowed to set their fsbase/gsbase 736 * values directly, but only if they're using the segment 737 * selectors that allow that semantic. 738 * 739 * (32-bit processes must use lwp_set_private().) 740 */ 741 pcb->pcb_fsbase = grp[REG_FSBASE]; 742 pcb->pcb_gsbase = grp[REG_GSBASE]; 743 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel); 744 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel); 745 746 /* 747 * Ensure that we go out via update_sregs 748 */ 749 pcb->pcb_rupdate = 1; 750 lwptot(lwp)->t_post_sys = 1; 751 if (thisthread) 752 kpreempt_enable(); 753 #if defined(_SYSCALL32_IMPL) 754 } else { 755 rp->r_rdi = (uint32_t)grp[REG_RDI]; 756 rp->r_rsi = (uint32_t)grp[REG_RSI]; 757 rp->r_rdx = (uint32_t)grp[REG_RDX]; 758 rp->r_rcx = (uint32_t)grp[REG_RCX]; 759 rp->r_rax = (uint32_t)grp[REG_RAX]; 760 rp->r_rbx = (uint32_t)grp[REG_RBX]; 761 rp->r_rbp = (uint32_t)grp[REG_RBP]; 762 rp->r_trapno = (uint32_t)grp[REG_TRAPNO]; 763 rp->r_err = (uint32_t)grp[REG_ERR]; 764 rp->r_rip = (uint32_t)grp[REG_RIP]; 765 766 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel); 767 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel); 768 769 rp->r_rsp = (uint32_t)grp[REG_RSP]; 770 771 if (thisthread) 772 kpreempt_disable(); 773 774 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel); 775 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel); 776 777 /* 778 * (See fsbase/gsbase commentary above) 779 */ 780 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel); 781 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel); 782 783 /* 784 * Ensure that we go out via update_sregs 785 */ 786 pcb->pcb_rupdate = 1; 787 lwptot(lwp)->t_post_sys = 1; 788 if (thisthread) 789 kpreempt_enable(); 790 #endif 791 } 792 793 /* 794 * Only certain bits of the flags register can be modified. 795 */ 796 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) | 797 (grp[REG_RFL] & PSL_USERMASK); 798 799 #elif defined(__i386) 800 801 /* 802 * Only certain bits of the flags register can be modified. 803 */ 804 grp[EFL] = (rp->r_efl & ~PSL_USERMASK) | (grp[EFL] & PSL_USERMASK); 805 806 /* 807 * Copy saved registers from user stack. 808 */ 809 bcopy(grp, &rp->r_gs, sizeof (gregset_t)); 810 811 rp->r_cs = fix_segreg(rp->r_cs, IS_CS, datamodel); 812 rp->r_ss = fix_segreg(rp->r_ss, IS_NOT_CS, datamodel); 813 rp->r_ds = fix_segreg(rp->r_ds, IS_NOT_CS, datamodel); 814 rp->r_es = fix_segreg(rp->r_es, IS_NOT_CS, datamodel); 815 rp->r_fs = fix_segreg(rp->r_fs, IS_NOT_CS, datamodel); 816 rp->r_gs = fix_segreg(rp->r_gs, IS_NOT_CS, datamodel); 817 818 #endif /* __i386 */ 819 } 820 821 /* 822 * Determine whether eip is likely to have an interrupt frame 823 * on the stack. We do this by comparing the address to the 824 * range of addresses spanned by several well-known routines. 825 */ 826 extern void _interrupt(); 827 extern void _allsyscalls(); 828 extern void _cmntrap(); 829 extern void fakesoftint(); 830 831 extern size_t _interrupt_size; 832 extern size_t _allsyscalls_size; 833 extern size_t _cmntrap_size; 834 extern size_t _fakesoftint_size; 835 836 /* 837 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking. 838 * Returns MIN(current stack depth, pcstack_limit). 839 */ 840 int 841 getpcstack(pc_t *pcstack, int pcstack_limit) 842 { 843 struct frame *fp = (struct frame *)getfp(); 844 struct frame *nextfp, *minfp, *stacktop; 845 int depth = 0; 846 int on_intr; 847 uintptr_t pc; 848 849 if ((on_intr = CPU_ON_INTR(CPU)) != 0) 850 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); 851 else 852 stacktop = (struct frame *)curthread->t_stk; 853 minfp = fp; 854 855 pc = ((struct regs *)fp)->r_pc; 856 857 while (depth < pcstack_limit) { 858 nextfp = (struct frame *)fp->fr_savfp; 859 pc = fp->fr_savpc; 860 if (nextfp <= minfp || nextfp >= stacktop) { 861 if (on_intr) { 862 /* 863 * Hop from interrupt stack to thread stack. 864 */ 865 stacktop = (struct frame *)curthread->t_stk; 866 minfp = (struct frame *)curthread->t_stkbase; 867 on_intr = 0; 868 continue; 869 } 870 break; 871 } 872 pcstack[depth++] = (pc_t)pc; 873 fp = nextfp; 874 minfp = fp; 875 } 876 return (depth); 877 } 878 879 /* 880 * The following ELF header fields are defined as processor-specific 881 * in the V8 ABI: 882 * 883 * e_ident[EI_DATA] encoding of the processor-specific 884 * data in the object file 885 * e_machine processor identification 886 * e_flags processor-specific flags associated 887 * with the file 888 */ 889 890 /* 891 * The value of at_flags reflects a platform's cpu module support. 892 * at_flags is used to check for allowing a binary to execute and 893 * is passed as the value of the AT_FLAGS auxiliary vector. 894 */ 895 int at_flags = 0; 896 897 /* 898 * Check the processor-specific fields of an ELF header. 899 * 900 * returns 1 if the fields are valid, 0 otherwise 901 */ 902 /*ARGSUSED2*/ 903 int 904 elfheadcheck( 905 unsigned char e_data, 906 Elf32_Half e_machine, 907 Elf32_Word e_flags) 908 { 909 if (e_data != ELFDATA2LSB) 910 return (0); 911 #if defined(__amd64) 912 if (e_machine == EM_AMD64) 913 return (1); 914 #endif 915 return (e_machine == EM_386); 916 } 917 918 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */ 919 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */ 920 #if defined(_SYSCALL32_IMPL) 921 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */ 922 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */ 923 #endif 924 925 /* 926 * Gather information about the processor and place it into auxv_hwcap 927 * so that it can be exported to the linker via the aux vector. 928 * 929 * We use this seemingly complicated mechanism so that we can ensure 930 * that /etc/system can be used to override what the system can or 931 * cannot discover for itself. 932 */ 933 void 934 bind_hwcap(void) 935 { 936 uint_t cpu_hwcap_flags = cpuid_pass4(NULL); 937 938 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags) & 939 ~auxv_hwcap_exclude; 940 941 #if defined(__amd64) 942 /* 943 * On AMD processors, sysenter just doesn't work at all 944 * when the kernel is in long mode. On IA-32e processors 945 * it does, but there's no real point in all the alternate 946 * mechanism when syscall works on both. 947 * 948 * Besides, the kernel's sysenter handler is expecting a 949 * 32-bit lwp ... 950 */ 951 auxv_hwcap &= ~AV_386_SEP; 952 #else 953 /* 954 * 32-bit processes can -always- use the lahf/sahf instructions 955 */ 956 auxv_hwcap |= AV_386_AHF; 957 #endif 958 959 if (auxv_hwcap_include || auxv_hwcap_exclude) 960 cmn_err(CE_CONT, "?user ABI extensions: %b\n", 961 auxv_hwcap, FMT_AV_386); 962 963 #if defined(_SYSCALL32_IMPL) 964 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags) & 965 ~auxv_hwcap32_exclude; 966 967 #if defined(__amd64) 968 /* 969 * If this is an amd64 architecture machine from Intel, then 970 * syscall -doesn't- work in compatibility mode, only sysenter does. 971 * 972 * Sigh. 973 */ 974 if (!cpuid_syscall32_insn(NULL)) 975 auxv_hwcap32 &= ~AV_386_AMD_SYSC; 976 977 /* 978 * 32-bit processes can -always- use the lahf/sahf instructions 979 */ 980 auxv_hwcap32 |= AV_386_AHF; 981 #endif 982 983 if (auxv_hwcap32_include || auxv_hwcap32_exclude) 984 cmn_err(CE_CONT, "?32-bit user ABI extensions: %b\n", 985 auxv_hwcap32, FMT_AV_386); 986 #endif 987 } 988 989 /* 990 * sync_icache() - this is called 991 * in proc/fs/prusrio.c. x86 has an unified cache and therefore 992 * this is a nop. 993 */ 994 /* ARGSUSED */ 995 void 996 sync_icache(caddr_t addr, uint_t len) 997 { 998 /* Do nothing for now */ 999 } 1000 1001 /*ARGSUSED*/ 1002 void 1003 sync_data_memory(caddr_t va, size_t len) 1004 { 1005 /* Not implemented for this platform */ 1006 } 1007 1008 int 1009 __ipltospl(int ipl) 1010 { 1011 return (ipltospl(ipl)); 1012 } 1013 1014 /* 1015 * The panic code invokes panic_saveregs() to record the contents of a 1016 * regs structure into the specified panic_data structure for debuggers. 1017 */ 1018 void 1019 panic_saveregs(panic_data_t *pdp, struct regs *rp) 1020 { 1021 panic_nv_t *pnv = PANICNVGET(pdp); 1022 1023 struct cregs creg; 1024 1025 getcregs(&creg); 1026 1027 #if defined(__amd64) 1028 PANICNVADD(pnv, "rdi", rp->r_rdi); 1029 PANICNVADD(pnv, "rsi", rp->r_rsi); 1030 PANICNVADD(pnv, "rdx", rp->r_rdx); 1031 PANICNVADD(pnv, "rcx", rp->r_rcx); 1032 PANICNVADD(pnv, "r8", rp->r_r8); 1033 PANICNVADD(pnv, "r9", rp->r_r9); 1034 PANICNVADD(pnv, "rax", rp->r_rax); 1035 PANICNVADD(pnv, "rbx", rp->r_rbx); 1036 PANICNVADD(pnv, "rbp", rp->r_rbp); 1037 PANICNVADD(pnv, "r10", rp->r_r10); 1038 PANICNVADD(pnv, "r10", rp->r_r10); 1039 PANICNVADD(pnv, "r11", rp->r_r11); 1040 PANICNVADD(pnv, "r12", rp->r_r12); 1041 PANICNVADD(pnv, "r13", rp->r_r13); 1042 PANICNVADD(pnv, "r14", rp->r_r14); 1043 PANICNVADD(pnv, "r15", rp->r_r15); 1044 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE)); 1045 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE)); 1046 PANICNVADD(pnv, "ds", rp->r_ds); 1047 PANICNVADD(pnv, "es", rp->r_es); 1048 PANICNVADD(pnv, "fs", rp->r_fs); 1049 PANICNVADD(pnv, "gs", rp->r_gs); 1050 PANICNVADD(pnv, "trapno", rp->r_trapno); 1051 PANICNVADD(pnv, "err", rp->r_err); 1052 PANICNVADD(pnv, "rip", rp->r_rip); 1053 PANICNVADD(pnv, "cs", rp->r_cs); 1054 PANICNVADD(pnv, "rflags", rp->r_rfl); 1055 PANICNVADD(pnv, "rsp", rp->r_rsp); 1056 PANICNVADD(pnv, "ss", rp->r_ss); 1057 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3])); 1058 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0])); 1059 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3])); 1060 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0])); 1061 #elif defined(__i386) 1062 PANICNVADD(pnv, "gs", (uint32_t)rp->r_gs); 1063 PANICNVADD(pnv, "fs", (uint32_t)rp->r_fs); 1064 PANICNVADD(pnv, "es", (uint32_t)rp->r_es); 1065 PANICNVADD(pnv, "ds", (uint32_t)rp->r_ds); 1066 PANICNVADD(pnv, "edi", (uint32_t)rp->r_edi); 1067 PANICNVADD(pnv, "esi", (uint32_t)rp->r_esi); 1068 PANICNVADD(pnv, "ebp", (uint32_t)rp->r_ebp); 1069 PANICNVADD(pnv, "esp", (uint32_t)rp->r_esp); 1070 PANICNVADD(pnv, "ebx", (uint32_t)rp->r_ebx); 1071 PANICNVADD(pnv, "edx", (uint32_t)rp->r_edx); 1072 PANICNVADD(pnv, "ecx", (uint32_t)rp->r_ecx); 1073 PANICNVADD(pnv, "eax", (uint32_t)rp->r_eax); 1074 PANICNVADD(pnv, "trapno", (uint32_t)rp->r_trapno); 1075 PANICNVADD(pnv, "err", (uint32_t)rp->r_err); 1076 PANICNVADD(pnv, "eip", (uint32_t)rp->r_eip); 1077 PANICNVADD(pnv, "cs", (uint32_t)rp->r_cs); 1078 PANICNVADD(pnv, "eflags", (uint32_t)rp->r_efl); 1079 PANICNVADD(pnv, "uesp", (uint32_t)rp->r_uesp); 1080 PANICNVADD(pnv, "ss", (uint32_t)rp->r_ss); 1081 PANICNVADD(pnv, "gdt", creg.cr_gdt); 1082 PANICNVADD(pnv, "idt", creg.cr_idt); 1083 #endif /* __i386 */ 1084 1085 PANICNVADD(pnv, "ldt", creg.cr_ldt); 1086 PANICNVADD(pnv, "task", creg.cr_task); 1087 PANICNVADD(pnv, "cr0", creg.cr_cr0); 1088 PANICNVADD(pnv, "cr2", creg.cr_cr2); 1089 PANICNVADD(pnv, "cr3", creg.cr_cr3); 1090 if (creg.cr_cr4) 1091 PANICNVADD(pnv, "cr4", creg.cr_cr4); 1092 1093 PANICNVSET(pdp, pnv); 1094 } 1095 1096 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */ 1097 1098 #if !defined(__amd64) 1099 1100 /* 1101 * Given a return address (%eip), determine the likely number of arguments 1102 * that were pushed on the stack prior to its execution. We do this by 1103 * expecting that a typical call sequence consists of pushing arguments on 1104 * the stack, executing a call instruction, and then performing an add 1105 * on %esp to restore it to the value prior to pushing the arguments for 1106 * the call. We attempt to detect such an add, and divide the addend 1107 * by the size of a word to determine the number of pushed arguments. 1108 * 1109 * If we do not find such an add, we punt and return TR_ARG_MAX. It is not 1110 * possible to reliably determine if a function took no arguments (i.e. was 1111 * void) because assembler routines do not reliably perform an add on %esp 1112 * immediately upon returning (eg. _sys_call()), so returning TR_ARG_MAX is 1113 * safer than returning 0. 1114 */ 1115 static ulong_t 1116 argcount(uintptr_t eip) 1117 { 1118 const uint8_t *ins = (const uint8_t *)eip; 1119 ulong_t n; 1120 1121 enum { 1122 M_MODRM_ESP = 0xc4, /* Mod/RM byte indicates %esp */ 1123 M_ADD_IMM32 = 0x81, /* ADD imm32 to r/m32 */ 1124 M_ADD_IMM8 = 0x83 /* ADD imm8 to r/m32 */ 1125 }; 1126 1127 if (eip < KERNELBASE || ins[1] != M_MODRM_ESP) 1128 return (TR_ARG_MAX); 1129 1130 switch (ins[0]) { 1131 case M_ADD_IMM32: 1132 n = ins[2] + (ins[3] << 8) + (ins[4] << 16) + (ins[5] << 24); 1133 break; 1134 1135 case M_ADD_IMM8: 1136 n = ins[2]; 1137 break; 1138 1139 default: 1140 return (TR_ARG_MAX); 1141 } 1142 1143 n /= sizeof (long); 1144 return (MIN(n, TR_ARG_MAX)); 1145 } 1146 1147 #endif /* !__amd64 */ 1148 1149 /* 1150 * Print a stack backtrace using the specified frame pointer. We delay two 1151 * seconds before continuing, unless this is the panic traceback. Note 1152 * that the frame for the starting stack pointer value is omitted because 1153 * the corresponding %eip is not known. 1154 */ 1155 #if defined(__amd64) 1156 1157 void 1158 traceback(caddr_t fpreg) 1159 { 1160 struct frame *fp = (struct frame *)fpreg; 1161 struct frame *nextfp; 1162 uintptr_t pc, nextpc; 1163 ulong_t off; 1164 char args[TR_ARG_MAX * 2 + 16], *sym; 1165 1166 if (!panicstr) 1167 printf("traceback: %%fp = %p\n", (void *)fp); 1168 1169 fp = (struct frame *)plat_traceback(fpreg); 1170 if ((uintptr_t)fp < KERNELBASE) 1171 goto out; 1172 1173 pc = fp->fr_savpc; 1174 fp = (struct frame *)fp->fr_savfp; 1175 1176 while ((uintptr_t)fp >= KERNELBASE) { 1177 /* 1178 * XX64 Until port is complete tolerate 8-byte aligned 1179 * frame pointers but flag with a warning so they can 1180 * be fixed. 1181 */ 1182 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) { 1183 if (((uintptr_t)fp & (8 - 1)) == 0) { 1184 printf(" >> warning! 8-byte" 1185 " aligned %%fp = %p\n", (void *)fp); 1186 } else { 1187 printf( 1188 " >> mis-aligned %%fp = %p\n", (void *)fp); 1189 break; 1190 } 1191 } 1192 1193 args[0] = '\0'; 1194 nextpc = (uintptr_t)fp->fr_savpc; 1195 nextfp = (struct frame *)fp->fr_savfp; 1196 if ((sym = kobj_getsymname(pc, &off)) != NULL) { 1197 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp, 1198 mod_containing_pc((caddr_t)pc), sym, off, args); 1199 } else { 1200 printf("%016lx %lx (%s)\n", 1201 (uintptr_t)fp, pc, args); 1202 } 1203 1204 pc = nextpc; 1205 fp = nextfp; 1206 } 1207 out: 1208 if (!panicstr) { 1209 printf("end of traceback\n"); 1210 DELAY(2 * MICROSEC); 1211 } 1212 } 1213 1214 #elif defined(__i386) 1215 1216 void 1217 traceback(caddr_t fpreg) 1218 { 1219 struct frame *fp = (struct frame *)fpreg; 1220 struct frame *nextfp, *minfp, *stacktop; 1221 uintptr_t pc, nextpc; 1222 1223 cpu_t *cpu; 1224 1225 /* 1226 * args[] holds TR_ARG_MAX hex long args, plus ", " or '\0'. 1227 */ 1228 char args[TR_ARG_MAX * 2 + 8], *p; 1229 1230 int on_intr; 1231 ulong_t off; 1232 char *sym; 1233 1234 if (!panicstr) 1235 printf("traceback: %%fp = %p\n", (void *)fp); 1236 1237 /* 1238 * If we are panicking, all high-level interrupt information in 1239 * CPU was overwritten. panic_cpu has the correct values. 1240 */ 1241 kpreempt_disable(); /* prevent migration */ 1242 1243 cpu = (panicstr && CPU->cpu_id == panic_cpu.cpu_id)? &panic_cpu : CPU; 1244 1245 if ((on_intr = CPU_ON_INTR(cpu)) != 0) 1246 stacktop = (struct frame *)(cpu->cpu_intr_stack + SA(MINFRAME)); 1247 else 1248 stacktop = (struct frame *)curthread->t_stk; 1249 1250 kpreempt_enable(); 1251 1252 fp = (struct frame *)plat_traceback(fpreg); 1253 if ((uintptr_t)fp < KERNELBASE) 1254 goto out; 1255 1256 minfp = fp; /* Baseline minimum frame pointer */ 1257 pc = fp->fr_savpc; 1258 fp = (struct frame *)fp->fr_savfp; 1259 1260 while ((uintptr_t)fp >= KERNELBASE) { 1261 ulong_t argc; 1262 long *argv; 1263 1264 if (fp <= minfp || fp >= stacktop) { 1265 if (on_intr) { 1266 /* 1267 * Hop from interrupt stack to thread stack. 1268 */ 1269 stacktop = (struct frame *)curthread->t_stk; 1270 minfp = (struct frame *)curthread->t_stkbase; 1271 on_intr = 0; 1272 continue; 1273 } 1274 break; /* we're outside of the expected range */ 1275 } 1276 1277 if ((uintptr_t)fp & (STACK_ALIGN - 1)) { 1278 printf(" >> mis-aligned %%fp = %p\n", (void *)fp); 1279 break; 1280 } 1281 1282 nextpc = fp->fr_savpc; 1283 nextfp = (struct frame *)fp->fr_savfp; 1284 argc = argcount(nextpc); 1285 argv = (long *)((char *)fp + sizeof (struct frame)); 1286 1287 args[0] = '\0'; 1288 p = args; 1289 while (argc-- > 0 && argv < (long *)stacktop) { 1290 p += snprintf(p, args + sizeof (args) - p, 1291 "%s%lx", (p == args) ? "" : ", ", *argv++); 1292 } 1293 1294 if ((sym = kobj_getsymname(pc, &off)) != NULL) { 1295 printf("%08lx %s:%s+%lx (%s)\n", (uintptr_t)fp, 1296 mod_containing_pc((caddr_t)pc), sym, off, args); 1297 } else { 1298 printf("%08lx %lx (%s)\n", 1299 (uintptr_t)fp, pc, args); 1300 } 1301 1302 minfp = fp; 1303 pc = nextpc; 1304 fp = nextfp; 1305 } 1306 out: 1307 if (!panicstr) { 1308 printf("end of traceback\n"); 1309 DELAY(2 * MICROSEC); 1310 } 1311 } 1312 1313 #endif /* __i386 */ 1314 1315 /* 1316 * Generate a stack backtrace from a saved register set. 1317 */ 1318 void 1319 traceregs(struct regs *rp) 1320 { 1321 traceback((caddr_t)rp->r_fp); 1322 } 1323 1324 void 1325 exec_set_sp(size_t stksize) 1326 { 1327 klwp_t *lwp = ttolwp(curthread); 1328 1329 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize; 1330 } 1331 1332 hrtime_t 1333 gethrtime_waitfree(void) 1334 { 1335 return (dtrace_gethrtime()); 1336 } 1337 1338 hrtime_t 1339 gethrtime(void) 1340 { 1341 return (gethrtimef()); 1342 } 1343 1344 hrtime_t 1345 gethrtime_unscaled(void) 1346 { 1347 return (gethrtimeunscaledf()); 1348 } 1349 1350 void 1351 scalehrtime(hrtime_t *hrt) 1352 { 1353 scalehrtimef(hrt); 1354 } 1355 1356 void 1357 gethrestime(timespec_t *tp) 1358 { 1359 gethrestimef(tp); 1360 } 1361 1362 #if defined(__amd64) 1363 /* 1364 * Part of the implementation of hres_tick(); this routine is 1365 * easier in C than assembler .. called with the hres_lock held. 1366 * 1367 * XX64 Many of these timekeeping variables need to be extern'ed in a header 1368 */ 1369 1370 #include <sys/time.h> 1371 #include <sys/machlock.h> 1372 1373 extern int one_sec; 1374 extern int max_hres_adj; 1375 1376 void 1377 __adj_hrestime(void) 1378 { 1379 long long adj; 1380 1381 if (hrestime_adj == 0) 1382 adj = 0; 1383 else if (hrestime_adj > 0) { 1384 if (hrestime_adj < max_hres_adj) 1385 adj = hrestime_adj; 1386 else 1387 adj = max_hres_adj; 1388 } else { 1389 if (hrestime_adj < -max_hres_adj) 1390 adj = -max_hres_adj; 1391 else 1392 adj = hrestime_adj; 1393 } 1394 1395 timedelta -= adj; 1396 hrestime_adj = timedelta; 1397 hrestime.tv_nsec += adj; 1398 1399 while (hrestime.tv_nsec >= NANOSEC) { 1400 one_sec++; 1401 hrestime.tv_sec++; 1402 hrestime.tv_nsec -= NANOSEC; 1403 } 1404 } 1405 #endif 1406 1407 /* 1408 * Wrapper functions to maintain backwards compability 1409 */ 1410 int 1411 xcopyin(const void *uaddr, void *kaddr, size_t count) 1412 { 1413 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED)); 1414 } 1415 1416 int 1417 xcopyout(const void *kaddr, void *uaddr, size_t count) 1418 { 1419 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED)); 1420 } 1421