1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/fasttrap_isa.h> 30 #include <sys/fasttrap_impl.h> 31 #include <sys/dtrace.h> 32 #include <sys/dtrace_impl.h> 33 #include <sys/cmn_err.h> 34 #include <sys/regset.h> 35 #include <sys/privregs.h> 36 #include <sys/segments.h> 37 #include <sys/sysmacros.h> 38 #include <sys/trap.h> 39 #include <sys/archsystm.h> 40 41 /* 42 * Lossless User-Land Tracing on x86 43 * --------------------------------- 44 * 45 * The execution of most instructions is not dependent on the address; for 46 * these instructions it is sufficient to copy them into the user process's 47 * address space and execute them. To effectively single-step an instruction 48 * in user-land, we copy out the following sequence of instructions to scratch 49 * space in the user thread's ulwp_t structure. 50 * 51 * We then set the program counter (%eip or %rip) to point to this scratch 52 * space. Once execution resumes, the original instruction is executed and 53 * then control flow is redirected to what was originally the subsequent 54 * instruction. If the kernel attemps to deliver a signal while single- 55 * stepping, the signal is deferred and the program counter is moved into the 56 * second sequence of instructions. The second sequence ends in a trap into 57 * the kernel where the deferred signal is then properly handled and delivered. 58 * 59 * For instructions whose execute is position dependent, we perform simple 60 * emulation. These instructions are limited to control transfer 61 * instructions in 32-bit mode, but in 64-bit mode there's the added wrinkle 62 * of %rip-relative addressing that means that almost any instruction can be 63 * position dependent. For all the details on how we emulate generic 64 * instructions included %rip-relative instructions, see the code in 65 * fasttrap_pid_probe() below where we handle instructions of type 66 * FASTTRAP_T_COMMON (under the header: Generic Instruction Tracing). 67 */ 68 69 #define FASTTRAP_MODRM_MOD(modrm) (((modrm) >> 6) & 0x3) 70 #define FASTTRAP_MODRM_REG(modrm) (((modrm) >> 3) & 0x7) 71 #define FASTTRAP_MODRM_RM(modrm) ((modrm) & 0x7) 72 #define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm)) 73 74 #define FASTTRAP_SIB_SCALE(sib) (((sib) >> 6) & 0x3) 75 #define FASTTRAP_SIB_INDEX(sib) (((sib) >> 3) & 0x7) 76 #define FASTTRAP_SIB_BASE(sib) ((sib) & 0x7) 77 78 #define FASTTRAP_REX_W(rex) (((rex) >> 3) & 1) 79 #define FASTTRAP_REX_R(rex) (((rex) >> 2) & 1) 80 #define FASTTRAP_REX_X(rex) (((rex) >> 1) & 1) 81 #define FASTTRAP_REX_B(rex) ((rex) & 1) 82 #define FASTTRAP_REX(w, r, x, b) \ 83 (0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | (b)) 84 85 /* 86 * Single-byte op-codes. 87 */ 88 #define FASTTRAP_PUSHL_EBP 0x55 89 90 #define FASTTRAP_JO 0x70 91 #define FASTTRAP_JNO 0x71 92 #define FASTTRAP_JB 0x72 93 #define FASTTRAP_JAE 0x73 94 #define FASTTRAP_JE 0x74 95 #define FASTTRAP_JNE 0x75 96 #define FASTTRAP_JBE 0x76 97 #define FASTTRAP_JA 0x77 98 #define FASTTRAP_JS 0x78 99 #define FASTTRAP_JNS 0x79 100 #define FASTTRAP_JP 0x7a 101 #define FASTTRAP_JNP 0x7b 102 #define FASTTRAP_JL 0x7c 103 #define FASTTRAP_JGE 0x7d 104 #define FASTTRAP_JLE 0x7e 105 #define FASTTRAP_JG 0x7f 106 107 #define FASTTRAP_NOP 0x90 108 109 #define FASTTRAP_MOV_EAX 0xb8 110 #define FASTTRAP_MOV_ECX 0xb9 111 112 #define FASTTRAP_RET16 0xc2 113 #define FASTTRAP_RET 0xc3 114 115 #define FASTTRAP_LOOPNZ 0xe0 116 #define FASTTRAP_LOOPZ 0xe1 117 #define FASTTRAP_LOOP 0xe2 118 #define FASTTRAP_JCXZ 0xe3 119 120 #define FASTTRAP_CALL 0xe8 121 #define FASTTRAP_JMP32 0xe9 122 #define FASTTRAP_JMP8 0xeb 123 124 #define FASTTRAP_INT3 0xcc 125 #define FASTTRAP_INT 0xcd 126 127 #define FASTTRAP_2_BYTE_OP 0x0f 128 #define FASTTRAP_GROUP5_OP 0xff 129 130 /* 131 * Two-byte op-codes (second byte only). 132 */ 133 #define FASTTRAP_0F_JO 0x80 134 #define FASTTRAP_0F_JNO 0x81 135 #define FASTTRAP_0F_JB 0x82 136 #define FASTTRAP_0F_JAE 0x83 137 #define FASTTRAP_0F_JE 0x84 138 #define FASTTRAP_0F_JNE 0x85 139 #define FASTTRAP_0F_JBE 0x86 140 #define FASTTRAP_0F_JA 0x87 141 #define FASTTRAP_0F_JS 0x88 142 #define FASTTRAP_0F_JNS 0x89 143 #define FASTTRAP_0F_JP 0x8a 144 #define FASTTRAP_0F_JNP 0x8b 145 #define FASTTRAP_0F_JL 0x8c 146 #define FASTTRAP_0F_JGE 0x8d 147 #define FASTTRAP_0F_JLE 0x8e 148 #define FASTTRAP_0F_JG 0x8f 149 150 #define FASTTRAP_EFLAGS_OF 0x800 151 #define FASTTRAP_EFLAGS_DF 0x400 152 #define FASTTRAP_EFLAGS_SF 0x080 153 #define FASTTRAP_EFLAGS_ZF 0x040 154 #define FASTTRAP_EFLAGS_AF 0x010 155 #define FASTTRAP_EFLAGS_PF 0x004 156 #define FASTTRAP_EFLAGS_CF 0x001 157 158 /* 159 * Instruction prefixes. 160 */ 161 #define FASTTRAP_PREFIX_OPERAND 0x66 162 #define FASTTRAP_PREFIX_ADDRESS 0x67 163 #define FASTTRAP_PREFIX_CS 0x2E 164 #define FASTTRAP_PREFIX_DS 0x3E 165 #define FASTTRAP_PREFIX_ES 0x26 166 #define FASTTRAP_PREFIX_FS 0x64 167 #define FASTTRAP_PREFIX_GS 0x65 168 #define FASTTRAP_PREFIX_SS 0x36 169 #define FASTTRAP_PREFIX_LOCK 0xF0 170 #define FASTTRAP_PREFIX_REP 0xF3 171 #define FASTTRAP_PREFIX_REPNE 0xF2 172 173 #define FASTTRAP_NOREG 0xff 174 175 /* 176 * Map between instruction register encodings and the kernel constants which 177 * correspond to indicies into struct regs. 178 */ 179 #ifdef __amd64 180 static const uint8_t regmap[16] = { 181 REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, 182 REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, 183 }; 184 #else 185 static const uint8_t regmap[8] = { 186 EAX, ECX, EDX, EBX, UESP, EBP, ESI, EDI 187 }; 188 #endif 189 190 static ulong_t fasttrap_getreg(struct regs *, uint_t); 191 192 static uint64_t 193 fasttrap_anarg(struct regs *rp, int function_entry, int argno) 194 { 195 uint64_t value; 196 int shift = function_entry ? 1 : 0; 197 198 #ifdef __amd64 199 if (curproc->p_model == DATAMODEL_LP64) { 200 uintptr_t *stack; 201 202 /* 203 * In 64-bit mode, the first six arguments are stored in 204 * registers. 205 */ 206 if (argno < 6) 207 return ((&rp->r_rdi)[argno]); 208 209 stack = (uintptr_t *)rp->r_sp; 210 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 211 value = dtrace_fulword(&stack[argno - 6 + shift]); 212 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 213 } else { 214 #endif 215 uint32_t *stack = (uint32_t *)rp->r_sp; 216 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 217 value = dtrace_fuword32(&stack[argno + shift]); 218 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 219 #ifdef __amd64 220 } 221 #endif 222 223 return (value); 224 } 225 226 /*ARGSUSED*/ 227 int 228 fasttrap_tracepoint_init(proc_t *p, fasttrap_tracepoint_t *tp, uintptr_t pc, 229 fasttrap_probe_type_t type) 230 { 231 uint8_t instr[FASTTRAP_MAX_INSTR_SIZE + 10]; 232 size_t len = FASTTRAP_MAX_INSTR_SIZE; 233 size_t first = MIN(len, PAGESIZE - (pc & PAGEOFFSET)); 234 uint_t start = 0; 235 int rmindex, size; 236 uint8_t seg, rex = 0; 237 238 /* 239 * Read the instruction at the given address out of the process's 240 * address space. We don't have to worry about a debugger 241 * changing this instruction before we overwrite it with our trap 242 * instruction since P_PR_LOCK is set. Since instructions can span 243 * pages, we potentially read the instruction in two parts. If the 244 * second part fails, we just zero out that part of the instruction. 245 */ 246 if (uread(p, &instr[0], first, pc) != 0) 247 return (-1); 248 if (len > first && 249 uread(p, &instr[first], len - first, pc + first) != 0) { 250 bzero(&instr[first], len - first); 251 len = first; 252 } 253 254 /* 255 * If the disassembly fails, then we have a malformed instruction. 256 */ 257 if ((size = dtrace_instr_size_isa(instr, p->p_model, &rmindex)) <= 0) 258 return (-1); 259 260 /* 261 * Make sure the disassembler isn't completely broken. 262 */ 263 ASSERT(-1 <= rmindex && rmindex < size); 264 265 /* 266 * If the computed size is greater than the number of bytes read, 267 * then it was a malformed instruction possibly because it fell on a 268 * page boundary and the subsequent page was missing or because of 269 * some malicious user. 270 */ 271 if (size > len) 272 return (-1); 273 274 tp->ftt_size = (uint8_t)size; 275 tp->ftt_segment = FASTTRAP_SEG_NONE; 276 277 /* 278 * Find the start of the instruction's opcode by processing any 279 * legacy prefixes. 280 */ 281 for (;;) { 282 seg = 0; 283 switch (instr[start]) { 284 case FASTTRAP_PREFIX_SS: 285 seg++; 286 /*FALLTHRU*/ 287 case FASTTRAP_PREFIX_GS: 288 seg++; 289 /*FALLTHRU*/ 290 case FASTTRAP_PREFIX_FS: 291 seg++; 292 /*FALLTHRU*/ 293 case FASTTRAP_PREFIX_ES: 294 seg++; 295 /*FALLTHRU*/ 296 case FASTTRAP_PREFIX_DS: 297 seg++; 298 /*FALLTHRU*/ 299 case FASTTRAP_PREFIX_CS: 300 seg++; 301 /*FALLTHRU*/ 302 case FASTTRAP_PREFIX_OPERAND: 303 case FASTTRAP_PREFIX_ADDRESS: 304 case FASTTRAP_PREFIX_LOCK: 305 case FASTTRAP_PREFIX_REP: 306 case FASTTRAP_PREFIX_REPNE: 307 if (seg != 0) { 308 /* 309 * It's illegal for an instruction to specify 310 * two segment prefixes -- give up on this 311 * illegal instruction. 312 */ 313 if (tp->ftt_segment != FASTTRAP_SEG_NONE) 314 return (-1); 315 316 tp->ftt_segment = seg; 317 } 318 start++; 319 continue; 320 } 321 break; 322 } 323 324 #ifdef __amd64 325 /* 326 * Identify the REX prefix on 64-bit processes. 327 */ 328 if (p->p_model == DATAMODEL_LP64 && (instr[start] & 0xf0) == 0x40) 329 rex = instr[start++]; 330 #endif 331 332 /* 333 * Now that we're pretty sure that the instruction is okay, copy the 334 * valid part to the tracepoint. 335 */ 336 bcopy(instr, tp->ftt_instr, FASTTRAP_MAX_INSTR_SIZE); 337 338 tp->ftt_type = FASTTRAP_T_COMMON; 339 if (instr[start] == FASTTRAP_2_BYTE_OP) { 340 switch (instr[start + 1]) { 341 case FASTTRAP_0F_JO: 342 case FASTTRAP_0F_JNO: 343 case FASTTRAP_0F_JB: 344 case FASTTRAP_0F_JAE: 345 case FASTTRAP_0F_JE: 346 case FASTTRAP_0F_JNE: 347 case FASTTRAP_0F_JBE: 348 case FASTTRAP_0F_JA: 349 case FASTTRAP_0F_JS: 350 case FASTTRAP_0F_JNS: 351 case FASTTRAP_0F_JP: 352 case FASTTRAP_0F_JNP: 353 case FASTTRAP_0F_JL: 354 case FASTTRAP_0F_JGE: 355 case FASTTRAP_0F_JLE: 356 case FASTTRAP_0F_JG: 357 tp->ftt_type = FASTTRAP_T_JCC; 358 tp->ftt_code = (instr[start + 1] & 0x0f) | FASTTRAP_JO; 359 tp->ftt_dest = pc + tp->ftt_size + 360 *(int32_t *)&instr[start + 2]; 361 break; 362 } 363 } else if (instr[start] == FASTTRAP_GROUP5_OP) { 364 uint_t mod = FASTTRAP_MODRM_MOD(instr[start + 1]); 365 uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]); 366 uint_t rm = FASTTRAP_MODRM_RM(instr[start + 1]); 367 368 if (reg == 2 || reg == 4) { 369 uint_t i, sz; 370 371 if (reg == 2) 372 tp->ftt_type = FASTTRAP_T_CALL; 373 else 374 tp->ftt_type = FASTTRAP_T_JMP; 375 376 if (mod == 3) 377 tp->ftt_code = 2; 378 else 379 tp->ftt_code = 1; 380 381 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 382 383 /* 384 * See AMD x86-64 Architecture Programmer's Manual 385 * Volume 3, Section 1.2.7, Table 1-12, and 386 * Appendix A.3.1, Table A-15. 387 */ 388 if (mod != 3 && rm == 4) { 389 uint8_t sib = instr[start + 2]; 390 uint_t index = FASTTRAP_SIB_INDEX(sib); 391 uint_t base = FASTTRAP_SIB_BASE(sib); 392 393 tp->ftt_scale = FASTTRAP_SIB_SCALE(sib); 394 395 tp->ftt_index = (index == 4) ? 396 FASTTRAP_NOREG : 397 regmap[index | (FASTTRAP_REX_X(rex) << 3)]; 398 tp->ftt_base = (mod == 0 && base == 5) ? 399 FASTTRAP_NOREG : 400 regmap[base | (FASTTRAP_REX_B(rex) << 3)]; 401 402 i = 3; 403 sz = mod == 1 ? 1 : 4; 404 } else { 405 /* 406 * In 64-bit mode, mod == 0 and r/m == 5 407 * denotes %rip-relative addressing; in 32-bit 408 * mode, the base register isn't used. In both 409 * modes, there is a 32-bit operand. 410 */ 411 if (mod == 0 && rm == 5) { 412 #ifdef __amd64 413 if (p->p_model == DATAMODEL_LP64) 414 tp->ftt_base = REG_RIP; 415 else 416 #endif 417 tp->ftt_base = FASTTRAP_NOREG; 418 sz = 4; 419 } else { 420 uint8_t base = rm | 421 (FASTTRAP_REX_B(rex) << 3); 422 423 tp->ftt_base = regmap[base]; 424 sz = mod == 1 ? 1 : mod == 2 ? 4 : 0; 425 } 426 tp->ftt_index = FASTTRAP_NOREG; 427 i = 2; 428 } 429 430 if (sz == 1) 431 tp->ftt_dest = *(int8_t *)&instr[start + i]; 432 else if (sz == 4) 433 tp->ftt_dest = *(int32_t *)&instr[start + i]; 434 else 435 tp->ftt_dest = 0; 436 } 437 } else { 438 switch (instr[start]) { 439 case FASTTRAP_RET: 440 tp->ftt_type = FASTTRAP_T_RET; 441 break; 442 443 case FASTTRAP_RET16: 444 tp->ftt_type = FASTTRAP_T_RET16; 445 tp->ftt_dest = *(uint16_t *)&instr[start + 1]; 446 break; 447 448 case FASTTRAP_JO: 449 case FASTTRAP_JNO: 450 case FASTTRAP_JB: 451 case FASTTRAP_JAE: 452 case FASTTRAP_JE: 453 case FASTTRAP_JNE: 454 case FASTTRAP_JBE: 455 case FASTTRAP_JA: 456 case FASTTRAP_JS: 457 case FASTTRAP_JNS: 458 case FASTTRAP_JP: 459 case FASTTRAP_JNP: 460 case FASTTRAP_JL: 461 case FASTTRAP_JGE: 462 case FASTTRAP_JLE: 463 case FASTTRAP_JG: 464 tp->ftt_type = FASTTRAP_T_JCC; 465 tp->ftt_code = instr[start]; 466 tp->ftt_dest = pc + tp->ftt_size + 467 (int8_t)instr[start + 1]; 468 break; 469 470 case FASTTRAP_LOOPNZ: 471 case FASTTRAP_LOOPZ: 472 case FASTTRAP_LOOP: 473 tp->ftt_type = FASTTRAP_T_LOOP; 474 tp->ftt_code = instr[start]; 475 tp->ftt_dest = pc + tp->ftt_size + 476 (int8_t)instr[start + 1]; 477 break; 478 479 case FASTTRAP_JCXZ: 480 tp->ftt_type = FASTTRAP_T_JCXZ; 481 tp->ftt_dest = pc + tp->ftt_size + 482 (int8_t)instr[start + 1]; 483 break; 484 485 case FASTTRAP_CALL: 486 tp->ftt_type = FASTTRAP_T_CALL; 487 tp->ftt_dest = pc + tp->ftt_size + 488 *(int32_t *)&instr[start + 1]; 489 tp->ftt_code = 0; 490 break; 491 492 case FASTTRAP_JMP32: 493 tp->ftt_type = FASTTRAP_T_JMP; 494 tp->ftt_dest = pc + tp->ftt_size + 495 *(int32_t *)&instr[start + 1]; 496 break; 497 case FASTTRAP_JMP8: 498 tp->ftt_type = FASTTRAP_T_JMP; 499 tp->ftt_dest = pc + tp->ftt_size + 500 (int8_t)instr[start + 1]; 501 break; 502 503 case FASTTRAP_PUSHL_EBP: 504 if (start == 0) 505 tp->ftt_type = FASTTRAP_T_PUSHL_EBP; 506 break; 507 508 case FASTTRAP_NOP: 509 #ifdef __amd64 510 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 511 512 /* 513 * On amd64 we have to be careful not to confuse a nop 514 * (actually xchgl %eax, %eax) with an instruction using 515 * the same opcode, but that does something different 516 * (e.g. xchgl %r8d, %eax or xcghq %r8, %rax). 517 */ 518 if (FASTTRAP_REX_B(rex) == 0) 519 #endif 520 tp->ftt_type = FASTTRAP_T_NOP; 521 break; 522 523 case FASTTRAP_INT3: 524 /* 525 * The pid provider shares the int3 trap with debugger 526 * breakpoints so we can't instrument them. 527 */ 528 ASSERT(instr[start] == FASTTRAP_INSTR); 529 return (-1); 530 531 case FASTTRAP_INT: 532 /* 533 * Interrupts seem like they could be traced with 534 * no negative implications, but it's possible that 535 * a thread could be redirected by the trap handling 536 * code which would eventually return to the 537 * instruction after the interrupt. If the interrupt 538 * were in our scratch space, the subsequent 539 * instruction might be overwritten before we return. 540 * Accordingly we refuse to instrument any interrupt. 541 */ 542 return (-1); 543 } 544 } 545 546 #ifdef __amd64 547 if (p->p_model == DATAMODEL_LP64 && tp->ftt_type == FASTTRAP_T_COMMON) { 548 /* 549 * If the process is 64-bit and the instruction type is still 550 * FASTTRAP_T_COMMON -- meaning we're going to copy it out an 551 * execute it -- we need to watch for %rip-relative 552 * addressing mode. See the portion of fasttrap_pid_probe() 553 * below where we handle tracepoints with type 554 * FASTTRAP_T_COMMON for how we emulate instructions that 555 * employ %rip-relative addressing. 556 */ 557 if (rmindex != -1) { 558 uint_t mod = FASTTRAP_MODRM_MOD(instr[rmindex]); 559 uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]); 560 uint_t rm = FASTTRAP_MODRM_RM(instr[rmindex]); 561 562 ASSERT(rmindex > start); 563 564 if (mod == 0 && rm == 5) { 565 /* 566 * We need to be sure to avoid other 567 * registers used by this instruction. While 568 * the reg field may determine the op code 569 * rather than denoting a register, assuming 570 * that it denotes a register is always safe. 571 * We leave the REX field intact and use 572 * whatever value's there for simplicity. 573 */ 574 if (reg != 0) { 575 tp->ftt_ripmode = FASTTRAP_RIP_1 | 576 (FASTTRAP_RIP_X * 577 FASTTRAP_REX_B(rex)); 578 rm = 0; 579 } else { 580 tp->ftt_ripmode = FASTTRAP_RIP_2 | 581 (FASTTRAP_RIP_X * 582 FASTTRAP_REX_B(rex)); 583 rm = 1; 584 } 585 586 tp->ftt_modrm = tp->ftt_instr[rmindex]; 587 tp->ftt_instr[rmindex] = 588 FASTTRAP_MODRM(2, reg, rm); 589 } 590 } 591 } 592 #endif 593 594 return (0); 595 } 596 597 int 598 fasttrap_tracepoint_install(proc_t *p, fasttrap_tracepoint_t *tp) 599 { 600 fasttrap_instr_t instr = FASTTRAP_INSTR; 601 602 if (uwrite(p, &instr, 1, tp->ftt_pc) != 0) 603 return (-1); 604 605 return (0); 606 } 607 608 int 609 fasttrap_tracepoint_remove(proc_t *p, fasttrap_tracepoint_t *tp) 610 { 611 uint8_t instr; 612 613 /* 614 * Distinguish between read or write failures and a changed 615 * instruction. 616 */ 617 if (uread(p, &instr, 1, tp->ftt_pc) != 0) 618 return (0); 619 if (instr != FASTTRAP_INSTR) 620 return (0); 621 if (uwrite(p, &tp->ftt_instr[0], 1, tp->ftt_pc) != 0) 622 return (-1); 623 624 return (0); 625 } 626 627 static uintptr_t 628 fasttrap_fulword_noerr(const void *uaddr) 629 { 630 uintptr_t ret; 631 632 if (fasttrap_fulword(uaddr, &ret) == 0) 633 return (ret); 634 635 return (0); 636 } 637 638 static uint32_t 639 fasttrap_fuword32_noerr(const void *uaddr) 640 { 641 uint32_t ret; 642 643 if (fasttrap_fuword32(uaddr, &ret) == 0) 644 return (ret); 645 646 return (0); 647 } 648 649 static void 650 fasttrap_return_common(struct regs *rp, uintptr_t pc, pid_t pid, 651 uintptr_t new_pc) 652 { 653 fasttrap_tracepoint_t *tp; 654 fasttrap_bucket_t *bucket; 655 fasttrap_id_t *id; 656 kmutex_t *pid_mtx; 657 658 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 659 mutex_enter(pid_mtx); 660 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 661 662 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 663 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 664 !tp->ftt_proc->ftpc_defunct) 665 break; 666 } 667 668 /* 669 * Don't sweat it if we can't find the tracepoint again; unlike 670 * when we're in fasttrap_pid_probe(), finding the tracepoint here 671 * is not essential to the correct execution of the process. 672 */ 673 if (tp == NULL) { 674 mutex_exit(pid_mtx); 675 return; 676 } 677 678 for (id = tp->ftt_retids; id != NULL; id = id->fti_next) { 679 /* 680 * If there's a branch that could act as a return site, we 681 * need to trace it, and check here if the program counter is 682 * external to the function. 683 */ 684 if (tp->ftt_type != FASTTRAP_T_RET && 685 tp->ftt_type != FASTTRAP_T_RET16 && 686 new_pc - id->fti_probe->ftp_faddr < 687 id->fti_probe->ftp_fsize) 688 continue; 689 690 dtrace_probe(id->fti_probe->ftp_id, 691 pc - id->fti_probe->ftp_faddr, 692 rp->r_r0, rp->r_r1, 0, 0); 693 } 694 695 mutex_exit(pid_mtx); 696 } 697 698 static void 699 fasttrap_sigsegv(proc_t *p, kthread_t *t, uintptr_t addr) 700 { 701 sigqueue_t *sqp = kmem_zalloc(sizeof (sigqueue_t), KM_SLEEP); 702 703 sqp->sq_info.si_signo = SIGSEGV; 704 sqp->sq_info.si_code = SEGV_MAPERR; 705 sqp->sq_info.si_addr = (caddr_t)addr; 706 707 mutex_enter(&p->p_lock); 708 sigaddqa(p, t, sqp); 709 mutex_exit(&p->p_lock); 710 711 if (t != NULL) 712 aston(t); 713 } 714 715 #ifdef __amd64 716 static void 717 fasttrap_usdt_args64(fasttrap_probe_t *probe, struct regs *rp, int argc, 718 uintptr_t *argv) 719 { 720 int i, x, cap = MIN(argc, probe->ftp_nargs); 721 uintptr_t *stack = (uintptr_t *)rp->r_sp; 722 723 for (i = 0; i < cap; i++) { 724 x = probe->ftp_argmap[i]; 725 726 if (x < 6) 727 argv[i] = (&rp->r_rdi)[x]; 728 else 729 argv[i] = fasttrap_fulword_noerr(&stack[x]); 730 } 731 732 for (; i < argc; i++) { 733 argv[i] = 0; 734 } 735 } 736 #endif 737 738 static void 739 fasttrap_usdt_args32(fasttrap_probe_t *probe, struct regs *rp, int argc, 740 uint32_t *argv) 741 { 742 int i, x, cap = MIN(argc, probe->ftp_nargs); 743 uint32_t *stack = (uint32_t *)rp->r_sp; 744 745 for (i = 0; i < cap; i++) { 746 x = probe->ftp_argmap[i]; 747 748 argv[i] = fasttrap_fuword32_noerr(&stack[x]); 749 } 750 751 for (; i < argc; i++) { 752 argv[i] = 0; 753 } 754 } 755 756 static int 757 fasttrap_do_seg(fasttrap_tracepoint_t *tp, struct regs *rp, uintptr_t *addr) 758 { 759 proc_t *p = curproc; 760 user_desc_t *desc; 761 uint16_t sel, ndx, type; 762 uintptr_t limit; 763 764 switch (tp->ftt_segment) { 765 case FASTTRAP_SEG_CS: 766 sel = rp->r_cs; 767 break; 768 case FASTTRAP_SEG_DS: 769 sel = rp->r_ds; 770 break; 771 case FASTTRAP_SEG_ES: 772 sel = rp->r_es; 773 break; 774 case FASTTRAP_SEG_FS: 775 sel = rp->r_fs; 776 break; 777 case FASTTRAP_SEG_GS: 778 sel = rp->r_gs; 779 break; 780 case FASTTRAP_SEG_SS: 781 sel = rp->r_ss; 782 break; 783 } 784 785 /* 786 * Make sure the given segment register specifies a user priority 787 * selector rather than a kernel selector. 788 */ 789 if (!SELISUPL(sel)) 790 return (-1); 791 792 ndx = SELTOIDX(sel); 793 794 /* 795 * Check the bounds and grab the descriptor out of the specified 796 * descriptor table. 797 */ 798 if (SELISLDT(sel)) { 799 if (ndx > p->p_ldtlimit) 800 return (-1); 801 802 desc = p->p_ldt + ndx; 803 804 } else { 805 if (ndx >= NGDT) 806 return (-1); 807 808 desc = cpu_get_gdt() + ndx; 809 } 810 811 /* 812 * The descriptor must have user privilege level and it must be 813 * present in memory. 814 */ 815 if (desc->usd_dpl != SEL_UPL || desc->usd_p != 1) 816 return (-1); 817 818 type = desc->usd_type; 819 820 /* 821 * If the S bit in the type field is not set, this descriptor can 822 * only be used in system context. 823 */ 824 if ((type & 0x10) != 0x10) 825 return (-1); 826 827 limit = USEGD_GETLIMIT(desc) * (desc->usd_gran ? PAGESIZE : 1); 828 829 if (tp->ftt_segment == FASTTRAP_SEG_CS) { 830 /* 831 * The code/data bit and readable bit must both be set. 832 */ 833 if ((type & 0xa) != 0xa) 834 return (-1); 835 836 if (*addr > limit) 837 return (-1); 838 } else { 839 /* 840 * The code/data bit must be clear. 841 */ 842 if ((type & 0x8) != 0) 843 return (-1); 844 845 /* 846 * If the expand-down bit is clear, we just check the limit as 847 * it would naturally be applied. Otherwise, we need to check 848 * that the address is the range [limit + 1 .. 0xffff] or 849 * [limit + 1 ... 0xffffffff] depending on if the default 850 * operand size bit is set. 851 */ 852 if ((type & 0x4) == 0) { 853 if (*addr > limit) 854 return (-1); 855 } else if (desc->usd_def32) { 856 if (*addr < limit + 1 || 0xffff < *addr) 857 return (-1); 858 } else { 859 if (*addr < limit + 1 || 0xffffffff < *addr) 860 return (-1); 861 } 862 } 863 864 *addr += USEGD_GETBASE(desc); 865 866 return (0); 867 } 868 869 int 870 fasttrap_pid_probe(struct regs *rp) 871 { 872 proc_t *p = curproc; 873 uintptr_t pc = rp->r_pc - 1, new_pc = 0; 874 fasttrap_bucket_t *bucket; 875 kmutex_t *pid_mtx; 876 fasttrap_tracepoint_t *tp, tp_local; 877 pid_t pid; 878 dtrace_icookie_t cookie; 879 uint_t is_enabled = 0; 880 881 /* 882 * It's possible that a user (in a veritable orgy of bad planning) 883 * could redirect this thread's flow of control before it reached the 884 * return probe fasttrap. In this case we need to kill the process 885 * since it's in a unrecoverable state. 886 */ 887 if (curthread->t_dtrace_step) { 888 ASSERT(curthread->t_dtrace_on); 889 fasttrap_sigtrap(p, curthread, pc); 890 return (0); 891 } 892 893 /* 894 * Clear all user tracing flags. 895 */ 896 curthread->t_dtrace_ft = 0; 897 curthread->t_dtrace_pc = 0; 898 curthread->t_dtrace_npc = 0; 899 curthread->t_dtrace_scrpc = 0; 900 curthread->t_dtrace_astpc = 0; 901 #ifdef __amd64 902 curthread->t_dtrace_regv = 0; 903 #endif 904 905 /* 906 * Treat a child created by a call to vfork(2) as if it were its 907 * parent. We know that there's only one thread of control in such a 908 * process: this one. 909 */ 910 while (p->p_flag & SVFORK) { 911 p = p->p_parent; 912 } 913 914 pid = p->p_pid; 915 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 916 mutex_enter(pid_mtx); 917 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 918 919 /* 920 * Lookup the tracepoint that the process just hit. 921 */ 922 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 923 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 924 !tp->ftt_proc->ftpc_defunct) 925 break; 926 } 927 928 /* 929 * If we couldn't find a matching tracepoint, either a tracepoint has 930 * been inserted without using the pid<pid> ioctl interface (see 931 * fasttrap_ioctl), or somehow we have mislaid this tracepoint. 932 */ 933 if (tp == NULL) { 934 mutex_exit(pid_mtx); 935 return (-1); 936 } 937 938 /* 939 * Set the program counter to the address of the traced instruction 940 * so that it looks right in ustack() output. 941 */ 942 rp->r_pc = pc; 943 944 if (tp->ftt_ids != NULL) { 945 fasttrap_id_t *id; 946 947 #ifdef __amd64 948 if (p->p_model == DATAMODEL_LP64) { 949 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 950 fasttrap_probe_t *probe = id->fti_probe; 951 952 if (id->fti_ptype == DTFTP_ENTRY) { 953 /* 954 * We note that this was an entry 955 * probe to help ustack() find the 956 * first caller. 957 */ 958 cookie = dtrace_interrupt_disable(); 959 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 960 dtrace_probe(probe->ftp_id, rp->r_rdi, 961 rp->r_rsi, rp->r_rdx, rp->r_rcx, 962 rp->r_r8); 963 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 964 dtrace_interrupt_enable(cookie); 965 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 966 /* 967 * Note that in this case, we don't 968 * call dtrace_probe() since it's only 969 * an artificial probe meant to change 970 * the flow of control so that it 971 * encounters the true probe. 972 */ 973 is_enabled = 1; 974 } else if (probe->ftp_argmap == NULL) { 975 dtrace_probe(probe->ftp_id, rp->r_rdi, 976 rp->r_rsi, rp->r_rdx, rp->r_rcx, 977 rp->r_r8); 978 } else { 979 uintptr_t t[5]; 980 981 fasttrap_usdt_args64(probe, rp, 982 sizeof (t) / sizeof (t[0]), t); 983 984 dtrace_probe(probe->ftp_id, t[0], t[1], 985 t[2], t[3], t[4]); 986 } 987 } 988 } else { 989 #endif 990 uintptr_t s0, s1, s2, s3, s4, s5; 991 uint32_t *stack = (uint32_t *)rp->r_sp; 992 993 /* 994 * In 32-bit mode, all arguments are passed on the 995 * stack. If this is a function entry probe, we need 996 * to skip the first entry on the stack as it 997 * represents the return address rather than a 998 * parameter to the function. 999 */ 1000 s0 = fasttrap_fuword32_noerr(&stack[0]); 1001 s1 = fasttrap_fuword32_noerr(&stack[1]); 1002 s2 = fasttrap_fuword32_noerr(&stack[2]); 1003 s3 = fasttrap_fuword32_noerr(&stack[3]); 1004 s4 = fasttrap_fuword32_noerr(&stack[4]); 1005 s5 = fasttrap_fuword32_noerr(&stack[5]); 1006 1007 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1008 fasttrap_probe_t *probe = id->fti_probe; 1009 1010 if (id->fti_ptype == DTFTP_ENTRY) { 1011 /* 1012 * We note that this was an entry 1013 * probe to help ustack() find the 1014 * first caller. 1015 */ 1016 cookie = dtrace_interrupt_disable(); 1017 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1018 dtrace_probe(probe->ftp_id, s1, s2, 1019 s3, s4, s5); 1020 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1021 dtrace_interrupt_enable(cookie); 1022 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1023 /* 1024 * Note that in this case, we don't 1025 * call dtrace_probe() since it's only 1026 * an artificial probe meant to change 1027 * the flow of control so that it 1028 * encounters the true probe. 1029 */ 1030 is_enabled = 1; 1031 } else if (probe->ftp_argmap == NULL) { 1032 dtrace_probe(probe->ftp_id, s0, s1, 1033 s2, s3, s4); 1034 } else { 1035 uint32_t t[5]; 1036 1037 fasttrap_usdt_args32(probe, rp, 1038 sizeof (t) / sizeof (t[0]), t); 1039 1040 dtrace_probe(probe->ftp_id, t[0], t[1], 1041 t[2], t[3], t[4]); 1042 } 1043 } 1044 #ifdef __amd64 1045 } 1046 #endif 1047 } 1048 1049 /* 1050 * We're about to do a bunch of work so we cache a local copy of 1051 * the tracepoint to emulate the instruction, and then find the 1052 * tracepoint again later if we need to light up any return probes. 1053 */ 1054 tp_local = *tp; 1055 mutex_exit(pid_mtx); 1056 tp = &tp_local; 1057 1058 /* 1059 * Set the program counter to appear as though the traced instruction 1060 * had completely executed. This ensures that fasttrap_getreg() will 1061 * report the expected value for REG_RIP. 1062 */ 1063 rp->r_pc = pc + tp->ftt_size; 1064 1065 /* 1066 * If there's an is-enabled probe connected to this tracepoint it 1067 * means that there was a 'xorl %eax, %eax' or 'xorq %rax, %rax' 1068 * instruction that was placed there by DTrace when the binary was 1069 * linked. As this probe is, in fact, enabled, we need to stuff 1 1070 * into %eax or %rax. Accordingly, we can bypass all the instruction 1071 * emulation logic since we know the inevitable result. It's possible 1072 * that a user could construct a scenario where the 'is-enabled' 1073 * probe was on some other instruction, but that would be a rather 1074 * exotic way to shoot oneself in the foot. 1075 */ 1076 if (is_enabled) { 1077 rp->r_r0 = 1; 1078 new_pc = rp->r_pc; 1079 goto done; 1080 } 1081 1082 /* 1083 * We emulate certain types of instructions to ensure correctness 1084 * (in the case of position dependent instructions) or optimize 1085 * common cases. The rest we have the thread execute back in user- 1086 * land. 1087 */ 1088 switch (tp->ftt_type) { 1089 case FASTTRAP_T_RET: 1090 case FASTTRAP_T_RET16: 1091 { 1092 uintptr_t dst; 1093 uintptr_t addr; 1094 int ret; 1095 1096 /* 1097 * We have to emulate _every_ facet of the behavior of a ret 1098 * instruction including what happens if the load from %esp 1099 * fails; in that case, we send a SIGSEGV. 1100 */ 1101 #ifdef __amd64 1102 if (p->p_model == DATAMODEL_NATIVE) { 1103 #endif 1104 ret = fasttrap_fulword((void *)rp->r_sp, &dst); 1105 addr = rp->r_sp + sizeof (uintptr_t); 1106 #ifdef __amd64 1107 } else { 1108 uint32_t dst32; 1109 ret = fasttrap_fuword32((void *)rp->r_sp, &dst32); 1110 dst = dst32; 1111 addr = rp->r_sp + sizeof (uint32_t); 1112 } 1113 #endif 1114 1115 if (ret == -1) { 1116 fasttrap_sigsegv(p, curthread, rp->r_sp); 1117 new_pc = pc; 1118 break; 1119 } 1120 1121 if (tp->ftt_type == FASTTRAP_T_RET16) 1122 addr += tp->ftt_dest; 1123 1124 rp->r_sp = addr; 1125 new_pc = dst; 1126 break; 1127 } 1128 1129 case FASTTRAP_T_JCC: 1130 { 1131 uint_t taken; 1132 1133 switch (tp->ftt_code) { 1134 case FASTTRAP_JO: 1135 taken = (rp->r_ps & FASTTRAP_EFLAGS_OF) != 0; 1136 break; 1137 case FASTTRAP_JNO: 1138 taken = (rp->r_ps & FASTTRAP_EFLAGS_OF) == 0; 1139 break; 1140 case FASTTRAP_JB: 1141 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) != 0; 1142 break; 1143 case FASTTRAP_JAE: 1144 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) == 0; 1145 break; 1146 case FASTTRAP_JE: 1147 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0; 1148 break; 1149 case FASTTRAP_JNE: 1150 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0; 1151 break; 1152 case FASTTRAP_JBE: 1153 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) != 0 || 1154 (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0; 1155 break; 1156 case FASTTRAP_JA: 1157 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) == 0 && 1158 (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0; 1159 break; 1160 case FASTTRAP_JS: 1161 taken = (rp->r_ps & FASTTRAP_EFLAGS_SF) != 0; 1162 break; 1163 case FASTTRAP_JNS: 1164 taken = (rp->r_ps & FASTTRAP_EFLAGS_SF) == 0; 1165 break; 1166 case FASTTRAP_JP: 1167 taken = (rp->r_ps & FASTTRAP_EFLAGS_PF) != 0; 1168 break; 1169 case FASTTRAP_JNP: 1170 taken = (rp->r_ps & FASTTRAP_EFLAGS_PF) == 0; 1171 break; 1172 case FASTTRAP_JL: 1173 taken = ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) != 1174 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1175 break; 1176 case FASTTRAP_JGE: 1177 taken = ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) == 1178 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1179 break; 1180 case FASTTRAP_JLE: 1181 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0 || 1182 ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) != 1183 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1184 break; 1185 case FASTTRAP_JG: 1186 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0 && 1187 ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) == 1188 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1189 break; 1190 1191 } 1192 1193 if (taken) 1194 new_pc = tp->ftt_dest; 1195 else 1196 new_pc = pc + tp->ftt_size; 1197 break; 1198 } 1199 1200 case FASTTRAP_T_LOOP: 1201 { 1202 uint_t taken; 1203 #ifdef __amd64 1204 greg_t cx = rp->r_rcx--; 1205 #else 1206 greg_t cx = rp->r_ecx--; 1207 #endif 1208 1209 switch (tp->ftt_code) { 1210 case FASTTRAP_LOOPNZ: 1211 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0 && 1212 cx != 0; 1213 break; 1214 case FASTTRAP_LOOPZ: 1215 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0 && 1216 cx != 0; 1217 break; 1218 case FASTTRAP_LOOP: 1219 taken = (cx != 0); 1220 break; 1221 } 1222 1223 if (taken) 1224 new_pc = tp->ftt_dest; 1225 else 1226 new_pc = pc + tp->ftt_size; 1227 break; 1228 } 1229 1230 case FASTTRAP_T_JCXZ: 1231 { 1232 #ifdef __amd64 1233 greg_t cx = rp->r_rcx; 1234 #else 1235 greg_t cx = rp->r_ecx; 1236 #endif 1237 1238 if (cx == 0) 1239 new_pc = tp->ftt_dest; 1240 else 1241 new_pc = pc + tp->ftt_size; 1242 break; 1243 } 1244 1245 case FASTTRAP_T_PUSHL_EBP: 1246 { 1247 int ret; 1248 uintptr_t addr; 1249 #ifdef __amd64 1250 if (p->p_model == DATAMODEL_NATIVE) { 1251 #endif 1252 addr = rp->r_sp - sizeof (uintptr_t); 1253 ret = fasttrap_sulword((void *)addr, rp->r_fp); 1254 #ifdef __amd64 1255 } else { 1256 addr = rp->r_sp - sizeof (uint32_t); 1257 ret = fasttrap_suword32((void *)addr, 1258 (uint32_t)rp->r_fp); 1259 } 1260 #endif 1261 1262 if (ret == -1) { 1263 fasttrap_sigsegv(p, curthread, addr); 1264 new_pc = pc; 1265 break; 1266 } 1267 1268 rp->r_sp = addr; 1269 new_pc = pc + tp->ftt_size; 1270 break; 1271 } 1272 1273 case FASTTRAP_T_NOP: 1274 new_pc = pc + tp->ftt_size; 1275 break; 1276 1277 case FASTTRAP_T_JMP: 1278 case FASTTRAP_T_CALL: 1279 if (tp->ftt_code == 0) { 1280 new_pc = tp->ftt_dest; 1281 } else { 1282 uintptr_t value, addr = tp->ftt_dest; 1283 1284 if (tp->ftt_base != FASTTRAP_NOREG) 1285 addr += fasttrap_getreg(rp, tp->ftt_base); 1286 if (tp->ftt_index != FASTTRAP_NOREG) 1287 addr += fasttrap_getreg(rp, tp->ftt_index) << 1288 tp->ftt_scale; 1289 1290 if (tp->ftt_code == 1) { 1291 /* 1292 * If there's a segment prefix for this 1293 * instruction, we'll need to check permissions 1294 * and bounds on the given selector, and adjust 1295 * the address accordingly. 1296 */ 1297 if (tp->ftt_segment != FASTTRAP_SEG_NONE && 1298 fasttrap_do_seg(tp, rp, &addr) != 0) { 1299 fasttrap_sigsegv(p, curthread, addr); 1300 new_pc = pc; 1301 break; 1302 } 1303 1304 #ifdef __amd64 1305 if (p->p_model == DATAMODEL_NATIVE) { 1306 #endif 1307 if (fasttrap_fulword((void *)addr, 1308 &value) == -1) { 1309 fasttrap_sigsegv(p, curthread, 1310 addr); 1311 new_pc = pc; 1312 break; 1313 } 1314 new_pc = value; 1315 #ifdef __amd64 1316 } else { 1317 uint32_t value32; 1318 addr = (uintptr_t)(uint32_t)addr; 1319 if (fasttrap_fuword32((void *)addr, 1320 &value32) == -1) { 1321 fasttrap_sigsegv(p, curthread, 1322 addr); 1323 new_pc = pc; 1324 break; 1325 } 1326 new_pc = value32; 1327 } 1328 #endif 1329 } else { 1330 new_pc = addr; 1331 } 1332 } 1333 1334 /* 1335 * If this is a call instruction, we need to push the return 1336 * address onto the stack. If this fails, we send the process 1337 * a SIGSEGV and reset the pc to emulate what would happen if 1338 * this instruction weren't traced. 1339 */ 1340 if (tp->ftt_type == FASTTRAP_T_CALL) { 1341 int ret; 1342 uintptr_t addr; 1343 #ifdef __amd64 1344 if (p->p_model == DATAMODEL_NATIVE) { 1345 addr = rp->r_sp - sizeof (uintptr_t); 1346 ret = fasttrap_sulword((void *)addr, 1347 pc + tp->ftt_size); 1348 } else { 1349 #endif 1350 addr = rp->r_sp - sizeof (uint32_t); 1351 ret = fasttrap_suword32((void *)addr, 1352 (uint32_t)(pc + tp->ftt_size)); 1353 #ifdef __amd64 1354 } 1355 #endif 1356 1357 if (ret == -1) { 1358 fasttrap_sigsegv(p, curthread, addr); 1359 new_pc = pc; 1360 break; 1361 } 1362 1363 rp->r_sp = addr; 1364 } 1365 1366 break; 1367 1368 case FASTTRAP_T_COMMON: 1369 { 1370 uintptr_t addr; 1371 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 5 + 2]; 1372 uint_t i = 0; 1373 klwp_t *lwp = ttolwp(curthread); 1374 1375 /* 1376 * Compute the address of the ulwp_t and step over the 1377 * ul_self pointer. The method used to store the user-land 1378 * thread pointer is very different on 32- and 64-bit 1379 * kernels. 1380 */ 1381 #if defined(__amd64) 1382 if (p->p_model == DATAMODEL_LP64) { 1383 addr = lwp->lwp_pcb.pcb_fsbase; 1384 addr += sizeof (void *); 1385 } else { 1386 addr = lwp->lwp_pcb.pcb_gsbase; 1387 addr += sizeof (caddr32_t); 1388 } 1389 #elif defined(__i386) 1390 addr = USEGD_GETBASE(&lwp->lwp_pcb.pcb_gsdesc); 1391 addr += sizeof (void *); 1392 #endif 1393 1394 /* 1395 * Generic Instruction Tracing 1396 * --------------------------- 1397 * 1398 * This is the layout of the scratch space in the user-land 1399 * thread structure for our generated instructions. 1400 * 1401 * 32-bit mode bytes 1402 * ------------------------ ----- 1403 * a: <original instruction> <= 15 1404 * jmp <pc + tp->ftt_size> 5 1405 * b: <original instrction> <= 15 1406 * int T_DTRACE_RET 2 1407 * ----- 1408 * <= 37 1409 * 1410 * 64-bit mode bytes 1411 * ------------------------ ----- 1412 * a: <original instruction> <= 15 1413 * jmp 0(%rip) 6 1414 * <pc + tp->ftt_size> 8 1415 * b: <original instruction> <= 15 1416 * int T_DTRACE_RET 2 1417 * ----- 1418 * <= 46 1419 * 1420 * The %pc is set to a, and curthread->t_dtrace_astpc is set 1421 * to b. If we encounter a signal on the way out of the 1422 * kernel, trap() will set %pc to curthread->t_dtrace_astpc 1423 * so that we execute the original instruction and re-enter 1424 * the kernel rather than redirecting to the next instruction. 1425 * 1426 * If there are return probes (so we know that we're going to 1427 * need to reenter the kernel after executing the original 1428 * instruction), the scratch space will just contain the 1429 * original instruction followed by an interrupt -- the same 1430 * data as at b. 1431 * 1432 * %rip-relative Addressing 1433 * ------------------------ 1434 * 1435 * There's a further complication in 64-bit mode due to %rip- 1436 * relative addressing. While this is clearly a beneficial 1437 * architectural decision for position independent code, it's 1438 * hard not to see it as a personal attack against the pid 1439 * provider since before there was a relatively small set of 1440 * instructions to emulate; with %rip-relative addressing, 1441 * almost every instruction can potentially depend on the 1442 * address at which it's executed. Rather than emulating 1443 * the broad spectrum of instructions that can now be 1444 * position dependent, we emulate jumps and others as in 1445 * 32-bit mode, and take a different tack for instructions 1446 * using %rip-relative addressing. 1447 * 1448 * For every instruction that uses the ModRM byte, the 1449 * in-kernel disassembler reports its location. We use the 1450 * ModRM byte to identify that an instruction uses 1451 * %rip-relative addressing and to see what other registers 1452 * the instruction uses. To emulate those instructions, 1453 * we modify the instruction to be %rax-relative rather than 1454 * %rip-relative (or %rcx-relative if the instruction uses 1455 * %rax; or %r8- or %r9-relative if the REX.B is present so 1456 * we don't have to rewrite the REX prefix). We then load 1457 * the value that %rip would have been into the scratch 1458 * register and generate an instruction to reset the scratch 1459 * register back to its original value. The instruction 1460 * sequence looks like this: 1461 * 1462 * 64-mode %rip-relative bytes 1463 * ------------------------ ----- 1464 * a: <modified instruction> <= 15 1465 * movq $<value>, %<scratch> 6 1466 * jmp 0(%rip) 6 1467 * <pc + tp->ftt_size> 8 1468 * b: <modified instruction> <= 15 1469 * int T_DTRACE_RET 2 1470 * ----- 1471 * 52 1472 * 1473 * We set curthread->t_dtrace_regv so that upon receiving 1474 * a signal we can reset the value of the scratch register. 1475 */ 1476 1477 ASSERT(tp->ftt_size < FASTTRAP_MAX_INSTR_SIZE); 1478 1479 curthread->t_dtrace_scrpc = addr; 1480 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1481 i += tp->ftt_size; 1482 1483 #ifdef __amd64 1484 if (tp->ftt_ripmode != 0) { 1485 greg_t *reg; 1486 1487 ASSERT(p->p_model == DATAMODEL_LP64); 1488 ASSERT(tp->ftt_ripmode & 1489 (FASTTRAP_RIP_1 | FASTTRAP_RIP_2)); 1490 1491 /* 1492 * If this was a %rip-relative instruction, we change 1493 * it to be either a %rax- or %rcx-relative 1494 * instruction (depending on whether those registers 1495 * are used as another operand; or %r8- or %r9- 1496 * relative depending on the value of REX.B). We then 1497 * set that register and generate a movq instruction 1498 * to reset the value. 1499 */ 1500 if (tp->ftt_ripmode & FASTTRAP_RIP_X) 1501 scratch[i++] = FASTTRAP_REX(1, 0, 0, 1); 1502 else 1503 scratch[i++] = FASTTRAP_REX(1, 0, 0, 0); 1504 1505 if (tp->ftt_ripmode & FASTTRAP_RIP_1) 1506 scratch[i++] = FASTTRAP_MOV_EAX; 1507 else 1508 scratch[i++] = FASTTRAP_MOV_ECX; 1509 1510 switch (tp->ftt_ripmode) { 1511 case FASTTRAP_RIP_1: 1512 reg = &rp->r_rax; 1513 curthread->t_dtrace_reg = REG_RAX; 1514 break; 1515 case FASTTRAP_RIP_2: 1516 reg = &rp->r_rcx; 1517 curthread->t_dtrace_reg = REG_RCX; 1518 break; 1519 case FASTTRAP_RIP_1 | FASTTRAP_RIP_X: 1520 reg = &rp->r_r8; 1521 curthread->t_dtrace_reg = REG_R8; 1522 break; 1523 case FASTTRAP_RIP_2 | FASTTRAP_RIP_X: 1524 reg = &rp->r_r9; 1525 curthread->t_dtrace_reg = REG_R9; 1526 break; 1527 } 1528 1529 *(uint64_t *)&scratch[i] = *reg; 1530 curthread->t_dtrace_regv = *reg; 1531 *reg = pc + tp->ftt_size; 1532 i += sizeof (uint64_t); 1533 } 1534 #endif 1535 1536 /* 1537 * Generate the branch instruction to what would have 1538 * normally been the subsequent instruction. In 32-bit mode, 1539 * this is just a relative branch; in 64-bit mode this is a 1540 * %rip-relative branch that loads the 64-bit pc value 1541 * immediately after the jmp instruction. 1542 */ 1543 #ifdef __amd64 1544 if (p->p_model == DATAMODEL_LP64) { 1545 scratch[i++] = FASTTRAP_GROUP5_OP; 1546 scratch[i++] = FASTTRAP_MODRM(0, 4, 5); 1547 *(uint32_t *)&scratch[i] = 0; 1548 i += sizeof (uint32_t); 1549 *(uint64_t *)&scratch[i] = pc + tp->ftt_size; 1550 i += sizeof (uint64_t); 1551 } else { 1552 #endif 1553 /* 1554 * Set up the jmp to the next instruction; note that 1555 * the size of the traced instruction cancels out. 1556 */ 1557 scratch[i++] = FASTTRAP_JMP32; 1558 *(uint32_t *)&scratch[i] = pc - addr - 5; 1559 i += sizeof (uint32_t); 1560 #ifdef __amd64 1561 } 1562 #endif 1563 1564 curthread->t_dtrace_astpc = addr + i; 1565 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1566 i += tp->ftt_size; 1567 scratch[i++] = FASTTRAP_INT; 1568 scratch[i++] = T_DTRACE_RET; 1569 1570 if (fasttrap_copyout(scratch, (char *)addr, i)) { 1571 fasttrap_sigtrap(p, curthread, pc); 1572 new_pc = pc; 1573 break; 1574 } 1575 1576 if (tp->ftt_retids != NULL) { 1577 curthread->t_dtrace_step = 1; 1578 curthread->t_dtrace_ret = 1; 1579 new_pc = curthread->t_dtrace_astpc; 1580 } else { 1581 new_pc = curthread->t_dtrace_scrpc; 1582 } 1583 1584 curthread->t_dtrace_pc = pc; 1585 curthread->t_dtrace_npc = pc + tp->ftt_size; 1586 curthread->t_dtrace_on = 1; 1587 break; 1588 } 1589 1590 default: 1591 panic("fasttrap: mishandled an instruction"); 1592 } 1593 1594 done: 1595 /* 1596 * If there were no return probes when we first found the tracepoint, 1597 * we should feel no obligation to honor any return probes that were 1598 * subsequently enabled -- they'll just have to wait until the next 1599 * time around. 1600 */ 1601 if (tp->ftt_retids != NULL) { 1602 /* 1603 * We need to wait until the results of the instruction are 1604 * apparent before invoking any return probes. If this 1605 * instruction was emulated we can just call 1606 * fasttrap_return_common(); if it needs to be executed, we 1607 * need to wait until the user thread returns to the kernel. 1608 */ 1609 if (tp->ftt_type != FASTTRAP_T_COMMON) { 1610 /* 1611 * Set the program counter to the address of the traced 1612 * instruction so that it looks right in ustack() 1613 * output. We had previously set it to the end of the 1614 * instruction to simplify %rip-relative addressing. 1615 */ 1616 rp->r_pc = pc; 1617 1618 fasttrap_return_common(rp, pc, pid, new_pc); 1619 } else { 1620 ASSERT(curthread->t_dtrace_ret != 0); 1621 ASSERT(curthread->t_dtrace_pc == pc); 1622 ASSERT(curthread->t_dtrace_scrpc != 0); 1623 ASSERT(new_pc == curthread->t_dtrace_astpc); 1624 } 1625 } 1626 1627 rp->r_pc = new_pc; 1628 1629 return (0); 1630 } 1631 1632 int 1633 fasttrap_return_probe(struct regs *rp) 1634 { 1635 proc_t *p = curproc; 1636 uintptr_t pc = curthread->t_dtrace_pc; 1637 uintptr_t npc = curthread->t_dtrace_npc; 1638 1639 curthread->t_dtrace_pc = 0; 1640 curthread->t_dtrace_npc = 0; 1641 curthread->t_dtrace_scrpc = 0; 1642 curthread->t_dtrace_astpc = 0; 1643 1644 /* 1645 * Treat a child created by a call to vfork(2) as if it were its 1646 * parent. We know that there's only one thread of control in such a 1647 * process: this one. 1648 */ 1649 while (p->p_flag & SVFORK) { 1650 p = p->p_parent; 1651 } 1652 1653 /* 1654 * We set rp->r_pc to the address of the traced instruction so 1655 * that it appears to dtrace_probe() that we're on the original 1656 * instruction, and so that the user can't easily detect our 1657 * complex web of lies. dtrace_return_probe() (our caller) 1658 * will correctly set %pc after we return. 1659 */ 1660 rp->r_pc = pc; 1661 1662 fasttrap_return_common(rp, pc, p->p_pid, npc); 1663 1664 return (0); 1665 } 1666 1667 /*ARGSUSED*/ 1668 uint64_t 1669 fasttrap_pid_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1670 int aframes) 1671 { 1672 return (fasttrap_anarg(ttolwp(curthread)->lwp_regs, 1, argno)); 1673 } 1674 1675 /*ARGSUSED*/ 1676 uint64_t 1677 fasttrap_usdt_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1678 int aframes) 1679 { 1680 return (fasttrap_anarg(ttolwp(curthread)->lwp_regs, 0, argno)); 1681 } 1682 1683 static ulong_t 1684 fasttrap_getreg(struct regs *rp, uint_t reg) 1685 { 1686 #ifdef __amd64 1687 switch (reg) { 1688 case REG_R15: return (rp->r_r15); 1689 case REG_R14: return (rp->r_r14); 1690 case REG_R13: return (rp->r_r13); 1691 case REG_R12: return (rp->r_r12); 1692 case REG_R11: return (rp->r_r11); 1693 case REG_R10: return (rp->r_r10); 1694 case REG_R9: return (rp->r_r9); 1695 case REG_R8: return (rp->r_r8); 1696 case REG_RDI: return (rp->r_rdi); 1697 case REG_RSI: return (rp->r_rsi); 1698 case REG_RBP: return (rp->r_rbp); 1699 case REG_RBX: return (rp->r_rbx); 1700 case REG_RDX: return (rp->r_rdx); 1701 case REG_RCX: return (rp->r_rcx); 1702 case REG_RAX: return (rp->r_rax); 1703 case REG_TRAPNO: return (rp->r_trapno); 1704 case REG_ERR: return (rp->r_err); 1705 case REG_RIP: return (rp->r_rip); 1706 case REG_CS: return (rp->r_cs); 1707 case REG_RFL: return (rp->r_rfl); 1708 case REG_RSP: return (rp->r_rsp); 1709 case REG_SS: return (rp->r_ss); 1710 case REG_FS: return (rp->r_fs); 1711 case REG_GS: return (rp->r_gs); 1712 case REG_DS: return (rp->r_ds); 1713 case REG_ES: return (rp->r_es); 1714 case REG_FSBASE: return (rp->r_fsbase); 1715 case REG_GSBASE: return (rp->r_gsbase); 1716 } 1717 1718 panic("dtrace: illegal register constant"); 1719 /*NOTREACHED*/ 1720 #else 1721 if (reg >= _NGREG) 1722 panic("dtrace: illegal register constant"); 1723 1724 return (((greg_t *)&rp->r_gs)[reg]); 1725 #endif 1726 } 1727