xref: /titanic_41/usr/src/uts/intel/asm/cpu.h (revision cde2885fdf538266ee2a3b08dee2d5075ce8fa2b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _ASM_CPU_H
27 #define	_ASM_CPU_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #if !defined(__lint) && defined(__GNUC__)
34 
35 #if defined(__i386) || defined(__amd64)
36 
37 extern __inline__ void ht_pause(void)
38 {
39 	__asm__ __volatile__(
40 	    "pause");
41 }
42 
43 /*
44  * prefetch 64 bytes
45  *
46  * prefetch is an SSE extension which is not supported on
47  * older 32-bit processors, so define this as a no-op for now
48  */
49 
50 extern __inline__ void prefetch_read_many(void *addr)
51 {
52 #if defined(__amd64)
53 	__asm__(
54 	    "prefetcht0 (%0);"
55 	    "prefetcht0 32(%0);"
56 	    : /* no output */
57 	    : "r" (addr));
58 #endif	/* __amd64 */
59 }
60 
61 extern __inline__ void prefetch_read_once(void *addr)
62 {
63 #if defined(__amd64)
64 	__asm__(
65 	    "prefetchnta (%0);"
66 	    "prefetchnta 32(%0);"
67 	    : /* no output */
68 	    : "r" (addr));
69 #endif	/* __amd64 */
70 }
71 
72 extern __inline__ void prefetch_write_many(void *addr)
73 {
74 #if defined(__amd64)
75 	__asm__(
76 	    "prefetcht0 (%0);"
77 	    "prefetcht0 32(%0);"
78 	    : /* no output */
79 	    : "r" (addr));
80 #endif	/* __amd64 */
81 }
82 
83 extern __inline__ void prefetch_write_once(void *addr)
84 {
85 #if defined(__amd64)
86 	__asm__(
87 	    "prefetcht0 (%0);"
88 	    "prefetcht0 32(%0);"
89 	    : /* no output */
90 	    : "r" (addr));
91 #endif	/* __amd64 */
92 }
93 
94 #if !defined(__xpv)
95 
96 extern __inline__ void cli(void)
97 {
98 	__asm__ __volatile__(
99 	    "cli" : : : "memory");
100 }
101 
102 extern __inline__ void sti(void)
103 {
104 	__asm__ __volatile__(
105 	    "sti");
106 }
107 
108 extern __inline__ void i86_halt(void)
109 {
110 	__asm__ __volatile__(
111 	    "sti; hlt");
112 }
113 
114 #endif /* !__xpv */
115 
116 #endif	/* __i386 || defined(__amd64) */
117 
118 #if defined(__amd64)
119 
120 extern __inline__ void __set_ds(selector_t value)
121 {
122 	__asm__ __volatile__(
123 	    "movw	%0, %%ds"
124 	    : /* no output */
125 	    : "r" (value));
126 }
127 
128 extern __inline__ void __set_es(selector_t value)
129 {
130 	__asm__ __volatile__(
131 	    "movw	%0, %%es"
132 	    : /* no output */
133 	    : "r" (value));
134 }
135 
136 extern __inline__ void __set_fs(selector_t value)
137 {
138 	__asm__ __volatile__(
139 	    "movw	%0, %%fs"
140 	    : /* no output */
141 	    : "r" (value));
142 }
143 
144 extern __inline__ void __set_gs(selector_t value)
145 {
146 	__asm__ __volatile__(
147 	    "movw	%0, %%gs"
148 	    : /* no output */
149 	    : "r" (value));
150 }
151 
152 #if !defined(__xpv)
153 
154 extern __inline__ void __swapgs(void)
155 {
156 	__asm__ __volatile__(
157 	    "mfence; swapgs");
158 }
159 
160 #endif /* !__xpv */
161 
162 #endif	/* __amd64 */
163 
164 #endif	/* !__lint && __GNUC__ */
165 
166 #ifdef	__cplusplus
167 }
168 #endif
169 
170 #endif	/* _ASM_CPU_H */
171