xref: /titanic_41/usr/src/uts/intel/amd64/sys/privregs.h (revision bf56214c0556fa6864189c826d39dbe156bb22a0)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_AMD64_SYS_PRIVREGS_H
28 #define	_AMD64_SYS_PRIVREGS_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * This file describes the cpu's privileged register set, and
38  * how the machine state is saved on the stack when a trap occurs.
39  */
40 
41 #if !defined(__amd64)
42 #error	"non-amd64 code depends on amd64 privileged header!"
43 #endif
44 
45 #ifndef _ASM
46 
47 /*
48  * This is NOT the structure to use for general purpose debugging;
49  * see /proc for that.  This is NOT the structure to use to decode
50  * the ucontext or grovel about in a core file; see <sys/regset.h>.
51  */
52 
53 struct regs {
54 	/*
55 	 * Extra frame for mdb to follow through high level interrupts and
56 	 * system traps.  Set them to 0 to terminate stacktrace.
57 	 */
58 	greg_t	r_savfp;	/* a copy of %rbp */
59 	greg_t	r_savpc;	/* a copy of %rip */
60 
61 	greg_t	r_rdi;		/* 1st arg to function */
62 	greg_t	r_rsi;		/* 2nd arg to function */
63 	greg_t	r_rdx;		/* 3rd arg to function, 2nd return register */
64 	greg_t	r_rcx;		/* 4th arg to function */
65 
66 	greg_t	r_r8;		/* 5th arg to function */
67 	greg_t	r_r9;		/* 6th arg to function */
68 	greg_t	r_rax;		/* 1st return register, # SSE registers */
69 	greg_t	r_rbx;		/* callee-saved, optional base pointer */
70 
71 	greg_t	r_rbp;		/* callee-saved, optional frame pointer */
72 	greg_t	r_r10;		/* temporary register, static chain pointer */
73 	greg_t	r_r11;		/* temporary register */
74 	greg_t	r_r12;		/* callee-saved */
75 
76 	greg_t	r_r13;		/* callee-saved */
77 	greg_t	r_r14;		/* callee-saved */
78 	greg_t	r_r15;		/* callee-saved */
79 
80 	/*
81 	 * fsbase and gsbase are sampled on every exception in DEBUG kernels
82 	 * only.  They remain in the non-DEBUG kernel to avoid any flag days.
83 	 */
84 	greg_t	__r_fsbase;	/* no longer used in non-DEBUG builds */
85 	greg_t	__r_gsbase;	/* no longer used in non-DEBUG builds */
86 	greg_t	r_ds;
87 	greg_t	r_es;
88 	greg_t	r_fs;		/* %fs is *never* used by the kernel */
89 	greg_t	r_gs;
90 
91 	greg_t	r_trapno;
92 
93 	/*
94 	 * (the rest of these are defined by the hardware)
95 	 */
96 	greg_t	r_err;
97 	greg_t	r_rip;
98 	greg_t	r_cs;
99 	greg_t	r_rfl;
100 	greg_t	r_rsp;
101 	greg_t	r_ss;
102 };
103 
104 #define	r_r0	r_rax	/* r0 for portability */
105 #define	r_r1	r_rdx	/* r1 for portability */
106 #define	r_fp	r_rbp	/* kernel frame pointer */
107 #define	r_sp	r_rsp	/* user stack pointer */
108 #define	r_pc	r_rip	/* user's instruction pointer */
109 #define	r_ps	r_rfl	/* user's RFLAGS */
110 
111 #ifdef _KERNEL
112 #define	lwptoregs(lwp)	((struct regs *)((lwp)->lwp_regs))
113 #endif /* _KERNEL */
114 
115 #else	/* !_ASM */
116 
117 #if defined(_MACHDEP)
118 
119 #include <sys/machprivregs.h>
120 #include <sys/pcb.h>
121 
122 #ifdef DEBUG
123 #define	__SAVE_BASES				\
124 	movl    $MSR_AMD_FSBASE, %ecx;          \
125 	rdmsr;                                  \
126 	movl    %eax, REGOFF_FSBASE(%rsp);      \
127 	movl    %edx, REGOFF_FSBASE+4(%rsp);    \
128 	movl    $MSR_AMD_GSBASE, %ecx;          \
129 	rdmsr;                                  \
130 	movl    %eax, REGOFF_GSBASE(%rsp);      \
131 	movl    %edx, REGOFF_GSBASE+4(%rsp)
132 #else
133 #define	__SAVE_BASES
134 #endif
135 
136 /*
137  * Create a struct regs on the stack suitable for an
138  * interrupt trap.
139  *
140  * Assumes that the trap handler has already pushed an
141  * appropriate r_err and r_trapno
142  */
143 #define	__SAVE_REGS				\
144 	movq	%r15, REGOFF_R15(%rsp);		\
145 	movq	%r14, REGOFF_R14(%rsp);		\
146 	movq	%r13, REGOFF_R13(%rsp);		\
147 	movq	%r12, REGOFF_R12(%rsp);		\
148 	movq	%r11, REGOFF_R11(%rsp);		\
149 	movq	%r10, REGOFF_R10(%rsp);		\
150 	movq	%rbp, REGOFF_RBP(%rsp);		\
151 	movq	%rbx, REGOFF_RBX(%rsp);		\
152 	movq	%rax, REGOFF_RAX(%rsp);		\
153 	movq	%r9, REGOFF_R9(%rsp);		\
154 	movq	%r8, REGOFF_R8(%rsp);		\
155 	movq	%rcx, REGOFF_RCX(%rsp);		\
156 	movq	%rdx, REGOFF_RDX(%rsp);		\
157 	movq	%rsi, REGOFF_RSI(%rsp);		\
158 	movq	%rdi, REGOFF_RDI(%rsp);		\
159 	movq	%rbp, REGOFF_SAVFP(%rsp);	\
160 	movq	REGOFF_RIP(%rsp), %rcx;		\
161 	movq	%rcx, REGOFF_SAVPC(%rsp);	\
162 	xorl	%ecx, %ecx;			\
163 	movw	%gs, %cx;			\
164 	movq	%rcx, REGOFF_GS(%rsp);		\
165 	movw	%fs, %cx;			\
166 	movq	%rcx, REGOFF_FS(%rsp);		\
167 	movw	%es, %cx;			\
168 	movq	%rcx, REGOFF_ES(%rsp);		\
169 	movw	%ds, %cx;			\
170 	movq	%rcx, REGOFF_DS(%rsp);		\
171 	__SAVE_BASES
172 
173 #define	__RESTORE_REGS				\
174 	movq	REGOFF_RDI(%rsp),	%rdi;	\
175 	movq	REGOFF_RSI(%rsp),	%rsi;	\
176 	movq	REGOFF_RDX(%rsp),	%rdx;	\
177 	movq	REGOFF_RCX(%rsp),	%rcx;	\
178 	movq	REGOFF_R8(%rsp),	%r8;	\
179 	movq	REGOFF_R9(%rsp),	%r9;	\
180 	movq	REGOFF_RAX(%rsp),	%rax;	\
181 	movq	REGOFF_RBX(%rsp),	%rbx;	\
182 	movq	REGOFF_RBP(%rsp),	%rbp;	\
183 	movq	REGOFF_R10(%rsp),	%r10;	\
184 	movq	REGOFF_R11(%rsp),	%r11;	\
185 	movq	REGOFF_R12(%rsp),	%r12;	\
186 	movq	REGOFF_R13(%rsp),	%r13;	\
187 	movq	REGOFF_R14(%rsp),	%r14;	\
188 	movq	REGOFF_R15(%rsp),	%r15
189 
190 /*
191  * Push register state onto the stack. If we've
192  * interrupted userland, do a swapgs as well.
193  */
194 #define	INTR_PUSH				\
195 	subq	$REGOFF_TRAPNO, %rsp;		\
196 	__SAVE_REGS;				\
197 	cmpw	$KCS_SEL, REGOFF_CS(%rsp);	\
198 	je	6f;				\
199 	movq	$0, REGOFF_SAVFP(%rsp);		\
200 	SWAPGS;					\
201 6:	CLEAN_CS
202 
203 #define	INTR_POP			\
204 	leaq	sys_lcall32(%rip), %r11;\
205 	cmpq	%r11, REGOFF_RIP(%rsp);	\
206 	__RESTORE_REGS;			\
207 	je	5f;			\
208 	cmpw	$KCS_SEL, REGOFF_CS(%rsp);\
209 	je	8f;			\
210 5:	SWAPGS;				\
211 8:	addq	$REGOFF_RIP, %rsp
212 
213 #define	USER_POP			\
214 	__RESTORE_REGS;			\
215 	SWAPGS;				\
216 	addq	$REGOFF_RIP, %rsp	/* Adjust %rsp to prepare for iretq */
217 
218 #define	USER32_POP			\
219 	movl	REGOFF_RDI(%rsp), %edi;	\
220 	movl	REGOFF_RSI(%rsp), %esi;	\
221 	movl	REGOFF_RDX(%rsp), %edx;	\
222 	movl	REGOFF_RCX(%rsp), %ecx;	\
223 	movl	REGOFF_RAX(%rsp), %eax;	\
224 	movl	REGOFF_RBX(%rsp), %ebx;	\
225 	movl	REGOFF_RBP(%rsp), %ebp;	\
226 	SWAPGS;				\
227 	addq	$REGOFF_RIP, %rsp	/* Adjust %rsp to prepare for iretq */
228 
229 #define	DFTRAP_PUSH				\
230 	subq	$REGOFF_TRAPNO, %rsp;		\
231 	__SAVE_REGS
232 
233 #endif	/* _MACHDEP */
234 
235 /*
236  * Used to set rflags to known values at the head of an
237  * interrupt gate handler, i.e. interrupts are -already- disabled.
238  */
239 #define	INTGATE_INIT_KERNEL_FLAGS	\
240 	pushq	$F_OFF;			\
241 	popfq
242 
243 #endif	/* !_ASM */
244 
245 #include <sys/controlregs.h>
246 
247 #if defined(_KERNEL) && !defined(_ASM)
248 #if !defined(__lint) && defined(__GNUC__)
249 
250 extern __inline__ ulong_t getcr8(void)
251 {
252 	uint64_t value;
253 
254 	__asm__ __volatile__(
255 		"movq %%cr8, %0"
256 		: "=r" (value));
257 	return (value);
258 }
259 
260 extern __inline__ void setcr8(ulong_t value)
261 {
262 	__asm__ __volatile__(
263 		"movq %0, %%cr8"
264 		: /* no output */
265 		: "r" (value));
266 }
267 
268 #else
269 
270 extern ulong_t getcr8(void);
271 extern void setcr8(ulong_t);
272 
273 #endif	/* !defined(__lint) && defined(__GNUC__) */
274 #endif	/* _KERNEL && !_ASM */
275 
276 /* Control register layout for panic dump */
277 
278 #define	CREGSZ		0x68
279 #define	CREG_GDT	0
280 #define	CREG_IDT	0x10
281 #define	CREG_LDT	0x20
282 #define	CREG_TASKR	0x28
283 #define	CREG_CR0	0x30
284 #define	CREG_CR2	0x38
285 #define	CREG_CR3	0x40
286 #define	CREG_CR4	0x48
287 #define	CREG_CR8	0x50
288 #define	CREG_KGSBASE	0x58
289 #define	CREG_EFER	0x60
290 
291 #if !defined(_ASM) && defined(_INT64_TYPE)
292 
293 typedef	uint64_t	creg64_t;
294 typedef	upad128_t	creg128_t;
295 
296 struct cregs {
297 	creg128_t	cr_gdt;
298 	creg128_t	cr_idt;
299 	creg64_t	cr_ldt;
300 	creg64_t	cr_task;
301 	creg64_t	cr_cr0;
302 	creg64_t	cr_cr2;
303 	creg64_t	cr_cr3;
304 	creg64_t	cr_cr4;
305 	creg64_t	cr_cr8;
306 	creg64_t	cr_kgsbase;
307 	creg64_t	cr_efer;
308 };
309 
310 #if defined(_KERNEL)
311 extern void getcregs(struct cregs *);
312 #endif	/* _KERNEL */
313 
314 #endif	/* !_ASM && _INT64_TYPE */
315 
316 #ifdef __cplusplus
317 }
318 #endif
319 
320 #endif	/* !_AMD64_SYS_PRIVREGS_H */
321