xref: /titanic_41/usr/src/uts/i86pc/sys/rm_platter.h (revision 5203bc321053fb87d7073c7640548fab73634793)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * Copyright (c) 2010, Intel Corporation.
27  * All rights reserved.
28  */
29 
30 #ifndef	_SYS_RM_PLATTER_H
31 #define	_SYS_RM_PLATTER_H
32 
33 #include <sys/types.h>
34 #include <sys/tss.h>
35 #include <sys/segments.h>
36 
37 #ifdef	__cplusplus
38 extern "C" {
39 #endif
40 
41 #define	RM_PLATTER_CODE_SIZE		0x400
42 #define	RM_PLATTER_CPU_HALT_CODE_SIZE	0x100
43 
44 typedef	struct rm_platter {
45 	char		rm_code[RM_PLATTER_CODE_SIZE];
46 	char		rm_cpu_halt_code[RM_PLATTER_CPU_HALT_CODE_SIZE];
47 #if defined(__amd64)
48 	/*
49 	 * The compiler will want to 64-bit align the 64-bit rm_gdt_base
50 	 * pointer, so we need to add an extra four bytes of padding here to
51 	 * make sure rm_gdt_lim and rm_gdt_base will align to create a proper
52 	 * ten byte GDT pseudo-descriptor.
53 	 */
54 	uint32_t	rm_gdt_pad;
55 #endif	/* __amd64 */
56 	ushort_t	rm_debug;
57 	ushort_t	rm_gdt_lim;	/* stuff for lgdt */
58 	user_desc_t	*rm_gdt_base;
59 #if defined(__amd64)
60 	/*
61 	 * The compiler will want to 64-bit align the 64-bit rm_idt_base
62 	 * pointer, so we need to add an extra four bytes of padding here to
63 	 * make sure rm_idt_lim and rm_idt_base will align to create a proper
64 	 * ten byte IDT pseudo-descriptor.
65 	 */
66 	uint32_t	rm_idt_pad;
67 #endif	/* __amd64 */
68 	ushort_t	rm_cpu_halted;	/* non-zero if CPU has been halted */
69 	ushort_t	rm_idt_lim;	/* stuff for lidt */
70 	gate_desc_t	*rm_idt_base;
71 	uint_t		rm_pdbr;	/* cr3 value */
72 	uint_t		rm_cpu;		/* easy way to know which CPU we are */
73 	uint_t		rm_x86feature;	/* X86 supported features */
74 	uint_t		rm_cr4;		/* cr4 value on cpu0 */
75 #if defined(__amd64)
76 	/*
77 	 * Temporary GDT for the brief transition from real mode to protected
78 	 * mode before a CPU continues on into long mode.
79 	 *
80 	 * Putting it here assures it will be located in identity mapped memory
81 	 * (va == pa, 1:1).
82 	 *
83 	 * rm_temp_gdt is sized to hold only a null descriptor in slot zero
84 	 * and a 64-bit code descriptor in slot one.
85 	 *
86 	 * rm_temp_[gi]dt_lim and rm_temp_[gi]dt_base are the pseudo-descriptors
87 	 * for the temporary GDT and IDT, respectively.
88 	 */
89 	uint64_t	rm_temp_gdt[2];
90 	ushort_t	rm_temp_gdtdesc_pad;	/* filler to align GDT desc */
91 	ushort_t	rm_temp_gdt_lim;
92 	uint32_t	rm_temp_gdt_base;
93 	ushort_t	rm_temp_idtdesc_pad;	/* filler to align IDT desc */
94 	ushort_t	rm_temp_idt_lim;
95 	uint32_t	rm_temp_idt_base;
96 
97 	/*
98 	 * The code executing in the rm_platter needs the offset into the
99 	 * platter at which the 64-bit code starts, so have mp_startup
100 	 * calculate it and store it here.
101 	 */
102 	uint32_t	rm_longmode64_addr;
103 #endif	/* __amd64 */
104 } rm_platter_t;
105 
106 /*
107  * cpu tables put within a single structure two of the tables which need to be
108  * allocated when a CPU starts up.
109  *
110  * Note: the tss should be 16 byte aligned for best performance on amd64
111  * Since DEFAULTSTKSIZE is a multiple of PAGESIZE tss will be aligned.
112  */
113 struct cpu_tables {
114 	char		ct_stack[DEFAULTSTKSZ];
115 	struct tss	ct_tss;
116 };
117 
118 /*
119  * gdt entries are 8 bytes long, ensure that we have an even no. of them.
120  */
121 #if ((NGDT / 2) * 2 != NGDT)
122 #error "rm_platter.h: tss not properly aligned"
123 #endif
124 
125 #ifdef	__cplusplus
126 }
127 #endif
128 
129 #endif	/* _SYS_RM_PLATTER_H */
130