17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 55f9a4ecdSrab * Common Development and Distribution License (the "License"). 65f9a4ecdSrab * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 227417cfdeSKuriakose Kuruvilla * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 237c478bd9Sstevel@tonic-gate */ 24a3114836SGerry Liu /* 25a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 26a3114836SGerry Liu * All rights reserved. 27a3114836SGerry Liu */ 28*f16a0f4cSRobert Mustacchi /* 29*f16a0f4cSRobert Mustacchi * Copyright 2011 Joyent, Inc. All rights reserved. 30*f16a0f4cSRobert Mustacchi */ 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #ifndef _SYS_RM_PLATTER_H 337c478bd9Sstevel@tonic-gate #define _SYS_RM_PLATTER_H 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #include <sys/types.h> 367c478bd9Sstevel@tonic-gate #include <sys/tss.h> 377c478bd9Sstevel@tonic-gate #include <sys/segments.h> 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate #ifdef __cplusplus 407c478bd9Sstevel@tonic-gate extern "C" { 417c478bd9Sstevel@tonic-gate #endif 427c478bd9Sstevel@tonic-gate 43a3114836SGerry Liu #define RM_PLATTER_CODE_SIZE 0x400 44a3114836SGerry Liu #define RM_PLATTER_CPU_HALT_CODE_SIZE 0x100 45a3114836SGerry Liu 467c478bd9Sstevel@tonic-gate typedef struct rm_platter { 47a3114836SGerry Liu char rm_code[RM_PLATTER_CODE_SIZE]; 48a3114836SGerry Liu char rm_cpu_halt_code[RM_PLATTER_CPU_HALT_CODE_SIZE]; 497c478bd9Sstevel@tonic-gate #if defined(__amd64) 507c478bd9Sstevel@tonic-gate /* 517c478bd9Sstevel@tonic-gate * The compiler will want to 64-bit align the 64-bit rm_gdt_base 527c478bd9Sstevel@tonic-gate * pointer, so we need to add an extra four bytes of padding here to 537c478bd9Sstevel@tonic-gate * make sure rm_gdt_lim and rm_gdt_base will align to create a proper 547c478bd9Sstevel@tonic-gate * ten byte GDT pseudo-descriptor. 557c478bd9Sstevel@tonic-gate */ 567c478bd9Sstevel@tonic-gate uint32_t rm_gdt_pad; 577c478bd9Sstevel@tonic-gate #endif /* __amd64 */ 587c478bd9Sstevel@tonic-gate ushort_t rm_debug; 597c478bd9Sstevel@tonic-gate ushort_t rm_gdt_lim; /* stuff for lgdt */ 607c478bd9Sstevel@tonic-gate user_desc_t *rm_gdt_base; 617c478bd9Sstevel@tonic-gate #if defined(__amd64) 627c478bd9Sstevel@tonic-gate /* 637c478bd9Sstevel@tonic-gate * The compiler will want to 64-bit align the 64-bit rm_idt_base 647c478bd9Sstevel@tonic-gate * pointer, so we need to add an extra four bytes of padding here to 657c478bd9Sstevel@tonic-gate * make sure rm_idt_lim and rm_idt_base will align to create a proper 667c478bd9Sstevel@tonic-gate * ten byte IDT pseudo-descriptor. 677c478bd9Sstevel@tonic-gate */ 687c478bd9Sstevel@tonic-gate uint32_t rm_idt_pad; 697c478bd9Sstevel@tonic-gate #endif /* __amd64 */ 70a3114836SGerry Liu ushort_t rm_cpu_halted; /* non-zero if CPU has been halted */ 717c478bd9Sstevel@tonic-gate ushort_t rm_idt_lim; /* stuff for lidt */ 727c478bd9Sstevel@tonic-gate gate_desc_t *rm_idt_base; 737c478bd9Sstevel@tonic-gate uint_t rm_pdbr; /* cr3 value */ 747c478bd9Sstevel@tonic-gate uint_t rm_cpu; /* easy way to know which CPU we are */ 757417cfdeSKuriakose Kuruvilla uint_t rm_filler3; 767c478bd9Sstevel@tonic-gate uint_t rm_cr4; /* cr4 value on cpu0 */ 777c478bd9Sstevel@tonic-gate #if defined(__amd64) 787c478bd9Sstevel@tonic-gate /* 797c478bd9Sstevel@tonic-gate * Temporary GDT for the brief transition from real mode to protected 807c478bd9Sstevel@tonic-gate * mode before a CPU continues on into long mode. 817c478bd9Sstevel@tonic-gate * 827c478bd9Sstevel@tonic-gate * Putting it here assures it will be located in identity mapped memory 837c478bd9Sstevel@tonic-gate * (va == pa, 1:1). 847c478bd9Sstevel@tonic-gate * 857c478bd9Sstevel@tonic-gate * rm_temp_gdt is sized to hold only a null descriptor in slot zero 867c478bd9Sstevel@tonic-gate * and a 64-bit code descriptor in slot one. 877c478bd9Sstevel@tonic-gate * 887c478bd9Sstevel@tonic-gate * rm_temp_[gi]dt_lim and rm_temp_[gi]dt_base are the pseudo-descriptors 897c478bd9Sstevel@tonic-gate * for the temporary GDT and IDT, respectively. 907c478bd9Sstevel@tonic-gate */ 917c478bd9Sstevel@tonic-gate uint64_t rm_temp_gdt[2]; 927c478bd9Sstevel@tonic-gate ushort_t rm_temp_gdtdesc_pad; /* filler to align GDT desc */ 937c478bd9Sstevel@tonic-gate ushort_t rm_temp_gdt_lim; 947c478bd9Sstevel@tonic-gate uint32_t rm_temp_gdt_base; 957c478bd9Sstevel@tonic-gate ushort_t rm_temp_idtdesc_pad; /* filler to align IDT desc */ 967c478bd9Sstevel@tonic-gate ushort_t rm_temp_idt_lim; 977c478bd9Sstevel@tonic-gate uint32_t rm_temp_idt_base; 987c478bd9Sstevel@tonic-gate 997c478bd9Sstevel@tonic-gate /* 1007c478bd9Sstevel@tonic-gate * The code executing in the rm_platter needs the offset into the 1017c478bd9Sstevel@tonic-gate * platter at which the 64-bit code starts, so have mp_startup 1027c478bd9Sstevel@tonic-gate * calculate it and store it here. 1037c478bd9Sstevel@tonic-gate */ 1047c478bd9Sstevel@tonic-gate uint32_t rm_longmode64_addr; 1057c478bd9Sstevel@tonic-gate #endif /* __amd64 */ 1067c478bd9Sstevel@tonic-gate } rm_platter_t; 1077c478bd9Sstevel@tonic-gate 1087c478bd9Sstevel@tonic-gate /* 109ae115bc7Smrj * cpu tables put within a single structure two of the tables which need to be 110ae115bc7Smrj * allocated when a CPU starts up. 1117c478bd9Sstevel@tonic-gate * 112ae115bc7Smrj * Note: the tss should be 16 byte aligned for best performance on amd64 113ae115bc7Smrj * Since DEFAULTSTKSIZE is a multiple of PAGESIZE tss will be aligned. 1147c478bd9Sstevel@tonic-gate */ 1157c478bd9Sstevel@tonic-gate struct cpu_tables { 1167c478bd9Sstevel@tonic-gate char ct_stack[DEFAULTSTKSZ]; 117*f16a0f4cSRobert Mustacchi tss_t ct_tss; 1187c478bd9Sstevel@tonic-gate }; 1197c478bd9Sstevel@tonic-gate 1207c478bd9Sstevel@tonic-gate /* 1217c478bd9Sstevel@tonic-gate * gdt entries are 8 bytes long, ensure that we have an even no. of them. 1227c478bd9Sstevel@tonic-gate */ 1237c478bd9Sstevel@tonic-gate #if ((NGDT / 2) * 2 != NGDT) 1247c478bd9Sstevel@tonic-gate #error "rm_platter.h: tss not properly aligned" 1257c478bd9Sstevel@tonic-gate #endif 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1287c478bd9Sstevel@tonic-gate } 1297c478bd9Sstevel@tonic-gate #endif 1307c478bd9Sstevel@tonic-gate 1317c478bd9Sstevel@tonic-gate #endif /* _SYS_RM_PLATTER_H */ 132