xref: /titanic_41/usr/src/uts/i86pc/sys/apic.h (revision 9fa473b0d301bd8031d14635bfa88422277ca80a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #ifndef _SYS_APIC_APIC_H
26 #define	_SYS_APIC_APIC_H
27 
28 #include <sys/psm_types.h>
29 #include <sys/avintr.h>
30 #include <sys/pci.h>
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/psm_common.h>
37 
38 #define	APIC_PCPLUSMP_NAME	"pcplusmp"
39 
40 #define	APIC_IO_ADDR	0xfec00000
41 #define	APIC_LOCAL_ADDR	0xfee00000
42 #define	APIC_IO_MEMLEN	0xf
43 #define	APIC_LOCAL_MEMLEN	0xfffff
44 
45 /* Local Unit ID register */
46 #define	APIC_LID_REG		0x8
47 
48 /* I/o Unit Version Register */
49 #define	APIC_VERS_REG		0xc
50 
51 /* Task Priority register */
52 #define	APIC_TASK_REG		0x20
53 
54 /* EOI register */
55 #define	APIC_EOI_REG		0x2c
56 
57 /* Remote Read register		*/
58 #define	APIC_REMOTE_READ	0x30
59 
60 /* Logical Destination register */
61 #define	APIC_DEST_REG		0x34
62 
63 /* Destination Format register */
64 #define	APIC_FORMAT_REG		0x38
65 
66 /* Spurious Interrupt Vector register */
67 #define	APIC_SPUR_INT_REG	0x3c
68 
69 /* Error Status Register */
70 #define	APIC_ERROR_STATUS	0xa0
71 
72 /* Interrupt Command registers */
73 #define	APIC_INT_CMD1		0xc0
74 #define	APIC_INT_CMD2		0xc4
75 
76 /* Timer Vector Table register */
77 #define	APIC_LOCAL_TIMER	0xc8
78 
79 /* Local Interrupt Vector registers */
80 #define	APIC_CMCI_VECT		0xbc
81 #define	APIC_THERM_VECT		0xcc
82 #define	APIC_PCINT_VECT		0xd0
83 #define	APIC_INT_VECT0		0xd4
84 #define	APIC_INT_VECT1		0xd8
85 #define	APIC_ERR_VECT		0xdc
86 
87 /* IPL for performance counter interrupts */
88 #define	APIC_PCINT_IPL		0xe
89 #define	APIC_LVT_MASK		0x10000		/* Mask bit (16) in LVT */
90 
91 /* Initial Count register */
92 #define	APIC_INIT_COUNT		0xe0
93 
94 /* Current Count Register */
95 #define	APIC_CURR_COUNT		0xe4
96 #define	APIC_CURR_ADD		0x39	/* used for remote read command */
97 #define	CURR_COUNT_OFFSET	(sizeof (int32_t) * APIC_CURR_COUNT)
98 
99 /* Divider Configuration Register */
100 #define	APIC_DIVIDE_REG		0xf8
101 
102 /* Various mode for local APIC. Modes are mutually exclusive  */
103 #define	APIC_IS_DISABLED	0x0
104 #define	APIC_MODE_NOTSET	0x1
105 #define	LOCAL_APIC		0x2
106 #define	LOCAL_X2APIC		0x3
107 
108 /* x2APIC SELF IPI Register */
109 #define	X2APIC_SELF_IPI		0xFC
110 
111 /* General x2APIC constants used at various places */
112 #define	APIC_SVR_SUPPRESS_BROADCAST_EOI		0x1000
113 #define	APIC_DIRECTED_EOI_BIT			0x1000000
114 
115 /* IRR register	*/
116 #define	APIC_IRR_REG		0x80
117 
118 /* ISR register	*/
119 #define	APIC_ISR_REG		0x40
120 
121 #define	APIC_IO_REG		0x0
122 #define	APIC_IO_DATA		0x4
123 #define	APIC_IO_EOI		0x10
124 
125 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
126 #define	APIC_ID_BIT_OFFSET	24
127 #define	APIC_ICR_ID_BIT_OFFSET	24
128 #define	APIC_LDR_ID_BIT_OFFSET	24
129 
130 /*
131  * Choose between flat and clustered models by writing the following to the
132  * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will
133  * disable logical destination mode.
134  * Does not seem to be in the docs for local APICs on the processors.
135  */
136 #define	APIC_FLAT_MODEL		0xFFFFFFFFUL
137 #define	APIC_CLUSTER_MODEL	0x0FFFFFFF
138 
139 /*
140  * The commands which follow are window selectors written to APIC_IO_REG
141  * before data can be read/written from/to APIC_IO_DATA
142  */
143 
144 #define	APIC_ID_CMD		0x0
145 #define	APIC_VERS_CMD		0x1
146 #define	APIC_RDT_CMD		0x10
147 #define	APIC_RDT_CMD2		0x11
148 
149 #define	APIC_INTEGRATED_VERS	0x10	/* 0x10 & above indicates integrated */
150 #define	IOAPIC_VER_82489DX	0x01	/* Version ID: 82489DX External APIC */
151 
152 #define	APIC_INT_SPURIOUS	-1
153 
154 #define	APIC_IMCR_P1	0x22		/* int mode conf register port 1 */
155 #define	APIC_IMCR_P2	0x23		/* int mode conf register port 2 */
156 #define	APIC_IMCR_SELECT 0x70		/* select imcr by writing into P1 */
157 #define	APIC_IMCR_PIC	0x0		/* selects PIC mode (8259-> BSP) */
158 #define	APIC_IMCR_APIC	0x1		/* selects APIC mode (8259->APIC) */
159 
160 #define	APIC_CT_VECT	0x4ac		/* conf table vector		*/
161 #define	APIC_CT_SIZE	1024		/* conf table size		*/
162 
163 #define	APIC_ID		'MPAT'		/* conf table signature 	*/
164 
165 #define	VENID_AMD		0x1022
166 #define	DEVID_8131_IOAPIC	0x7451
167 #define	DEVID_8132_IOAPIC	0x7459
168 
169 #define	IOAPICS_NODE_NAME	"ioapics"
170 #define	IOAPICS_CHILD_NAME	"ioapic"
171 #define	IOAPICS_DEV_TYPE	"ioapic"
172 #define	IOAPICS_PROP_VENID	"vendor-id"
173 #define	IOAPICS_PROP_DEVID	"device-id"
174 
175 #define	IS_CLASS_IOAPIC(b, s, p) \
176 	((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC &&	\
177 	((p) == PCI_PERIPH_PIC_IF_IO_APIC ||			\
178 	(p) == PCI_PERIPH_PIC_IF_IOX_APIC))
179 
180 /*
181  * These macros are used in frequently called routines like
182  * apic_intr_enter().
183  */
184 #define	X2APIC_WRITE(reg, v) \
185 	wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)
186 
187 #define	LOCAL_APIC_WRITE_REG(reg, v) \
188 	apicadr[reg] = v
189 
190 /*
191  * MP floating pointer structure defined in Intel MP Spec 1.1
192  */
193 struct apic_mpfps_hdr {
194 	uint32_t	mpfps_sig;	/* _MP_ (0x5F4D505F)		*/
195 	uint32_t	mpfps_mpct_paddr; /* paddr of MP configuration tbl */
196 	uchar_t	mpfps_length;		/* in paragraph (16-bytes units) */
197 	uchar_t	mpfps_spec_rev;		/* version number of MP spec	 */
198 	uchar_t	mpfps_checksum;		/* checksum of complete structure */
199 	uchar_t	mpfps_featinfo1;	/* mp feature info bytes 1	 */
200 	uchar_t	mpfps_featinfo2;	/* mp feature info bytes 2	 */
201 	uchar_t	mpfps_featinfo3;	/* mp feature info bytes 3	 */
202 	uchar_t	mpfps_featinfo4;	/* mp feature info bytes 4	 */
203 	uchar_t	mpfps_featinfo5;	/* mp feature info bytes 5	 */
204 };
205 
206 #define	MPFPS_FEATINFO2_IMCRP		0x80	/* IMCRP presence bit	*/
207 
208 #define	APIC_MPS_OEM_ID_LEN		8
209 #define	APIC_MPS_PROD_ID_LEN		12
210 
211 struct apic_mp_cnf_hdr {
212 	uint_t	mpcnf_sig;
213 
214 	uint_t	mpcnf_tbl_length:	16,
215 		mpcnf_spec:		8,
216 		mpcnf_cksum:		8;
217 
218 	char	mpcnf_oem_str[APIC_MPS_OEM_ID_LEN];
219 
220 	char	mpcnf_prod_str[APIC_MPS_PROD_ID_LEN];
221 
222 	uint_t	mpcnf_oem_ptr;
223 
224 	uint_t	mpcnf_oem_tbl_size:	16,
225 		mpcnf_entry_cnt:	16;
226 
227 	uint_t	mpcnf_local_apic;
228 
229 	uint_t	mpcnf_resv;
230 };
231 
232 struct apic_procent {
233 	uint_t	proc_entry:		8,
234 		proc_apicid:		8,
235 		proc_version:		8,
236 		proc_cpuflags:		8;
237 
238 	uint_t	proc_stepping:		4,
239 		proc_model:		4,
240 		proc_family:		4,
241 		proc_type:		2,	/* undocumented feature */
242 		proc_resv1:		18;
243 
244 	uint_t	proc_feature;
245 
246 	uint_t	proc_resv2;
247 
248 	uint_t	proc_resv3;
249 };
250 
251 /*
252  * proc_cpuflags definitions
253  */
254 #define	CPUFLAGS_EN	1	/* if not set, this processor is unusable */
255 #define	CPUFLAGS_BP	2	/* set if this is the bootstrap processor */
256 
257 
258 struct apic_bus {
259 	uchar_t	bus_entry;
260 	uchar_t	bus_id;
261 	ushort_t	bus_str1;
262 	uint_t	bus_str2;
263 };
264 
265 struct apic_io_entry {
266 	uint_t	io_entry:		8,
267 		io_apicid:		8,
268 		io_version:		8,
269 		io_flags:		8;
270 
271 	uint_t	io_apic_addr;
272 };
273 
274 #define	IOAPIC_FLAGS_EN		0x01	/* this I/O apic is enable or not */
275 
276 #define	MAX_IO_APIC		32	/* maximum # of IOAPICs supported */
277 
278 struct apic_io_intr {
279 	uint_t	intr_entry:		8,
280 		intr_type:		8,
281 		intr_po:		2,
282 		intr_el:		2,
283 		intr_resv:		12;
284 
285 	uint_t	intr_busid:		8,
286 		intr_irq:		8,
287 		intr_destid:		8,
288 		intr_destintin:		8;
289 };
290 
291 /*
292  * intr_type definitions
293  */
294 #define	IO_INTR_INT	0x00
295 #define	IO_INTR_NMI	0x01
296 #define	IO_INTR_SMI	0x02
297 #define	IO_INTR_EXTINT	0x03
298 
299 /*
300  * destination APIC ID
301  */
302 #define	INTR_ALL_APIC		0xff
303 
304 
305 /* local vector table							*/
306 #define	AV_MASK		0x10000
307 
308 /* interrupt command register 32-63					*/
309 #define	AV_TOALL	0x7fffffff
310 #define	AV_HIGH_ORDER	0x40000000
311 #define	AV_IM_OFF	0x40000000
312 
313 /* interrupt command register 0-31					*/
314 #define	AV_DELIV_MODE	0x700
315 
316 #define	AV_FIXED	0x000
317 #define	AV_LOPRI	0x100
318 #define	AV_SMI		0x200
319 #define	AV_REMOTE	0x300
320 #define	AV_NMI		0x400
321 #define	AV_RESET	0x500
322 #define	AV_STARTUP	0x600
323 #define	AV_EXTINT	0x700
324 
325 #define	AV_PDEST	0x000
326 #define	AV_LDEST	0x800
327 
328 /* IO & Local APIC Bit Definitions */
329 #define	RDT_VECTOR(x)	((uchar_t)((x) & 0xFF))
330 #define	AV_PENDING	0x1000
331 #define	AV_ACTIVE_LOW	0x2000		/* only for integrated APIC */
332 #define	AV_REMOTE_IRR   0x4000		/* IOAPIC RDT-specific */
333 #define	AV_LEVEL	0x8000
334 #define	AV_DEASSERT	AV_LEVEL
335 #define	AV_ASSERT	0xc000
336 
337 #define	AV_READ_PENDING	0x10000
338 #define	AV_REMOTE_STATUS	0x20000	/* 1 = valid, 0 = invalid */
339 
340 #define	AV_SH_SELF		0x40000	/* Short hand for self */
341 #define	AV_SH_ALL_INCSELF	0x80000 /* All processors */
342 #define	AV_SH_ALL_EXCSELF	0xc0000 /* All excluding self */
343 /* spurious interrupt vector register					*/
344 #define	AV_UNIT_ENABLE	0x100
345 
346 /* timer vector table							*/
347 #define	AV_TIME		0x20000	/* Set timer mode to periodic */
348 
349 #define	APIC_MAXVAL	0xffffffffUL
350 #define	APIC_TIME_MIN	0x5000
351 #define	APIC_TIME_COUNT	0x4000
352 
353 /*
354  * Range of the low byte value in apic_tick before starting calibration
355  */
356 #define	APIC_LB_MIN	0x60
357 #define	APIC_LB_MAX	0xe0
358 
359 #define	APIC_MAX_VECTOR		255
360 #define	APIC_RESV_VECT		0x00
361 #define	APIC_RESV_IRQ		0xfe
362 #define	APIC_BASE_VECT		0x20	/* This will come in as interrupt 0 */
363 #define	APIC_AVAIL_VECTOR	(APIC_MAX_VECTOR+1-APIC_BASE_VECT)
364 #define	APIC_VECTOR_PER_IPL	0x10	/* # of vectors before PRI changes */
365 #define	APIC_VECTOR(ipl)	(apic_ipltopri[ipl] | APIC_RESV_VECT)
366 #define	APIC_VECTOR_MASK	0x0f
367 #define	APIC_HI_PRI_VECTS	2	/* vects reserved for hi pri reqs */
368 #define	APIC_IPL_MASK		0xf0
369 #define	APIC_IPL_SHIFT		4	/* >> to get ipl part of vector */
370 #define	APIC_FIRST_FREE_IRQ	0x10
371 #define	APIC_MAX_ISA_IRQ	15
372 #define	APIC_IPL0		0x0f	/* let IDLE_IPL be the lowest */
373 #define	APIC_IDLE_IPL		0x00
374 
375 #define	APIC_MASK_ALL		0xf0	/* Mask all interrupts */
376 
377 /* spurious interrupt vector						*/
378 #define	APIC_SPUR_INTR		0xFF
379 
380 /* special or reserve vectors */
381 #define	APIC_CHECK_RESERVE_VECTORS(v) \
382 	(((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
383 	((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == T_INT80))
384 
385 /* cmos shutdown code for BIOS						*/
386 #define	BIOS_SHUTDOWN		0x0a
387 
388 /* define the entry types for BIOS information tables as defined in PC+MP */
389 #define	APIC_CPU_ENTRY		0
390 #define	APIC_BUS_ENTRY		1
391 #define	APIC_IO_ENTRY		2
392 #define	APIC_IO_INTR_ENTRY	3
393 #define	APIC_LOCAL_INTR_ENTRY	4
394 #define	APIC_MPTBL_ADDR		(639 * 1024)
395 /*
396  * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
397  * of system base memory or in ROM between 0xF0000 and 0xFFFFF
398  */
399 #define	MPFPS_RAM_WIN_LEN	1024
400 #define	MPFPS_ROM_WIN_START	(uint32_t)0xf0000
401 #define	MPFPS_ROM_WIN_LEN	0x10000
402 
403 #define	EISA_LEVEL_CNTL		0x4D0
404 
405 /* definitions for apic_irq_table */
406 #define	FREE_INDEX		(short)-1	/* empty slot */
407 #define	RESERVE_INDEX		(short)-2	/* ipi, softintr, clkintr */
408 #define	ACPI_INDEX		(short)-3	/* ACPI */
409 #define	MSI_INDEX		(short)-4	/* MSI */
410 #define	MSIX_INDEX		(short)-5	/* MSI-X */
411 #define	DEFAULT_INDEX		(short)0x7FFF
412 	/* biggest positive no. to avoid conflict with actual index */
413 
414 #define	APIC_IS_MSI_OR_MSIX_INDEX(index) \
415 	((index) == MSI_INDEX || (index) == MSIX_INDEX)
416 
417 /*
418  * definitions for MSI Address
419  */
420 #define	MSI_ADDR_HDR		APIC_LOCAL_ADDR
421 #define	MSI_ADDR_DEST_SHIFT	12	/* Destination CPU's apic id */
422 #define	MSI_ADDR_RH_FIXED	0x0	/* Redirection Hint Fixed */
423 #define	MSI_ADDR_RH_LOPRI	0x1	/* Redirection Hint Lowest priority */
424 #define	MSI_ADDR_RH_SHIFT	3
425 #define	MSI_ADDR_DM_PHYSICAL	0x0	/* Physical Destination Mode */
426 #define	MSI_ADDR_DM_LOGICAL	0x1	/* Logical Destination Mode */
427 #define	MSI_ADDR_DM_SHIFT	2
428 
429 /*
430  * TM is either edge or level.
431  */
432 #define	TRIGGER_MODE_EDGE		0x0	/* edge sensitive */
433 #define	TRIGGER_MODE_LEVEL		0x1	/* level sensitive */
434 
435 /*
436  * definitions for MSI Data
437  */
438 #define	MSI_DATA_DELIVERY_FIXED		0x0	/* Fixed delivery */
439 #define	MSI_DATA_DELIVERY_LOPRI		0x1	/* Lowest priority delivery */
440 #define	MSI_DATA_DELIVERY_SMI		0x2
441 #define	MSI_DATA_DELIVERY_NMI		0x4
442 #define	MSI_DATA_DELIVERY_INIT		0x5
443 #define	MSI_DATA_DELIVERY_EXTINT	0x7
444 #define	MSI_DATA_DELIVERY_SHIFT		8
445 #define	MSI_DATA_TM_EDGE		TRIGGER_MODE_EDGE
446 #define	MSI_DATA_TM_LEVEL		TRIGGER_MODE_LEVEL
447 #define	MSI_DATA_TM_SHIFT		15
448 #define	MSI_DATA_LEVEL_DEASSERT		0x0
449 #define	MSI_DATA_LEVEL_ASSERT		0x1	/* Edge always assert */
450 #define	MSI_DATA_LEVEL_SHIFT		14
451 
452 /*
453  * use to define each irq setup by the apic
454  */
455 typedef struct	apic_irq {
456 	short	airq_mps_intr_index;	/* index into mps interrupt entries */
457 					/*  table */
458 	uchar_t	airq_intin_no;
459 	uchar_t	airq_ioapicindex;
460 	dev_info_t	*airq_dip; /* device corresponding to this interrupt */
461 	/*
462 	 * IRQ could be shared (in H/W) in which case dip & major will be
463 	 * for the one that was last added at this level. We cannot keep a
464 	 * linked list as delspl does not tell us which device has just
465 	 * been unloaded. For most servers where we are worried about
466 	 * performance, interrupt should not be shared & should not be
467 	 * a problem. This does not cause any correctness issue - dip is
468 	 * used only as an optimisation to avoid going thru all the tables
469 	 * in translate IRQ (which is always called twice due to brokenness
470 	 * in the way IPLs are determined for devices). major is used only
471 	 * to bind interrupts corresponding to the same device on the same
472 	 * CPU. Not finding major will just cause it to be potentially bound
473 	 * to another CPU.
474 	 */
475 	major_t	airq_major;	/* major number corresponding to the device */
476 	ushort_t airq_rdt_entry;	/* level, polarity & trig mode */
477 	uint32_t airq_cpu;		/* target CPU, non-reserved IRQ only */
478 	uint32_t airq_temp_cpu;   /* non-reserved IRQ only, for disable_intr */
479 	uchar_t	airq_vector;		/* Vector chosen for this irq */
480 	uchar_t	airq_share;		/* number of interrupts at this irq */
481 	uchar_t	airq_share_id;		/* id to identify source from irqno */
482 	uchar_t	airq_ipl;		/* The ipl at which this is handled */
483 	iflag_t airq_iflag;		/* interrupt flag */
484 	uchar_t	airq_origirq;		/* original irq passed in */
485 	uint_t	airq_busy;		/* How frequently did clock find */
486 					/* us in this */
487 	struct apic_irq *airq_next;	/* chain of intpts sharing a vector */
488 	void		*airq_intrmap_private; /* intr remap private data */
489 } apic_irq_t;
490 
491 #define	IRQ_USER_BOUND	0x80000000 /* user requested bind if set in airq_cpu */
492 #define	IRQ_UNBOUND	(uint32_t)-1	/* set in airq_cpu and airq_temp_cpu */
493 #define	IRQ_UNINIT	(uint32_t)-2 /* in airq_temp_cpu till addspl called */
494 
495 /* Macros to help deal with shared interrupts */
496 #define	VIRTIRQ(irqno, share_id)	((irqno) | ((share_id) << 8))
497 #define	IRQINDEX(irq)	((irq) & 0xFF)	/* Mask to get irq from virtual irq */
498 
499 /*
500  * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we
501  * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also
502  * don't want the compiler to optimize apic_cpus_info.
503  */
504 #define	APIC_PADSZ	15
505 
506 #pragma	pack(1)
507 typedef struct apic_cpus_info {
508 	uint32_t aci_local_id;
509 	uchar_t	aci_local_ver;
510 	uchar_t	aci_status;
511 	uchar_t	aci_redistribute;	/* Selected for redistribution */
512 	uint_t	aci_busy;		/* Number of ticks we were in ISR */
513 	uint_t	aci_spur_cnt;		/* # of spurious intpts on this cpu */
514 	uint_t	aci_ISR_in_progress;	/* big enough to hold 1 << MAXIPL */
515 	uchar_t	aci_curipl;		/* IPL of current ISR */
516 	uchar_t	aci_current[MAXIPL];	/* Current IRQ at each IPL */
517 	uint32_t aci_bound;		/* # of user requested binds ? */
518 	uint32_t aci_temp_bound;	/* # of non user IRQ binds */
519 	uint32_t aci_processor_id;	/* Only used in ACPI mode. */
520 	uchar_t	aci_idle;		/* The CPU is idle */
521 	/*
522 	 * Fill to make sure each struct is in separate 64-byte cache line.
523 	 */
524 	uchar_t	aci_pad[APIC_PADSZ];	/* padding for 64-byte cache line */
525 } apic_cpus_info_t;
526 #pragma	pack()
527 
528 #define	APIC_CPU_ONLINE		1
529 #define	APIC_CPU_INTR_ENABLE	2
530 #define	APIC_CPU_FREE		4	/* APIC CPU slot is free */
531 #define	APIC_CPU_DIRTY		8	/* Slot was once used */
532 
533 /*
534  * APIC ops to support various flavors of APIC like APIC and x2APIC.
535  */
536 typedef	struct apic_regs_ops {
537 	uint64_t	(*apic_read)(uint32_t);
538 	void 		(*apic_write)(uint32_t, uint64_t);
539 	int		(*apic_get_pri)(void);
540 	void		(*apic_write_task_reg)(uint64_t);
541 	void		(*apic_write_int_cmd)(uint32_t, uint32_t);
542 	void		(*apic_send_eoi)(uint32_t);
543 } apic_reg_ops_t;
544 
545 /*
546  * interrupt structure for ioapic and msi
547  */
548 typedef struct ioapic_rdt {
549 	uint32_t	ir_lo;
550 	uint32_t	ir_hi;
551 } ioapic_rdt_t;
552 
553 typedef struct msi_regs {
554 	uint32_t	mr_data;
555 	uint64_t	mr_addr;
556 }msi_regs_t;
557 
558 /*
559  * APIC ops to support intel interrupt remapping
560  */
561 typedef struct apic_intrmap_ops {
562 	int	(*apic_intrmap_init)(int);
563 	void	(*apic_intrmap_enable)(int);
564 	void	(*apic_intrmap_alloc_entry)(apic_irq_t *);
565 	void	(*apic_intrmap_map_entry)(apic_irq_t *, void *);
566 	void	(*apic_intrmap_free_entry)(apic_irq_t *);
567 	void	(*apic_intrmap_record_rdt)(apic_irq_t *, ioapic_rdt_t *);
568 	void	(*apic_intrmap_record_msi)(apic_irq_t *, msi_regs_t *);
569 } apic_intrmap_ops_t;
570 
571 /*
572  * Various poweroff methods and ports & bits for them
573  */
574 #define	APIC_POWEROFF_NONE		0
575 #define	APIC_POWEROFF_VIA_RTC		1
576 #define	APIC_POWEROFF_VIA_ASPEN_BMC	2
577 #define	APIC_POWEROFF_VIA_SITKA_BMC	3
578 
579 /* For RTC */
580 #define	RTC_REGA		0x0a
581 #define	PFR_REG			0x4a    /* extended control register */
582 #define	PAB_CBIT		0x08
583 #define	WF_FLAG			0x02
584 #define	KS_FLAG			0x01
585 #define	EXT_BANK		0x10
586 
587 /* For Aspen/Drake BMC */
588 
589 #define	CC_SMS_GET_STATUS	0x40
590 #define	CC_SMS_WR_START		0x41
591 #define	CC_SMS_WR_NEXT		0x42
592 #define	CC_SMS_WR_END		0x43
593 
594 #define	MISMIC_DATA_REGISTER	0x0ca9
595 #define	MISMIC_CNTL_REGISTER	0x0caa
596 #define	MISMIC_FLAG_REGISTER	0x0cab
597 
598 #define	MISMIC_BUSY_MASK	0x01
599 
600 /* For Sitka/Cabrillo BMC */
601 
602 #define	SMS_GET_STATUS		0x60
603 #define	SMS_WRITE_START		0x61
604 #define	SMS_WRITE_END		0x62
605 
606 #define	SMS_DATA_REGISTER	0x0ca2
607 #define	SMS_STATUS_REGISTER	0x0ca3
608 #define	SMS_COMMAND_REGISTER	0x0ca3
609 
610 #define	SMS_IBF_MASK		0x02
611 #define	SMS_STATE_MASK		0xc0
612 
613 #define	SMS_IDLE_STATE		0x00
614 #define	SMS_READ_STATE		0x40
615 #define	SMS_WRITE_STATE		0x80
616 #define	SMS_ERROR_STATE		0xc0
617 
618 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg);
619 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value);
620 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value);
621 
622 /* Macros for reading/writing the IOAPIC RDT entries */
623 #define	READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \
624 	ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)))
625 
626 #define	READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \
627 	ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)))
628 
629 #define	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \
630 	ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value)
631 
632 #define	WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \
633 	ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value)
634 
635 /* Used by PSM_INTR_OP_GET_INTR to return device information. */
636 typedef struct {
637 	uint16_t	avgi_req_flags;	/* request flags - to kernel */
638 	uint8_t		avgi_num_devs;	/* # devs on this ino - from kernel */
639 	uint8_t		avgi_vector;	/* vector */
640 	uint32_t	avgi_cpu_id;	/* cpu of interrupt - from kernel */
641 	dev_info_t	**avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */
642 					/* Contains num_devs elements. */
643 } apic_get_intr_t;
644 
645 /* Masks for avgi_req_flags. */
646 #define	PSMGI_REQ_CPUID		0x1	/* Request CPU ID */
647 #define	PSMGI_REQ_NUM_DEVS	0x2	/* Request num of devices on vector */
648 #define	PSMGI_REQ_VECTOR	0x4
649 #define	PSMGI_REQ_GET_DEVS	0x8	/* Request device list */
650 #define	PSMGI_REQ_ALL		0xf	/* Request everything */
651 
652 /* Other flags */
653 #define	PSMGI_INTRBY_VEC	0	/* Vec passed.  xlate to IRQ needed */
654 #define	PSMGI_INTRBY_IRQ	0x8000	/* IRQ passed.  no xlate needed */
655 #define	PSMGI_INTRBY_FLAGS	0x8000	/* Mask for this flag */
656 
657 /*
658  * Use scaled-fixed-point arithmetic to calculate apic ticks.
659  * Round when dividing (by adding half of divisor to dividend)
660  * for one extra bit of precision.
661  */
662 
663 #define	SF	(1ULL<<20)		/* Scaling Factor: scale by 2^20 */
664 #define	APIC_TICKS_TO_NSECS(ticks)	((((int64_t)(ticks) * SF) + \
665 					apic_ticks_per_SFnsecs / 2) / \
666 					apic_ticks_per_SFnsecs);
667 #define	APIC_NSECS_TO_TICKS(nsecs)	(((int64_t)(nsecs) * \
668 					apic_ticks_per_SFnsecs + (SF/2)) / SF)
669 
670 extern int	apic_verbose;
671 
672 /* Flag definitions for apic_verbose */
673 #define	APIC_VERBOSE_IOAPIC_FLAG		0x00000001
674 #define	APIC_VERBOSE_IRQ_FLAG			0x00000002
675 #define	APIC_VERBOSE_POWEROFF_FLAG		0x00000004
676 #define	APIC_VERBOSE_POWEROFF_PAUSE_FLAG	0x00000008
677 
678 
679 #define	APIC_VERBOSE_IOAPIC(fmt) \
680 	if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \
681 		cmn_err fmt;
682 
683 #define	APIC_AV_PENDING_SET() \
684 	while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \
685 		apic_ret();
686 
687 #define	APIC_VERBOSE_IRQ(fmt) \
688 	if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \
689 		cmn_err fmt;
690 
691 #define	APIC_VERBOSE_POWEROFF(fmt) \
692 	if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \
693 		prom_printf fmt;
694 
695 #ifdef DEBUG
696 #define	DENT		0x0001
697 extern int	apic_debug;
698 /*
699  * set apic_restrict_vector to the # of vectors we want to allow per range
700  * useful in testing shared interrupt logic by setting it to 2 or 3
701  */
702 extern int	apic_restrict_vector;
703 
704 #define	APIC_DEBUG_MSGBUFSIZE	2048
705 extern int	apic_debug_msgbuf[];
706 extern int	apic_debug_msgbufindex;
707 
708 /*
709  * Put "int" info into debug buffer. No MP consistency, but light weight.
710  * Good enough for most debugging.
711  */
712 #define	APIC_DEBUG_BUF_PUT(x) \
713 	apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \
714 	if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \
715 		apic_debug_msgbufindex = 0;
716 
717 #endif /* DEBUG */
718 
719 extern int	apic_error;
720 /* values which apic_error can take. Not catastrophic, but may help debug */
721 #define	APIC_ERR_BOOT_EOI		0x1
722 #define	APIC_ERR_GET_IPIVECT_FAIL	0x2
723 #define	APIC_ERR_INVALID_INDEX		0x4
724 #define	APIC_ERR_MARK_VECTOR_FAIL	0x8
725 #define	APIC_ERR_APIC_ERROR		0x40000000
726 #define	APIC_ERR_NMI			0x80000000
727 
728 /*
729  * ACPI definitions
730  */
731 /* _PIC method arguments */
732 #define	ACPI_PIC_MODE	0
733 #define	ACPI_APIC_MODE	1
734 
735 /* APIC error flags we care about */
736 #define	APIC_SEND_CS_ERROR	0x01
737 #define	APIC_RECV_CS_ERROR	0x02
738 #define	APIC_CS_ERRORS		(APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR)
739 
740 /* Maximum number of times to retry reprogramming at apic_intr_exit time */
741 #define	APIC_REPROGRAM_MAX_TRIES 10000
742 
743 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */
744 #define	IOAPIC_MASK 1
745 #define	IOAPIC_NOMASK 0
746 
747 #define	INTR_ROUND_ROBIN_WITH_AFFINITY	0
748 #define	INTR_ROUND_ROBIN		1
749 #define	INTR_LOWEST_PRIORITY		2
750 
751 
752 
753 struct ioapic_reprogram_data {
754 	boolean_t			done;
755 	apic_irq_t			*irqp;
756 	/* The CPU to which the int will be bound */
757 	int				bindcpu;
758 	/* # times the reprogram timeout was called */
759 	unsigned			tries;
760 };
761 
762 /* The irq # is implicit in the array index: */
763 extern struct ioapic_reprogram_data apic_reprogram_info[];
764 
765 extern void apic_intr_exit(int ipl, int irq);
766 extern void x2apic_intr_exit(int ipl, int irq);
767 extern int apic_probe_common();
768 extern void apic_init_common();
769 extern void ioapic_init_intr();
770 extern void ioapic_disable_redirection();
771 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
772 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
773 extern void apic_cleanup_busy();
774 extern void apic_intr_redistribute();
775 extern uchar_t apic_xlate_vector(uchar_t vector);
776 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri);
777 extern void apic_free_vector(uchar_t vector);
778 extern int apic_allocate_irq(int irq);
779 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid,
780     uchar_t intin);
781 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu,
782     struct ioapic_reprogram_data *drep);
783 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu);
784 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type);
785 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
786     psm_intr_op_t intr_op, int *result);
787 extern int apic_state(psm_state_request_t *);
788 extern boolean_t apic_cpu_in_range(int cpu);
789 extern int apic_check_msi_support();
790 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec,
791     int type);
792 extern int apic_navail_vector(dev_info_t *dip, int pri);
793 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count,
794     int pri, int behavior);
795 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count,
796     int pri, int behavior);
797 extern void  apic_free_vectors(dev_info_t *dip, int inum, int count, int pri,
798     int type);
799 extern int apic_get_vector_intr_info(int vecirq,
800     apic_get_intr_t *intr_params_p);
801 extern uchar_t apic_find_multi_vectors(int pri, int count);
802 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred);
803 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags);
804 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags);
805 extern void mapout_apic(caddr_t addr, size_t len);
806 extern void mapout_ioapic(caddr_t addr, size_t len);
807 extern uchar_t apic_modify_vector(uchar_t vector, int irq);
808 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum);
809 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type);
810 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum);
811 extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum,
812     int vector, int count, int target_apic_id);
813 extern char *apic_get_apic_type();
814 extern uint16_t	apic_get_apic_version();
815 extern void x2apic_send_ipi();
816 extern void apic_ret();
817 extern int apic_detect_x2apic();
818 extern void apic_enable_x2apic();
819 extern int apic_local_mode();
820 extern void apic_change_eoi();
821 extern void apic_send_EOI(uint32_t);
822 extern void apic_send_directed_EOI(uint32_t);
823 
824 extern volatile uint32_t *apicadr;	/* virtual addr of local APIC   */
825 extern int apic_forceload;
826 extern apic_cpus_info_t *apic_cpus;
827 #ifdef _MACHDEP
828 extern cpuset_t apic_cpumask;
829 #endif
830 extern uint_t apic_picinit_called;
831 extern uchar_t apic_ipltopri[MAXIPL+1];
832 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1];
833 extern int apic_max_device_irq;
834 extern int apic_min_device_irq;
835 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
836 extern volatile uint32_t *apicioadr[MAX_IO_APIC];
837 extern uchar_t apic_io_id[MAX_IO_APIC];
838 extern lock_t apic_ioapic_lock;
839 extern uint32_t apic_physaddr[MAX_IO_APIC];
840 extern kmutex_t airq_mutex;
841 extern int apic_first_avail_irq;
842 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL];
843 extern int apic_imcrp;
844 extern int apic_revector_pending;
845 extern char apic_level_intr[APIC_MAX_VECTOR+1];
846 extern uchar_t apic_resv_vector[MAXIPL+1];
847 extern int apic_sample_factor_redistribution;
848 extern int apic_int_busy_mark;
849 extern int apic_int_free_mark;
850 extern int apic_diff_for_redistribution;
851 extern int apic_poweroff_method;
852 extern int apic_enable_acpi;
853 extern int apic_nproc;
854 extern int apic_max_nproc;
855 extern int apic_next_bind_cpu;
856 extern int apic_redistribute_sample_interval;
857 extern int apic_multi_msi_enable;
858 extern int apic_sci_vect;
859 extern uchar_t apic_ipls[];
860 extern apic_reg_ops_t *apic_reg_ops;
861 extern int apic_mode;
862 extern void x2apic_update_psm();
863 extern void apic_change_ops();
864 extern void apic_common_send_ipi(int, int);
865 extern void apic_set_directed_EOI_handler();
866 extern int apic_directed_EOI_supported();
867 
868 extern apic_intrmap_ops_t *apic_vt_ops;
869 
870 #ifdef	__cplusplus
871 }
872 #endif
873 
874 #endif	/* _SYS_APIC_APIC_H */
875