1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 28 /* All Rights Reserved */ 29 /* */ 30 /* Copyright (c) 1987, 1988 Microsoft Corporation */ 31 /* All Rights Reserved */ 32 /* */ 33 34 #include <sys/types.h> 35 #include <sys/sysmacros.h> 36 #include <sys/param.h> 37 #include <sys/signal.h> 38 #include <sys/systm.h> 39 #include <sys/user.h> 40 #include <sys/proc.h> 41 #include <sys/disp.h> 42 #include <sys/class.h> 43 #include <sys/core.h> 44 #include <sys/syscall.h> 45 #include <sys/cpuvar.h> 46 #include <sys/vm.h> 47 #include <sys/sysinfo.h> 48 #include <sys/fault.h> 49 #include <sys/stack.h> 50 #include <sys/psw.h> 51 #include <sys/regset.h> 52 #include <sys/fp.h> 53 #include <sys/trap.h> 54 #include <sys/kmem.h> 55 #include <sys/vtrace.h> 56 #include <sys/cmn_err.h> 57 #include <sys/prsystm.h> 58 #include <sys/mutex_impl.h> 59 #include <sys/machsystm.h> 60 #include <sys/archsystm.h> 61 #include <sys/sdt.h> 62 #include <sys/avintr.h> 63 #include <sys/kobj.h> 64 65 #include <vm/hat.h> 66 67 #include <vm/seg_kmem.h> 68 #include <vm/as.h> 69 #include <vm/seg.h> 70 #include <vm/hat_pte.h> 71 #include <vm/hat_i86.h> 72 73 #include <sys/procfs.h> 74 75 #include <sys/reboot.h> 76 #include <sys/debug.h> 77 #include <sys/debugreg.h> 78 #include <sys/modctl.h> 79 #include <sys/aio_impl.h> 80 #include <sys/tnf.h> 81 #include <sys/tnf_probe.h> 82 #include <sys/cred.h> 83 #include <sys/mman.h> 84 #include <sys/x86_archext.h> 85 #include <sys/copyops.h> 86 #include <c2/audit.h> 87 #include <sys/ftrace.h> 88 #include <sys/panic.h> 89 #include <sys/traptrace.h> 90 #include <sys/ontrap.h> 91 #include <sys/cpc_impl.h> 92 #include <sys/bootconf.h> 93 #include <sys/bootinfo.h> 94 #include <sys/promif.h> 95 #include <sys/mach_mmu.h> 96 #if defined(__xpv) 97 #include <sys/hypervisor.h> 98 #endif 99 #include <sys/contract/process_impl.h> 100 101 #define USER 0x10000 /* user-mode flag added to trap type */ 102 103 static const char *trap_type_mnemonic[] = { 104 "de", "db", "2", "bp", 105 "of", "br", "ud", "nm", 106 "df", "9", "ts", "np", 107 "ss", "gp", "pf", "15", 108 "mf", "ac", "mc", "xf" 109 }; 110 111 static const char *trap_type[] = { 112 "Divide error", /* trap id 0 */ 113 "Debug", /* trap id 1 */ 114 "NMI interrupt", /* trap id 2 */ 115 "Breakpoint", /* trap id 3 */ 116 "Overflow", /* trap id 4 */ 117 "BOUND range exceeded", /* trap id 5 */ 118 "Invalid opcode", /* trap id 6 */ 119 "Device not available", /* trap id 7 */ 120 "Double fault", /* trap id 8 */ 121 "Coprocessor segment overrun", /* trap id 9 */ 122 "Invalid TSS", /* trap id 10 */ 123 "Segment not present", /* trap id 11 */ 124 "Stack segment fault", /* trap id 12 */ 125 "General protection", /* trap id 13 */ 126 "Page fault", /* trap id 14 */ 127 "Reserved", /* trap id 15 */ 128 "x87 floating point error", /* trap id 16 */ 129 "Alignment check", /* trap id 17 */ 130 "Machine check", /* trap id 18 */ 131 "SIMD floating point exception", /* trap id 19 */ 132 }; 133 134 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0])) 135 136 #define SLOW_SCALL_SIZE 2 137 #define FAST_SCALL_SIZE 2 138 139 int tudebug = 0; 140 int tudebugbpt = 0; 141 int tudebugfpe = 0; 142 int tudebugsse = 0; 143 144 #if defined(TRAPDEBUG) || defined(lint) 145 int tdebug = 0; 146 int lodebug = 0; 147 int faultdebug = 0; 148 #else 149 #define tdebug 0 150 #define lodebug 0 151 #define faultdebug 0 152 #endif /* defined(TRAPDEBUG) || defined(lint) */ 153 154 #if defined(TRAPTRACE) 155 /* 156 * trap trace record for cpu0 is allocated here. 157 * trap trace records for non-boot cpus are allocated in mp_startup_init(). 158 */ 159 static trap_trace_rec_t trap_tr0[TRAPTR_NENT]; 160 trap_trace_ctl_t trap_trace_ctl[NCPU] = { 161 { 162 (uintptr_t)trap_tr0, /* next record */ 163 (uintptr_t)trap_tr0, /* first record */ 164 (uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */ 165 (uintptr_t)0 /* current */ 166 }, 167 }; 168 169 /* 170 * default trap buffer size 171 */ 172 size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t); 173 int trap_trace_freeze = 0; 174 int trap_trace_off = 0; 175 176 /* 177 * A dummy TRAPTRACE entry to use after death. 178 */ 179 trap_trace_rec_t trap_trace_postmort; 180 181 static void dump_ttrace(void); 182 #endif /* TRAPTRACE */ 183 static void dumpregs(struct regs *); 184 static void showregs(uint_t, struct regs *, caddr_t); 185 static int kern_gpfault(struct regs *); 186 187 /*ARGSUSED*/ 188 static int 189 die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid) 190 { 191 struct panic_trap_info ti; 192 const char *trap_name, *trap_mnemonic; 193 194 if (type < TRAP_TYPES) { 195 trap_name = trap_type[type]; 196 trap_mnemonic = trap_type_mnemonic[type]; 197 } else { 198 trap_name = "trap"; 199 trap_mnemonic = "-"; 200 } 201 202 #ifdef TRAPTRACE 203 TRAPTRACE_FREEZE; 204 #endif 205 206 ti.trap_regs = rp; 207 ti.trap_type = type & ~USER; 208 ti.trap_addr = addr; 209 210 curthread->t_panic_trap = &ti; 211 212 if (type == T_PGFLT && addr < (caddr_t)KERNELBASE) { 213 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p " 214 "occurred in module \"%s\" due to %s", 215 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr, 216 mod_containing_pc((caddr_t)rp->r_pc), 217 addr < (caddr_t)PAGESIZE ? 218 "a NULL pointer dereference" : 219 "an illegal access to a user address"); 220 } else 221 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p", 222 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr); 223 return (0); 224 } 225 226 /* 227 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction. 228 * 229 * int <vector> is two bytes: 0xCD <vector> 230 */ 231 232 static int 233 rewrite_syscall(caddr_t pc) 234 { 235 uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT }; 236 237 if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE, 238 (uintptr_t)pc) != 0) 239 return (1); 240 241 return (0); 242 } 243 244 /* 245 * Test to see if the instruction at pc is sysenter or syscall. The second 246 * argument should be the x86 feature flag corresponding to the expected 247 * instruction. 248 * 249 * sysenter is two bytes: 0x0F 0x34 250 * syscall is two bytes: 0x0F 0x05 251 * int $T_SYSCALLINT is two bytes: 0xCD 0x91 252 */ 253 254 static int 255 instr_is_other_syscall(caddr_t pc, int which) 256 { 257 uchar_t instr[FAST_SCALL_SIZE]; 258 259 ASSERT(which == X86_SEP || which == X86_ASYSC || which == 0xCD); 260 261 if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0) 262 return (0); 263 264 switch (which) { 265 case X86_SEP: 266 if (instr[0] == 0x0F && instr[1] == 0x34) 267 return (1); 268 break; 269 case X86_ASYSC: 270 if (instr[0] == 0x0F && instr[1] == 0x05) 271 return (1); 272 break; 273 case 0xCD: 274 if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT) 275 return (1); 276 break; 277 } 278 279 return (0); 280 } 281 282 static const char * 283 syscall_insn_string(int syscall_insn) 284 { 285 switch (syscall_insn) { 286 case X86_SEP: 287 return ("sysenter"); 288 case X86_ASYSC: 289 return ("syscall"); 290 case 0xCD: 291 return ("int"); 292 default: 293 return ("Unknown"); 294 } 295 } 296 297 static int 298 ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn) 299 { 300 caddr_t linearpc; 301 int return_code = 0; 302 303 mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */ 304 305 if (linear_pc(rp, p, &linearpc) == 0) { 306 307 /* 308 * If another thread beat us here, it already changed 309 * this site to the slower (int) syscall instruction. 310 */ 311 if (instr_is_other_syscall(linearpc, 0xCD)) { 312 return_code = 1; 313 } else if (instr_is_other_syscall(linearpc, syscall_insn)) { 314 315 if (rewrite_syscall(linearpc) == 0) { 316 return_code = 1; 317 } 318 #ifdef DEBUG 319 else 320 cmn_err(CE_WARN, "failed to rewrite %s " 321 "instruction in process %d", 322 syscall_insn_string(syscall_insn), 323 p->p_pid); 324 #endif /* DEBUG */ 325 } 326 } 327 328 mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */ 329 330 return (return_code); 331 } 332 333 /* 334 * Test to see if the instruction at pc is a system call instruction. 335 * 336 * The bytes of an lcall instruction used for the syscall trap. 337 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 }; 338 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 }; 339 */ 340 341 #define LCALLSIZE 7 342 343 static int 344 instr_is_lcall_syscall(caddr_t pc) 345 { 346 uchar_t instr[LCALLSIZE]; 347 348 if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 && 349 instr[0] == 0x9a && 350 instr[1] == 0 && 351 instr[2] == 0 && 352 instr[3] == 0 && 353 instr[4] == 0 && 354 (instr[5] == 0x7 || instr[5] == 0x27) && 355 instr[6] == 0) 356 return (1); 357 358 return (0); 359 } 360 361 #ifdef __amd64 362 363 /* 364 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and 365 * SAHF instructions were not implemented in 64-bit mode. Later revisions 366 * did implement these instructions. An extension to the cpuid instruction 367 * was added to check for the capability of executing these instructions 368 * in 64-bit mode. 369 * 370 * Intel originally did not implement these instructions in EM64T either, 371 * but added them in later revisions. 372 * 373 * So, there are different chip revisions by both vendors out there that 374 * may or may not implement these instructions. The easy solution is to 375 * just always emulate these instructions on demand. 376 * 377 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e) 378 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f) 379 */ 380 381 #define LSAHFSIZE 1 382 383 static int 384 instr_is_lsahf(caddr_t pc, uchar_t *instr) 385 { 386 if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 && 387 (*instr == 0x9e || *instr == 0x9f)) 388 return (1); 389 return (0); 390 } 391 392 /* 393 * Emulate the LAHF and SAHF instructions. The reference manuals define 394 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5 395 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P). 396 * 397 * Note that %ah is bits 8-15 of %rax. 398 */ 399 static void 400 emulate_lsahf(struct regs *rp, uchar_t instr) 401 { 402 if (instr == 0x9e) { 403 /* sahf. Copy bits from %ah to flags. */ 404 rp->r_ps = (rp->r_ps & ~0xff) | 405 ((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1; 406 } else { 407 /* lahf. Copy bits from flags to %ah. */ 408 rp->r_rax = (rp->r_rax & ~0xff00) | 409 (((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8); 410 } 411 rp->r_pc += LSAHFSIZE; 412 } 413 #endif /* __amd64 */ 414 415 #ifdef OPTERON_ERRATUM_91 416 417 /* 418 * Test to see if the instruction at pc is a prefetch instruction. 419 * 420 * The first byte of prefetch instructions is always 0x0F. 421 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch. 422 * The third byte (ModRM) contains the register field bits (bits 3-5). 423 * These bits must be between 0 and 3 inclusive for regular prefetch and 424 * 0 and 1 inclusive for AMD 3dnow prefetch. 425 * 426 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F). 427 */ 428 429 static int 430 cmp_to_prefetch(uchar_t *p) 431 { 432 #ifdef _LP64 433 if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */ 434 p++; 435 #endif 436 return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) || 437 (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1)); 438 } 439 440 static int 441 instr_is_prefetch(caddr_t pc) 442 { 443 uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */ 444 445 return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 && 446 cmp_to_prefetch(instr)); 447 } 448 449 #endif /* OPTERON_ERRATUM_91 */ 450 451 /* 452 * Called from the trap handler when a processor trap occurs. 453 * 454 * Note: All user-level traps that might call stop() must exit 455 * trap() by 'goto out' or by falling through. 456 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1) 457 * however, there are paths that arrive here with PS_IE == 0 so special care 458 * must be taken in those cases. 459 */ 460 void 461 trap(struct regs *rp, caddr_t addr, processorid_t cpuid) 462 { 463 kthread_t *ct = curthread; 464 enum seg_rw rw; 465 unsigned type; 466 proc_t *p = ttoproc(ct); 467 klwp_t *lwp = ttolwp(ct); 468 uintptr_t lofault; 469 faultcode_t pagefault(), res, errcode; 470 enum fault_type fault_type; 471 k_siginfo_t siginfo; 472 uint_t fault = 0; 473 int mstate; 474 int sicode = 0; 475 int watchcode; 476 int watchpage; 477 caddr_t vaddr; 478 int singlestep_twiddle; 479 size_t sz; 480 int ta; 481 #ifdef __amd64 482 uchar_t instr; 483 #endif 484 485 ASSERT_STACK_ALIGNED(); 486 487 type = rp->r_trapno; 488 CPU_STATS_ADDQ(CPU, sys, trap, 1); 489 ASSERT(ct->t_schedflag & TS_DONT_SWAP); 490 491 if (type == T_PGFLT) { 492 493 errcode = rp->r_err; 494 if (errcode & PF_ERR_WRITE) 495 rw = S_WRITE; 496 else if ((caddr_t)rp->r_pc == addr || 497 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) 498 rw = S_EXEC; 499 else 500 rw = S_READ; 501 502 #if defined(__i386) 503 /* 504 * Pentium Pro work-around 505 */ 506 if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) { 507 uint_t attr; 508 uint_t priv_violation; 509 uint_t access_violation; 510 511 if (hat_getattr(addr < (caddr_t)kernelbase ? 512 curproc->p_as->a_hat : kas.a_hat, addr, &attr) 513 == -1) { 514 errcode &= ~PF_ERR_PROT; 515 } else { 516 priv_violation = (errcode & PF_ERR_USER) && 517 !(attr & PROT_USER); 518 access_violation = (errcode & PF_ERR_WRITE) && 519 !(attr & PROT_WRITE); 520 if (!priv_violation && !access_violation) 521 goto cleanup; 522 } 523 } 524 #endif /* __i386 */ 525 526 } else if (type == T_SGLSTP && lwp != NULL) 527 lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr; 528 529 if (tdebug) 530 showregs(type, rp, addr); 531 532 if (USERMODE(rp->r_cs)) { 533 /* 534 * Set up the current cred to use during this trap. u_cred 535 * no longer exists. t_cred is used instead. 536 * The current process credential applies to the thread for 537 * the entire trap. If trapping from the kernel, this 538 * should already be set up. 539 */ 540 if (ct->t_cred != p->p_cred) { 541 cred_t *oldcred = ct->t_cred; 542 /* 543 * DTrace accesses t_cred in probe context. t_cred 544 * must always be either NULL, or point to a valid, 545 * allocated cred structure. 546 */ 547 ct->t_cred = crgetcred(); 548 crfree(oldcred); 549 } 550 ASSERT(lwp != NULL); 551 type |= USER; 552 ASSERT(lwptoregs(lwp) == rp); 553 lwp->lwp_state = LWP_SYS; 554 555 switch (type) { 556 case T_PGFLT + USER: 557 if ((caddr_t)rp->r_pc == addr) 558 mstate = LMS_TFAULT; 559 else 560 mstate = LMS_DFAULT; 561 break; 562 default: 563 mstate = LMS_TRAP; 564 break; 565 } 566 /* Kernel probe */ 567 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */, 568 tnf_microstate, state, mstate); 569 mstate = new_mstate(ct, mstate); 570 571 bzero(&siginfo, sizeof (siginfo)); 572 } 573 574 switch (type) { 575 case T_PGFLT + USER: 576 case T_SGLSTP: 577 case T_SGLSTP + USER: 578 case T_BPTFLT + USER: 579 break; 580 581 default: 582 FTRACE_2("trap(): type=0x%lx, regs=0x%lx", 583 (ulong_t)type, (ulong_t)rp); 584 break; 585 } 586 587 switch (type) { 588 case T_SIMDFPE: 589 /* Make sure we enable interrupts before die()ing */ 590 sti(); /* The SIMD exception comes in via cmninttrap */ 591 /*FALLTHROUGH*/ 592 default: 593 if (type & USER) { 594 if (tudebug) 595 showregs(type, rp, (caddr_t)0); 596 printf("trap: Unknown trap type %d in user mode\n", 597 type & ~USER); 598 siginfo.si_signo = SIGILL; 599 siginfo.si_code = ILL_ILLTRP; 600 siginfo.si_addr = (caddr_t)rp->r_pc; 601 siginfo.si_trapno = type & ~USER; 602 fault = FLTILL; 603 break; 604 } else { 605 (void) die(type, rp, addr, cpuid); 606 /*NOTREACHED*/ 607 } 608 609 case T_PGFLT: /* system page fault */ 610 /* 611 * If we're under on_trap() protection (see <sys/ontrap.h>), 612 * set ot_trap and bounce back to the on_trap() call site 613 * via the installed trampoline. 614 */ 615 if ((ct->t_ontrap != NULL) && 616 (ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) { 617 ct->t_ontrap->ot_trap |= OT_DATA_ACCESS; 618 rp->r_pc = ct->t_ontrap->ot_trampoline; 619 goto cleanup; 620 } 621 622 /* 623 * See if we can handle as pagefault. Save lofault 624 * across this. Here we assume that an address 625 * less than KERNELBASE is a user fault. 626 * We can do this as copy.s routines verify that the 627 * starting address is less than KERNELBASE before 628 * starting and because we know that we always have 629 * KERNELBASE mapped as invalid to serve as a "barrier". 630 */ 631 lofault = ct->t_lofault; 632 ct->t_lofault = 0; 633 634 mstate = new_mstate(ct, LMS_KFAULT); 635 636 if (addr < (caddr_t)kernelbase) { 637 res = pagefault(addr, 638 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0); 639 if (res == FC_NOMAP && 640 addr < p->p_usrstack && 641 grow(addr)) 642 res = 0; 643 } else { 644 res = pagefault(addr, 645 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1); 646 } 647 (void) new_mstate(ct, mstate); 648 649 /* 650 * Restore lofault. If we resolved the fault, exit. 651 * If we didn't and lofault wasn't set, die. 652 */ 653 ct->t_lofault = lofault; 654 if (res == 0) 655 goto cleanup; 656 657 #if defined(OPTERON_ERRATUM_93) && defined(_LP64) 658 if (lofault == 0 && opteron_erratum_93) { 659 /* 660 * Workaround for Opteron Erratum 93. On return from 661 * a System Managment Interrupt at a HLT instruction 662 * the %rip might be truncated to a 32 bit value. 663 * BIOS is supposed to fix this, but some don't. 664 * If this occurs we simply restore the high order bits. 665 * The HLT instruction is 1 byte of 0xf4. 666 */ 667 uintptr_t rip = rp->r_pc; 668 669 if ((rip & 0xfffffffful) == rip) { 670 rip |= 0xfffffffful << 32; 671 if (hat_getpfnum(kas.a_hat, (caddr_t)rip) != 672 PFN_INVALID && 673 (*(uchar_t *)rip == 0xf4 || 674 *(uchar_t *)(rip - 1) == 0xf4)) { 675 rp->r_pc = rip; 676 goto cleanup; 677 } 678 } 679 } 680 #endif /* OPTERON_ERRATUM_93 && _LP64 */ 681 682 #ifdef OPTERON_ERRATUM_91 683 if (lofault == 0 && opteron_erratum_91) { 684 /* 685 * Workaround for Opteron Erratum 91. Prefetches may 686 * generate a page fault (they're not supposed to do 687 * that!). If this occurs we simply return back to the 688 * instruction. 689 */ 690 caddr_t pc = (caddr_t)rp->r_pc; 691 692 /* 693 * If the faulting PC is not mapped, this is a 694 * legitimate kernel page fault that must result in a 695 * panic. If the faulting PC is mapped, it could contain 696 * a prefetch instruction. Check for that here. 697 */ 698 if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) { 699 if (cmp_to_prefetch((uchar_t *)pc)) { 700 #ifdef DEBUG 701 cmn_err(CE_WARN, "Opteron erratum 91 " 702 "occurred: kernel prefetch" 703 " at %p generated a page fault!", 704 (void *)rp->r_pc); 705 #endif /* DEBUG */ 706 goto cleanup; 707 } 708 } 709 (void) die(type, rp, addr, cpuid); 710 } 711 #endif /* OPTERON_ERRATUM_91 */ 712 713 if (lofault == 0) 714 (void) die(type, rp, addr, cpuid); 715 716 /* 717 * Cannot resolve fault. Return to lofault. 718 */ 719 if (lodebug) { 720 showregs(type, rp, addr); 721 traceregs(rp); 722 } 723 if (FC_CODE(res) == FC_OBJERR) 724 res = FC_ERRNO(res); 725 else 726 res = EFAULT; 727 rp->r_r0 = res; 728 rp->r_pc = ct->t_lofault; 729 goto cleanup; 730 731 case T_PGFLT + USER: /* user page fault */ 732 if (faultdebug) { 733 char *fault_str; 734 735 switch (rw) { 736 case S_READ: 737 fault_str = "read"; 738 break; 739 case S_WRITE: 740 fault_str = "write"; 741 break; 742 case S_EXEC: 743 fault_str = "exec"; 744 break; 745 default: 746 fault_str = ""; 747 break; 748 } 749 printf("user %s fault: addr=0x%lx errcode=0x%x\n", 750 fault_str, (uintptr_t)addr, errcode); 751 } 752 753 #if defined(OPTERON_ERRATUM_100) && defined(_LP64) 754 /* 755 * Workaround for AMD erratum 100 756 * 757 * A 32-bit process may receive a page fault on a non 758 * 32-bit address by mistake. The range of the faulting 759 * address will be 760 * 761 * 0xffffffff80000000 .. 0xffffffffffffffff or 762 * 0x0000000100000000 .. 0x000000017fffffff 763 * 764 * The fault is always due to an instruction fetch, however 765 * the value of r_pc should be correct (in 32 bit range), 766 * so we ignore the page fault on the bogus address. 767 */ 768 if (p->p_model == DATAMODEL_ILP32 && 769 (0xffffffff80000000 <= (uintptr_t)addr || 770 (0x100000000 <= (uintptr_t)addr && 771 (uintptr_t)addr <= 0x17fffffff))) { 772 if (!opteron_erratum_100) 773 panic("unexpected erratum #100"); 774 if (rp->r_pc <= 0xffffffff) 775 goto out; 776 } 777 #endif /* OPTERON_ERRATUM_100 && _LP64 */ 778 779 ASSERT(!(curthread->t_flag & T_WATCHPT)); 780 watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw)); 781 #ifdef __i386 782 /* 783 * In 32-bit mode, the lcall (system call) instruction fetches 784 * one word from the stack, at the stack pointer, because of the 785 * way the call gate is constructed. This is a bogus 786 * read and should not be counted as a read watchpoint. 787 * We work around the problem here by testing to see if 788 * this situation applies and, if so, simply jumping to 789 * the code in locore.s that fields the system call trap. 790 * The registers on the stack are already set up properly 791 * due to the match between the call gate sequence and the 792 * trap gate sequence. We just have to adjust the pc. 793 */ 794 if (watchpage && addr == (caddr_t)rp->r_sp && 795 rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) { 796 extern void watch_syscall(void); 797 798 rp->r_pc += LCALLSIZE; 799 watch_syscall(); /* never returns */ 800 /* NOTREACHED */ 801 } 802 #endif /* __i386 */ 803 vaddr = addr; 804 if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0) 805 fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL; 806 else if ((watchcode = pr_is_watchpoint(&vaddr, &ta, 807 sz, NULL, rw)) != 0) { 808 if (ta) { 809 do_watch_step(vaddr, sz, rw, 810 watchcode, rp->r_pc); 811 fault_type = F_INVAL; 812 } else { 813 bzero(&siginfo, sizeof (siginfo)); 814 siginfo.si_signo = SIGTRAP; 815 siginfo.si_code = watchcode; 816 siginfo.si_addr = vaddr; 817 siginfo.si_trapafter = 0; 818 siginfo.si_pc = (caddr_t)rp->r_pc; 819 fault = FLTWATCH; 820 break; 821 } 822 } else { 823 /* XXX pr_watch_emul() never succeeds (for now) */ 824 if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw)) 825 goto out; 826 do_watch_step(vaddr, sz, rw, 0, 0); 827 fault_type = F_INVAL; 828 } 829 830 res = pagefault(addr, fault_type, rw, 0); 831 832 /* 833 * If pagefault() succeeded, ok. 834 * Otherwise attempt to grow the stack. 835 */ 836 if (res == 0 || 837 (res == FC_NOMAP && 838 addr < p->p_usrstack && 839 grow(addr))) { 840 lwp->lwp_lastfault = FLTPAGE; 841 lwp->lwp_lastfaddr = addr; 842 if (prismember(&p->p_fltmask, FLTPAGE)) { 843 bzero(&siginfo, sizeof (siginfo)); 844 siginfo.si_addr = addr; 845 (void) stop_on_fault(FLTPAGE, &siginfo); 846 } 847 goto out; 848 } else if (res == FC_PROT && addr < p->p_usrstack && 849 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) { 850 report_stack_exec(p, addr); 851 } 852 853 #ifdef OPTERON_ERRATUM_91 854 /* 855 * Workaround for Opteron Erratum 91. Prefetches may generate a 856 * page fault (they're not supposed to do that!). If this 857 * occurs we simply return back to the instruction. 858 * 859 * We rely on copyin to properly fault in the page with r_pc. 860 */ 861 if (opteron_erratum_91 && 862 addr != (caddr_t)rp->r_pc && 863 instr_is_prefetch((caddr_t)rp->r_pc)) { 864 #ifdef DEBUG 865 cmn_err(CE_WARN, "Opteron erratum 91 occurred: " 866 "prefetch at %p in pid %d generated a trap!", 867 (void *)rp->r_pc, p->p_pid); 868 #endif /* DEBUG */ 869 goto out; 870 } 871 #endif /* OPTERON_ERRATUM_91 */ 872 873 if (tudebug) 874 showregs(type, rp, addr); 875 /* 876 * In the case where both pagefault and grow fail, 877 * set the code to the value provided by pagefault. 878 * We map all errors returned from pagefault() to SIGSEGV. 879 */ 880 bzero(&siginfo, sizeof (siginfo)); 881 siginfo.si_addr = addr; 882 switch (FC_CODE(res)) { 883 case FC_HWERR: 884 case FC_NOSUPPORT: 885 siginfo.si_signo = SIGBUS; 886 siginfo.si_code = BUS_ADRERR; 887 fault = FLTACCESS; 888 break; 889 case FC_ALIGN: 890 siginfo.si_signo = SIGBUS; 891 siginfo.si_code = BUS_ADRALN; 892 fault = FLTACCESS; 893 break; 894 case FC_OBJERR: 895 if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) { 896 siginfo.si_signo = SIGBUS; 897 siginfo.si_code = BUS_OBJERR; 898 fault = FLTACCESS; 899 } 900 break; 901 default: /* FC_NOMAP or FC_PROT */ 902 siginfo.si_signo = SIGSEGV; 903 siginfo.si_code = 904 (res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR; 905 fault = FLTBOUNDS; 906 break; 907 } 908 break; 909 910 case T_ILLINST + USER: /* invalid opcode fault */ 911 /* 912 * If the syscall instruction is disabled due to LDT usage, a 913 * user program that attempts to execute it will trigger a #ud 914 * trap. Check for that case here. If this occurs on a CPU which 915 * doesn't even support syscall, the result of all of this will 916 * be to emulate that particular instruction. 917 */ 918 if (p->p_ldt != NULL && 919 ldt_rewrite_syscall(rp, p, X86_ASYSC)) 920 goto out; 921 922 #ifdef __amd64 923 /* 924 * Emulate the LAHF and SAHF instructions if needed. 925 * See the instr_is_lsahf function for details. 926 */ 927 if (p->p_model == DATAMODEL_LP64 && 928 instr_is_lsahf((caddr_t)rp->r_pc, &instr)) { 929 emulate_lsahf(rp, instr); 930 goto out; 931 } 932 #endif 933 934 /*FALLTHROUGH*/ 935 936 if (tudebug) 937 showregs(type, rp, (caddr_t)0); 938 siginfo.si_signo = SIGILL; 939 siginfo.si_code = ILL_ILLOPC; 940 siginfo.si_addr = (caddr_t)rp->r_pc; 941 fault = FLTILL; 942 break; 943 944 case T_ZERODIV + USER: /* integer divide by zero */ 945 if (tudebug && tudebugfpe) 946 showregs(type, rp, (caddr_t)0); 947 siginfo.si_signo = SIGFPE; 948 siginfo.si_code = FPE_INTDIV; 949 siginfo.si_addr = (caddr_t)rp->r_pc; 950 fault = FLTIZDIV; 951 break; 952 953 case T_OVFLW + USER: /* integer overflow */ 954 if (tudebug && tudebugfpe) 955 showregs(type, rp, (caddr_t)0); 956 siginfo.si_signo = SIGFPE; 957 siginfo.si_code = FPE_INTOVF; 958 siginfo.si_addr = (caddr_t)rp->r_pc; 959 fault = FLTIOVF; 960 break; 961 962 case T_NOEXTFLT + USER: /* math coprocessor not available */ 963 if (tudebug && tudebugfpe) 964 showregs(type, rp, addr); 965 if (fpnoextflt(rp)) { 966 siginfo.si_signo = SIGILL; 967 siginfo.si_code = ILL_ILLOPC; 968 siginfo.si_addr = (caddr_t)rp->r_pc; 969 fault = FLTILL; 970 } 971 break; 972 973 case T_EXTOVRFLT: /* extension overrun fault */ 974 /* check if we took a kernel trap on behalf of user */ 975 { 976 extern void ndptrap_frstor(void); 977 if (rp->r_pc != (uintptr_t)ndptrap_frstor) { 978 sti(); /* T_EXTOVRFLT comes in via cmninttrap */ 979 (void) die(type, rp, addr, cpuid); 980 } 981 type |= USER; 982 } 983 /*FALLTHROUGH*/ 984 case T_EXTOVRFLT + USER: /* extension overrun fault */ 985 if (tudebug && tudebugfpe) 986 showregs(type, rp, addr); 987 if (fpextovrflt(rp)) { 988 siginfo.si_signo = SIGSEGV; 989 siginfo.si_code = SEGV_MAPERR; 990 siginfo.si_addr = (caddr_t)rp->r_pc; 991 fault = FLTBOUNDS; 992 } 993 break; 994 995 case T_EXTERRFLT: /* x87 floating point exception pending */ 996 /* check if we took a kernel trap on behalf of user */ 997 { 998 extern void ndptrap_frstor(void); 999 if (rp->r_pc != (uintptr_t)ndptrap_frstor) { 1000 sti(); /* T_EXTERRFLT comes in via cmninttrap */ 1001 (void) die(type, rp, addr, cpuid); 1002 } 1003 type |= USER; 1004 } 1005 /*FALLTHROUGH*/ 1006 1007 case T_EXTERRFLT + USER: /* x87 floating point exception pending */ 1008 if (tudebug && tudebugfpe) 1009 showregs(type, rp, addr); 1010 if (sicode = fpexterrflt(rp)) { 1011 siginfo.si_signo = SIGFPE; 1012 siginfo.si_code = sicode; 1013 siginfo.si_addr = (caddr_t)rp->r_pc; 1014 fault = FLTFPE; 1015 } 1016 break; 1017 1018 case T_SIMDFPE + USER: /* SSE and SSE2 exceptions */ 1019 if (tudebug && tudebugsse) 1020 showregs(type, rp, addr); 1021 if ((x86_feature & (X86_SSE|X86_SSE2)) == 0) { 1022 /* 1023 * There are rumours that some user instructions 1024 * on older CPUs can cause this trap to occur; in 1025 * which case send a SIGILL instead of a SIGFPE. 1026 */ 1027 siginfo.si_signo = SIGILL; 1028 siginfo.si_code = ILL_ILLTRP; 1029 siginfo.si_addr = (caddr_t)rp->r_pc; 1030 siginfo.si_trapno = type & ~USER; 1031 fault = FLTILL; 1032 } else if ((sicode = fpsimderrflt(rp)) != 0) { 1033 siginfo.si_signo = SIGFPE; 1034 siginfo.si_code = sicode; 1035 siginfo.si_addr = (caddr_t)rp->r_pc; 1036 fault = FLTFPE; 1037 } 1038 1039 sti(); /* The SIMD exception comes in via cmninttrap */ 1040 break; 1041 1042 case T_BPTFLT: /* breakpoint trap */ 1043 /* 1044 * Kernel breakpoint traps should only happen when kmdb is 1045 * active, and even then, it'll have interposed on the IDT, so 1046 * control won't get here. If it does, we've hit a breakpoint 1047 * without the debugger, which is very strange, and very 1048 * fatal. 1049 */ 1050 if (tudebug && tudebugbpt) 1051 showregs(type, rp, (caddr_t)0); 1052 1053 (void) die(type, rp, addr, cpuid); 1054 break; 1055 1056 case T_SGLSTP: /* single step/hw breakpoint exception */ 1057 1058 /* Now evaluate how we got here */ 1059 if (lwp != NULL && (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP)) { 1060 /* 1061 * i386 single-steps even through lcalls which 1062 * change the privilege level. So we take a trap at 1063 * the first instruction in privileged mode. 1064 * 1065 * Set a flag to indicate that upon completion of 1066 * the system call, deal with the single-step trap. 1067 * 1068 * The same thing happens for sysenter, too. 1069 */ 1070 singlestep_twiddle = 0; 1071 if (rp->r_pc == (uintptr_t)sys_sysenter || 1072 rp->r_pc == (uintptr_t)brand_sys_sysenter) { 1073 singlestep_twiddle = 1; 1074 #if defined(__amd64) 1075 /* 1076 * Since we are already on the kernel's 1077 * %gs, on 64-bit systems the sysenter case 1078 * needs to adjust the pc to avoid 1079 * executing the swapgs instruction at the 1080 * top of the handler. 1081 */ 1082 if (rp->r_pc == (uintptr_t)sys_sysenter) 1083 rp->r_pc = (uintptr_t) 1084 _sys_sysenter_post_swapgs; 1085 else 1086 rp->r_pc = (uintptr_t) 1087 _brand_sys_sysenter_post_swapgs; 1088 #endif 1089 } 1090 #if defined(__i386) 1091 else if (rp->r_pc == (uintptr_t)sys_call || 1092 rp->r_pc == (uintptr_t)brand_sys_call) { 1093 singlestep_twiddle = 1; 1094 } 1095 #endif 1096 else { 1097 /* not on sysenter/syscall; uregs available */ 1098 if (tudebug && tudebugbpt) 1099 showregs(type, rp, (caddr_t)0); 1100 } 1101 if (singlestep_twiddle) { 1102 rp->r_ps &= ~PS_T; /* turn off trace */ 1103 lwp->lwp_pcb.pcb_flags |= DEBUG_PENDING; 1104 ct->t_post_sys = 1; 1105 aston(curthread); 1106 goto cleanup; 1107 } 1108 } 1109 /* XXX - needs review on debugger interface? */ 1110 if (boothowto & RB_DEBUG) 1111 debug_enter((char *)NULL); 1112 else 1113 (void) die(type, rp, addr, cpuid); 1114 break; 1115 1116 case T_NMIFLT: /* NMI interrupt */ 1117 printf("Unexpected NMI in system mode\n"); 1118 goto cleanup; 1119 1120 case T_NMIFLT + USER: /* NMI interrupt */ 1121 printf("Unexpected NMI in user mode\n"); 1122 break; 1123 1124 case T_GPFLT: /* general protection violation */ 1125 /* 1126 * Any #GP that occurs during an on_trap .. no_trap bracket 1127 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection, 1128 * or in a on_fault .. no_fault bracket, is forgiven 1129 * and we trampoline. This protection is given regardless 1130 * of whether we are 32/64 bit etc - if a distinction is 1131 * required then define new on_trap protection types. 1132 * 1133 * On amd64, we can get a #gp from referencing addresses 1134 * in the virtual address hole e.g. from a copyin or in 1135 * update_sregs while updating user segment registers. 1136 * 1137 * On the 32-bit hypervisor we could also generate one in 1138 * mfn_to_pfn by reaching around or into where the hypervisor 1139 * lives which is protected by segmentation. 1140 */ 1141 1142 /* 1143 * If we're under on_trap() protection (see <sys/ontrap.h>), 1144 * set ot_trap and trampoline back to the on_trap() call site 1145 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS. 1146 */ 1147 if (ct->t_ontrap != NULL) { 1148 int ttype = ct->t_ontrap->ot_prot & 1149 (OT_DATA_ACCESS | OT_SEGMENT_ACCESS); 1150 1151 if (ttype != 0) { 1152 ct->t_ontrap->ot_trap |= ttype; 1153 if (tudebug) 1154 showregs(type, rp, (caddr_t)0); 1155 rp->r_pc = ct->t_ontrap->ot_trampoline; 1156 goto cleanup; 1157 } 1158 } 1159 1160 /* 1161 * If we're under lofault protection (copyin etc.), 1162 * longjmp back to lofault with an EFAULT. 1163 */ 1164 if (ct->t_lofault) { 1165 /* 1166 * Fault is not resolvable, so just return to lofault 1167 */ 1168 if (lodebug) { 1169 showregs(type, rp, addr); 1170 traceregs(rp); 1171 } 1172 rp->r_r0 = EFAULT; 1173 rp->r_pc = ct->t_lofault; 1174 goto cleanup; 1175 } 1176 1177 /* 1178 * We fall through to the next case, which repeats 1179 * the OT_SEGMENT_ACCESS check which we've already 1180 * done, so we'll always fall through to the 1181 * T_STKFLT case. 1182 */ 1183 /*FALLTHROUGH*/ 1184 case T_SEGFLT: /* segment not present fault */ 1185 /* 1186 * One example of this is #NP in update_sregs while 1187 * attempting to update a user segment register 1188 * that points to a descriptor that is marked not 1189 * present. 1190 */ 1191 if (ct->t_ontrap != NULL && 1192 ct->t_ontrap->ot_prot & OT_SEGMENT_ACCESS) { 1193 ct->t_ontrap->ot_trap |= OT_SEGMENT_ACCESS; 1194 if (tudebug) 1195 showregs(type, rp, (caddr_t)0); 1196 rp->r_pc = ct->t_ontrap->ot_trampoline; 1197 goto cleanup; 1198 } 1199 /*FALLTHROUGH*/ 1200 case T_STKFLT: /* stack fault */ 1201 case T_TSSFLT: /* invalid TSS fault */ 1202 if (tudebug) 1203 showregs(type, rp, (caddr_t)0); 1204 if (kern_gpfault(rp)) 1205 (void) die(type, rp, addr, cpuid); 1206 goto cleanup; 1207 1208 /* 1209 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps 1210 * should have no need for them, so we put a stop to it here. 1211 * 1212 * So: not-present fault is ONLY valid for 32-bit processes with 1213 * a private LDT trying to do a system call. Emulate it. 1214 * 1215 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT 1216 * have a private LDT, and are trying to do a system call. Emulate it. 1217 */ 1218 1219 case T_SEGFLT + USER: /* segment not present fault */ 1220 case T_GPFLT + USER: /* general protection violation */ 1221 #ifdef _SYSCALL32_IMPL 1222 if (p->p_model != DATAMODEL_NATIVE) { 1223 #endif /* _SYSCALL32_IMPL */ 1224 if (instr_is_lcall_syscall((caddr_t)rp->r_pc)) { 1225 if (type == T_SEGFLT + USER) 1226 ASSERT(p->p_ldt != NULL); 1227 1228 if ((p->p_ldt == NULL && type == T_GPFLT + USER) || 1229 type == T_SEGFLT + USER) { 1230 1231 /* 1232 * The user attempted a system call via the obsolete 1233 * call gate mechanism. Because the process doesn't have 1234 * an LDT (i.e. the ldtr contains 0), a #gp results. 1235 * Emulate the syscall here, just as we do above for a 1236 * #np trap. 1237 */ 1238 1239 /* 1240 * Since this is a not-present trap, rp->r_pc points to 1241 * the trapping lcall instruction. We need to bump it 1242 * to the next insn so the app can continue on. 1243 */ 1244 rp->r_pc += LCALLSIZE; 1245 lwp->lwp_regs = rp; 1246 1247 /* 1248 * Normally the microstate of the LWP is forced back to 1249 * LMS_USER by the syscall handlers. Emulate that 1250 * behavior here. 1251 */ 1252 mstate = LMS_USER; 1253 1254 dosyscall(); 1255 goto out; 1256 } 1257 } 1258 #ifdef _SYSCALL32_IMPL 1259 } 1260 #endif /* _SYSCALL32_IMPL */ 1261 /* 1262 * If the current process is using a private LDT and the 1263 * trapping instruction is sysenter, the sysenter instruction 1264 * has been disabled on the CPU because it destroys segment 1265 * registers. If this is the case, rewrite the instruction to 1266 * be a safe system call and retry it. If this occurs on a CPU 1267 * which doesn't even support sysenter, the result of all of 1268 * this will be to emulate that particular instruction. 1269 */ 1270 if (p->p_ldt != NULL && 1271 ldt_rewrite_syscall(rp, p, X86_SEP)) 1272 goto out; 1273 1274 /*FALLTHROUGH*/ 1275 1276 case T_BOUNDFLT + USER: /* bound fault */ 1277 case T_STKFLT + USER: /* stack fault */ 1278 case T_TSSFLT + USER: /* invalid TSS fault */ 1279 if (tudebug) 1280 showregs(type, rp, (caddr_t)0); 1281 siginfo.si_signo = SIGSEGV; 1282 siginfo.si_code = SEGV_MAPERR; 1283 siginfo.si_addr = (caddr_t)rp->r_pc; 1284 fault = FLTBOUNDS; 1285 break; 1286 1287 case T_ALIGNMENT + USER: /* user alignment error (486) */ 1288 if (tudebug) 1289 showregs(type, rp, (caddr_t)0); 1290 bzero(&siginfo, sizeof (siginfo)); 1291 siginfo.si_signo = SIGBUS; 1292 siginfo.si_code = BUS_ADRALN; 1293 siginfo.si_addr = (caddr_t)rp->r_pc; 1294 fault = FLTACCESS; 1295 break; 1296 1297 case T_SGLSTP + USER: /* single step/hw breakpoint exception */ 1298 if (tudebug && tudebugbpt) 1299 showregs(type, rp, (caddr_t)0); 1300 1301 /* Was it single-stepping? */ 1302 if (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP) { 1303 pcb_t *pcb = &lwp->lwp_pcb; 1304 1305 rp->r_ps &= ~PS_T; 1306 /* 1307 * If both NORMAL_STEP and WATCH_STEP are in effect, 1308 * give precedence to WATCH_STEP. If neither is set, 1309 * user must have set the PS_T bit in %efl; treat this 1310 * as NORMAL_STEP. 1311 */ 1312 if ((fault = undo_watch_step(&siginfo)) == 0 && 1313 ((pcb->pcb_flags & NORMAL_STEP) || 1314 !(pcb->pcb_flags & WATCH_STEP))) { 1315 siginfo.si_signo = SIGTRAP; 1316 siginfo.si_code = TRAP_TRACE; 1317 siginfo.si_addr = (caddr_t)rp->r_pc; 1318 fault = FLTTRACE; 1319 } 1320 pcb->pcb_flags &= ~(NORMAL_STEP|WATCH_STEP); 1321 } 1322 break; 1323 1324 case T_BPTFLT + USER: /* breakpoint trap */ 1325 if (tudebug && tudebugbpt) 1326 showregs(type, rp, (caddr_t)0); 1327 /* 1328 * int 3 (the breakpoint instruction) leaves the pc referring 1329 * to the address one byte after the breakpointed address. 1330 * If the P_PR_BPTADJ flag has been set via /proc, We adjust 1331 * it back so it refers to the breakpointed address. 1332 */ 1333 if (p->p_proc_flag & P_PR_BPTADJ) 1334 rp->r_pc--; 1335 siginfo.si_signo = SIGTRAP; 1336 siginfo.si_code = TRAP_BRKPT; 1337 siginfo.si_addr = (caddr_t)rp->r_pc; 1338 fault = FLTBPT; 1339 break; 1340 1341 case T_AST: 1342 /* 1343 * This occurs only after the cs register has been made to 1344 * look like a kernel selector, either through debugging or 1345 * possibly by functions like setcontext(). The thread is 1346 * about to cause a general protection fault at common_iret() 1347 * in locore. We let that happen immediately instead of 1348 * doing the T_AST processing. 1349 */ 1350 goto cleanup; 1351 1352 case T_AST + USER: /* profiling, resched, h/w error pseudo trap */ 1353 if (lwp->lwp_pcb.pcb_flags & ASYNC_HWERR) { 1354 proc_t *p = ttoproc(curthread); 1355 extern void print_msg_hwerr(ctid_t ct_id, proc_t *p); 1356 1357 lwp->lwp_pcb.pcb_flags &= ~ASYNC_HWERR; 1358 print_msg_hwerr(p->p_ct_process->conp_contract.ct_id, 1359 p); 1360 contract_process_hwerr(p->p_ct_process, p); 1361 siginfo.si_signo = SIGKILL; 1362 siginfo.si_code = SI_NOINFO; 1363 } else if (lwp->lwp_pcb.pcb_flags & CPC_OVERFLOW) { 1364 lwp->lwp_pcb.pcb_flags &= ~CPC_OVERFLOW; 1365 if (kcpc_overflow_ast()) { 1366 /* 1367 * Signal performance counter overflow 1368 */ 1369 if (tudebug) 1370 showregs(type, rp, (caddr_t)0); 1371 bzero(&siginfo, sizeof (siginfo)); 1372 siginfo.si_signo = SIGEMT; 1373 siginfo.si_code = EMT_CPCOVF; 1374 siginfo.si_addr = (caddr_t)rp->r_pc; 1375 fault = FLTCPCOVF; 1376 } 1377 } 1378 1379 break; 1380 } 1381 1382 /* 1383 * We can't get here from a system trap 1384 */ 1385 ASSERT(type & USER); 1386 1387 if (fault) { 1388 /* We took a fault so abort single step. */ 1389 lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP); 1390 /* 1391 * Remember the fault and fault adddress 1392 * for real-time (SIGPROF) profiling. 1393 */ 1394 lwp->lwp_lastfault = fault; 1395 lwp->lwp_lastfaddr = siginfo.si_addr; 1396 1397 DTRACE_PROC2(fault, int, fault, ksiginfo_t *, &siginfo); 1398 1399 /* 1400 * If a debugger has declared this fault to be an 1401 * event of interest, stop the lwp. Otherwise just 1402 * deliver the associated signal. 1403 */ 1404 if (siginfo.si_signo != SIGKILL && 1405 prismember(&p->p_fltmask, fault) && 1406 stop_on_fault(fault, &siginfo) == 0) 1407 siginfo.si_signo = 0; 1408 } 1409 1410 if (siginfo.si_signo) 1411 trapsig(&siginfo, (fault != FLTFPE && fault != FLTCPCOVF)); 1412 1413 if (lwp->lwp_oweupc) 1414 profil_tick(rp->r_pc); 1415 1416 if (ct->t_astflag | ct->t_sig_check) { 1417 /* 1418 * Turn off the AST flag before checking all the conditions that 1419 * may have caused an AST. This flag is on whenever a signal or 1420 * unusual condition should be handled after the next trap or 1421 * syscall. 1422 */ 1423 astoff(ct); 1424 /* 1425 * If a single-step trap occurred on a syscall (see above) 1426 * recognize it now. Do this before checking for signals 1427 * because deferred_singlestep_trap() may generate a SIGTRAP to 1428 * the LWP or may otherwise mark the LWP to call issig(FORREAL). 1429 */ 1430 if (lwp->lwp_pcb.pcb_flags & DEBUG_PENDING) 1431 deferred_singlestep_trap((caddr_t)rp->r_pc); 1432 1433 ct->t_sig_check = 0; 1434 1435 mutex_enter(&p->p_lock); 1436 if (curthread->t_proc_flag & TP_CHANGEBIND) { 1437 timer_lwpbind(); 1438 curthread->t_proc_flag &= ~TP_CHANGEBIND; 1439 } 1440 mutex_exit(&p->p_lock); 1441 1442 /* 1443 * for kaio requests that are on the per-process poll queue, 1444 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel 1445 * should copyout their result_t to user memory. by copying 1446 * out the result_t, the user can poll on memory waiting 1447 * for the kaio request to complete. 1448 */ 1449 if (p->p_aio) 1450 aio_cleanup(0); 1451 /* 1452 * If this LWP was asked to hold, call holdlwp(), which will 1453 * stop. holdlwps() sets this up and calls pokelwps() which 1454 * sets the AST flag. 1455 * 1456 * Also check TP_EXITLWP, since this is used by fresh new LWPs 1457 * through lwp_rtt(). That flag is set if the lwp_create(2) 1458 * syscall failed after creating the LWP. 1459 */ 1460 if (ISHOLD(p)) 1461 holdlwp(); 1462 1463 /* 1464 * All code that sets signals and makes ISSIG evaluate true must 1465 * set t_astflag afterwards. 1466 */ 1467 if (ISSIG_PENDING(ct, lwp, p)) { 1468 if (issig(FORREAL)) 1469 psig(); 1470 ct->t_sig_check = 1; 1471 } 1472 1473 if (ct->t_rprof != NULL) { 1474 realsigprof(0, 0, 0); 1475 ct->t_sig_check = 1; 1476 } 1477 1478 /* 1479 * /proc can't enable/disable the trace bit itself 1480 * because that could race with the call gate used by 1481 * system calls via "lcall". If that happened, an 1482 * invalid EFLAGS would result. prstep()/prnostep() 1483 * therefore schedule an AST for the purpose. 1484 */ 1485 if (lwp->lwp_pcb.pcb_flags & REQUEST_STEP) { 1486 lwp->lwp_pcb.pcb_flags &= ~REQUEST_STEP; 1487 rp->r_ps |= PS_T; 1488 } 1489 if (lwp->lwp_pcb.pcb_flags & REQUEST_NOSTEP) { 1490 lwp->lwp_pcb.pcb_flags &= ~REQUEST_NOSTEP; 1491 rp->r_ps &= ~PS_T; 1492 } 1493 } 1494 1495 out: /* We can't get here from a system trap */ 1496 ASSERT(type & USER); 1497 1498 if (ISHOLD(p)) 1499 holdlwp(); 1500 1501 /* 1502 * Set state to LWP_USER here so preempt won't give us a kernel 1503 * priority if it occurs after this point. Call CL_TRAPRET() to 1504 * restore the user-level priority. 1505 * 1506 * It is important that no locks (other than spinlocks) be entered 1507 * after this point before returning to user mode (unless lwp_state 1508 * is set back to LWP_SYS). 1509 */ 1510 lwp->lwp_state = LWP_USER; 1511 1512 if (ct->t_trapret) { 1513 ct->t_trapret = 0; 1514 thread_lock(ct); 1515 CL_TRAPRET(ct); 1516 thread_unlock(ct); 1517 } 1518 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ) 1519 preempt(); 1520 prunstop(); 1521 (void) new_mstate(ct, mstate); 1522 1523 /* Kernel probe */ 1524 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */, 1525 tnf_microstate, state, LMS_USER); 1526 1527 return; 1528 1529 cleanup: /* system traps end up here */ 1530 ASSERT(!(type & USER)); 1531 } 1532 1533 /* 1534 * Patch non-zero to disable preemption of threads in the kernel. 1535 */ 1536 int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */ 1537 1538 struct kpreempt_cnts { /* kernel preemption statistics */ 1539 int kpc_idle; /* executing idle thread */ 1540 int kpc_intr; /* executing interrupt thread */ 1541 int kpc_clock; /* executing clock thread */ 1542 int kpc_blocked; /* thread has blocked preemption (t_preempt) */ 1543 int kpc_notonproc; /* thread is surrendering processor */ 1544 int kpc_inswtch; /* thread has ratified scheduling decision */ 1545 int kpc_prilevel; /* processor interrupt level is too high */ 1546 int kpc_apreempt; /* asynchronous preemption */ 1547 int kpc_spreempt; /* synchronous preemption */ 1548 } kpreempt_cnts; 1549 1550 /* 1551 * kernel preemption: forced rescheduling, preempt the running kernel thread. 1552 * the argument is old PIL for an interrupt, 1553 * or the distingished value KPREEMPT_SYNC. 1554 */ 1555 void 1556 kpreempt(int asyncspl) 1557 { 1558 kthread_t *ct = curthread; 1559 1560 if (IGNORE_KERNEL_PREEMPTION) { 1561 aston(CPU->cpu_dispthread); 1562 return; 1563 } 1564 1565 /* 1566 * Check that conditions are right for kernel preemption 1567 */ 1568 do { 1569 if (ct->t_preempt) { 1570 /* 1571 * either a privileged thread (idle, panic, interrupt) 1572 * or will check when t_preempt is lowered 1573 * We need to specifically handle the case where 1574 * the thread is in the middle of swtch (resume has 1575 * been called) and has its t_preempt set 1576 * [idle thread and a thread which is in kpreempt 1577 * already] and then a high priority thread is 1578 * available in the local dispatch queue. 1579 * In this case the resumed thread needs to take a 1580 * trap so that it can call kpreempt. We achieve 1581 * this by using siron(). 1582 * How do we detect this condition: 1583 * idle thread is running and is in the midst of 1584 * resume: curthread->t_pri == -1 && CPU->dispthread 1585 * != CPU->thread 1586 * Need to ensure that this happens only at high pil 1587 * resume is called at high pil 1588 * Only in resume_from_idle is the pil changed. 1589 */ 1590 if (ct->t_pri < 0) { 1591 kpreempt_cnts.kpc_idle++; 1592 if (CPU->cpu_dispthread != CPU->cpu_thread) 1593 siron(); 1594 } else if (ct->t_flag & T_INTR_THREAD) { 1595 kpreempt_cnts.kpc_intr++; 1596 if (ct->t_pil == CLOCK_LEVEL) 1597 kpreempt_cnts.kpc_clock++; 1598 } else { 1599 kpreempt_cnts.kpc_blocked++; 1600 if (CPU->cpu_dispthread != CPU->cpu_thread) 1601 siron(); 1602 } 1603 aston(CPU->cpu_dispthread); 1604 return; 1605 } 1606 if (ct->t_state != TS_ONPROC || 1607 ct->t_disp_queue != CPU->cpu_disp) { 1608 /* this thread will be calling swtch() shortly */ 1609 kpreempt_cnts.kpc_notonproc++; 1610 if (CPU->cpu_thread != CPU->cpu_dispthread) { 1611 /* already in swtch(), force another */ 1612 kpreempt_cnts.kpc_inswtch++; 1613 siron(); 1614 } 1615 return; 1616 } 1617 if (getpil() >= DISP_LEVEL) { 1618 /* 1619 * We can't preempt this thread if it is at 1620 * a PIL >= DISP_LEVEL since it may be holding 1621 * a spin lock (like sched_lock). 1622 */ 1623 siron(); /* check back later */ 1624 kpreempt_cnts.kpc_prilevel++; 1625 return; 1626 } 1627 if (!interrupts_enabled()) { 1628 /* 1629 * Can't preempt while running with ints disabled 1630 */ 1631 kpreempt_cnts.kpc_prilevel++; 1632 return; 1633 } 1634 if (asyncspl != KPREEMPT_SYNC) 1635 kpreempt_cnts.kpc_apreempt++; 1636 else 1637 kpreempt_cnts.kpc_spreempt++; 1638 1639 ct->t_preempt++; 1640 preempt(); 1641 ct->t_preempt--; 1642 } while (CPU->cpu_kprunrun); 1643 } 1644 1645 /* 1646 * Print out debugging info. 1647 */ 1648 static void 1649 showregs(uint_t type, struct regs *rp, caddr_t addr) 1650 { 1651 int s; 1652 1653 s = spl7(); 1654 type &= ~USER; 1655 if (PTOU(curproc)->u_comm[0]) 1656 printf("%s: ", PTOU(curproc)->u_comm); 1657 if (type < TRAP_TYPES) 1658 printf("#%s %s\n", trap_type_mnemonic[type], trap_type[type]); 1659 else 1660 switch (type) { 1661 case T_SYSCALL: 1662 printf("Syscall Trap:\n"); 1663 break; 1664 case T_AST: 1665 printf("AST\n"); 1666 break; 1667 default: 1668 printf("Bad Trap = %d\n", type); 1669 break; 1670 } 1671 if (type == T_PGFLT) { 1672 printf("Bad %s fault at addr=0x%lx\n", 1673 USERMODE(rp->r_cs) ? "user": "kernel", (uintptr_t)addr); 1674 } else if (addr) { 1675 printf("addr=0x%lx\n", (uintptr_t)addr); 1676 } 1677 1678 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n", 1679 (ttoproc(curthread) && ttoproc(curthread)->p_pidp) ? 1680 ttoproc(curthread)->p_pid : 0, rp->r_pc, rp->r_sp, rp->r_ps); 1681 1682 #if defined(__lint) 1683 /* 1684 * this clause can be deleted when lint bug 4870403 is fixed 1685 * (lint thinks that bit 32 is illegal in a %b format string) 1686 */ 1687 printf("cr0: %x cr4: %b\n", 1688 (uint_t)getcr0(), (uint_t)getcr4(), FMT_CR4); 1689 #else 1690 printf("cr0: %b cr4: %b\n", 1691 (uint_t)getcr0(), FMT_CR0, (uint_t)getcr4(), FMT_CR4); 1692 #endif /* __lint */ 1693 1694 printf("cr2: %lx", getcr2()); 1695 #if !defined(__xpv) 1696 printf("cr3: %lx", getcr3()); 1697 #if defined(__amd64) 1698 printf("cr8: %lx\n", getcr8()); 1699 #endif 1700 #endif 1701 printf("\n"); 1702 1703 dumpregs(rp); 1704 splx(s); 1705 } 1706 1707 static void 1708 dumpregs(struct regs *rp) 1709 { 1710 #if defined(__amd64) 1711 const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n"; 1712 1713 printf(fmt, "rdi", rp->r_rdi, "rsi", rp->r_rsi, "rdx", rp->r_rdx); 1714 printf(fmt, "rcx", rp->r_rcx, " r8", rp->r_r8, " r9", rp->r_r9); 1715 printf(fmt, "rax", rp->r_rax, "rbx", rp->r_rbx, "rbp", rp->r_rbp); 1716 printf(fmt, "r10", rp->r_r10, "r11", rp->r_r11, "r12", rp->r_r12); 1717 printf(fmt, "r13", rp->r_r13, "r14", rp->r_r14, "r15", rp->r_r15); 1718 1719 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE), 1720 " ds", rp->r_ds); 1721 printf(fmt, " es", rp->r_es, " fs", rp->r_fs, " gs", rp->r_gs); 1722 1723 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, "rip", rp->r_rip); 1724 printf(fmt, " cs", rp->r_cs, "rfl", rp->r_rfl, "rsp", rp->r_rsp); 1725 1726 printf("\t%3s: %16lx\n", " ss", rp->r_ss); 1727 1728 #elif defined(__i386) 1729 const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n"; 1730 1731 printf(fmt, " gs", rp->r_gs, " fs", rp->r_fs, 1732 " es", rp->r_es, " ds", rp->r_ds); 1733 printf(fmt, "edi", rp->r_edi, "esi", rp->r_esi, 1734 "ebp", rp->r_ebp, "esp", rp->r_esp); 1735 printf(fmt, "ebx", rp->r_ebx, "edx", rp->r_edx, 1736 "ecx", rp->r_ecx, "eax", rp->r_eax); 1737 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, 1738 "eip", rp->r_eip, " cs", rp->r_cs); 1739 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n", 1740 "efl", rp->r_efl, "usp", rp->r_uesp, " ss", rp->r_ss); 1741 1742 #endif /* __i386 */ 1743 } 1744 1745 /* 1746 * Test to see if the instruction is iret on i386 or iretq on amd64. 1747 * 1748 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true 1749 * then we are in the context of hypervisor's failsafe handler because it 1750 * tried to iret and failed due to a bad selector. See xen_failsafe_callback. 1751 */ 1752 static int 1753 instr_is_iret(caddr_t pc) 1754 { 1755 1756 #if defined(__xpv) 1757 extern void nopop_sys_rtt_syscall(void); 1758 return ((pc == (caddr_t)nopop_sys_rtt_syscall) ? 1 : 0); 1759 1760 #else 1761 1762 #if defined(__amd64) 1763 static const uint8_t iret_insn[2] = { 0x48, 0xcf }; /* iretq */ 1764 1765 #elif defined(__i386) 1766 static const uint8_t iret_insn[1] = { 0xcf }; /* iret */ 1767 #endif /* __i386 */ 1768 return (bcmp(pc, iret_insn, sizeof (iret_insn)) == 0); 1769 1770 #endif /* __xpv */ 1771 } 1772 1773 #if defined(__i386) 1774 1775 /* 1776 * Test to see if the instruction is part of __SEGREGS_POP 1777 * 1778 * Note carefully the appallingly awful dependency between 1779 * the instruction sequence used in __SEGREGS_POP and these 1780 * instructions encoded here. 1781 */ 1782 static int 1783 instr_is_segregs_pop(caddr_t pc) 1784 { 1785 static const uint8_t movw_0_esp_gs[4] = { 0x8e, 0x6c, 0x24, 0x0 }; 1786 static const uint8_t movw_4_esp_fs[4] = { 0x8e, 0x64, 0x24, 0x4 }; 1787 static const uint8_t movw_8_esp_es[4] = { 0x8e, 0x44, 0x24, 0x8 }; 1788 static const uint8_t movw_c_esp_ds[4] = { 0x8e, 0x5c, 0x24, 0xc }; 1789 1790 if (bcmp(pc, movw_0_esp_gs, sizeof (movw_0_esp_gs)) == 0 || 1791 bcmp(pc, movw_4_esp_fs, sizeof (movw_4_esp_fs)) == 0 || 1792 bcmp(pc, movw_8_esp_es, sizeof (movw_8_esp_es)) == 0 || 1793 bcmp(pc, movw_c_esp_ds, sizeof (movw_c_esp_ds)) == 0) 1794 return (1); 1795 1796 return (0); 1797 } 1798 1799 #endif /* __i386 */ 1800 1801 /* 1802 * Test to see if the instruction is part of _sys_rtt. 1803 * 1804 * Again on the hypervisor if we try to IRET to user land with a bad code 1805 * or stack selector we will get vectored through xen_failsafe_callback. 1806 * In which case we assume we got here via _sys_rtt since we only allow 1807 * IRET to user land to take place in _sys_rtt. 1808 */ 1809 static int 1810 instr_is_sys_rtt(caddr_t pc) 1811 { 1812 extern void _sys_rtt(), _sys_rtt_end(); 1813 1814 if ((uintptr_t)pc < (uintptr_t)_sys_rtt || 1815 (uintptr_t)pc > (uintptr_t)_sys_rtt_end) 1816 return (0); 1817 1818 return (1); 1819 } 1820 1821 /* 1822 * Handle #gp faults in kernel mode. 1823 * 1824 * One legitimate way this can happen is if we attempt to update segment 1825 * registers to naughty values on the way out of the kernel. 1826 * 1827 * This can happen in a couple of ways: someone - either accidentally or 1828 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies 1829 * (signal(2)) a ucontext that contains silly segment register values. 1830 * Or someone - either accidentally or on purpose - modifies the prgregset_t 1831 * of a subject process via /proc to contain silly segment register values. 1832 * 1833 * (The unfortunate part is that we can end up discovering the bad segment 1834 * register value in the middle of an 'iret' after we've popped most of the 1835 * stack. So it becomes quite difficult to associate an accurate ucontext 1836 * with the lwp, because the act of taking the #gp trap overwrites most of 1837 * what we were going to send the lwp.) 1838 * 1839 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp 1840 * trying to return to user mode and we get a #gp fault, then we need 1841 * to die() -- which will happen if we return non-zero from this routine. 1842 */ 1843 static int 1844 kern_gpfault(struct regs *rp) 1845 { 1846 kthread_t *t = curthread; 1847 proc_t *p = ttoproc(t); 1848 klwp_t *lwp = ttolwp(t); 1849 struct regs tmpregs, *trp = NULL; 1850 caddr_t pc = (caddr_t)rp->r_pc; 1851 int v; 1852 uint32_t auditing = AU_AUDITING(); 1853 1854 /* 1855 * if we're not an lwp, or in the case of running native the 1856 * pc range is outside _sys_rtt, then we should immediately 1857 * be die()ing horribly. 1858 */ 1859 if (lwp == NULL || !instr_is_sys_rtt(pc)) 1860 return (1); 1861 1862 /* 1863 * So at least we're in the right part of the kernel. 1864 * 1865 * Disassemble the instruction at the faulting pc. 1866 * Once we know what it is, we carefully reconstruct the stack 1867 * based on the order in which the stack is deconstructed in 1868 * _sys_rtt. Ew. 1869 */ 1870 if (instr_is_iret(pc)) { 1871 /* 1872 * We took the #gp while trying to perform the IRET. 1873 * This means that either %cs or %ss are bad. 1874 * All we know for sure is that most of the general 1875 * registers have been restored, including the 1876 * segment registers, and all we have left on the 1877 * topmost part of the lwp's stack are the 1878 * registers that the iretq was unable to consume. 1879 * 1880 * All the rest of the state was crushed by the #gp 1881 * which pushed -its- registers atop our old save area 1882 * (because we had to decrement the stack pointer, sigh) so 1883 * all that we can try and do is to reconstruct the 1884 * crushed frame from the #gp trap frame itself. 1885 */ 1886 trp = &tmpregs; 1887 trp->r_ss = lwptoregs(lwp)->r_ss; 1888 trp->r_sp = lwptoregs(lwp)->r_sp; 1889 trp->r_ps = lwptoregs(lwp)->r_ps; 1890 trp->r_cs = lwptoregs(lwp)->r_cs; 1891 trp->r_pc = lwptoregs(lwp)->r_pc; 1892 bcopy(rp, trp, offsetof(struct regs, r_pc)); 1893 1894 /* 1895 * Validate simple math 1896 */ 1897 ASSERT(trp->r_pc == lwptoregs(lwp)->r_pc); 1898 ASSERT(trp->r_err == rp->r_err); 1899 1900 1901 1902 } 1903 1904 #if defined(__amd64) 1905 if (trp == NULL && lwp->lwp_pcb.pcb_rupdate != 0) { 1906 1907 /* 1908 * This is the common case -- we're trying to load 1909 * a bad segment register value in the only section 1910 * of kernel code that ever loads segment registers. 1911 * 1912 * We don't need to do anything at this point because 1913 * the pcb contains all the pending segment register 1914 * state, and the regs are still intact because we 1915 * didn't adjust the stack pointer yet. Given the fidelity 1916 * of all this, we could conceivably send a signal 1917 * to the lwp, rather than core-ing. 1918 */ 1919 trp = lwptoregs(lwp); 1920 ASSERT((caddr_t)trp == (caddr_t)rp->r_sp); 1921 } 1922 1923 #elif defined(__i386) 1924 1925 if (trp == NULL && instr_is_segregs_pop(pc)) 1926 trp = lwptoregs(lwp); 1927 1928 #endif /* __i386 */ 1929 1930 if (trp == NULL) 1931 return (1); 1932 1933 /* 1934 * If we get to here, we're reasonably confident that we've 1935 * correctly decoded what happened on the way out of the kernel. 1936 * Rewrite the lwp's registers so that we can create a core dump 1937 * the (at least vaguely) represents the mcontext we were 1938 * being asked to restore when things went so terribly wrong. 1939 */ 1940 1941 /* 1942 * Make sure that we have a meaningful %trapno and %err. 1943 */ 1944 trp->r_trapno = rp->r_trapno; 1945 trp->r_err = rp->r_err; 1946 1947 if ((caddr_t)trp != (caddr_t)lwptoregs(lwp)) 1948 bcopy(trp, lwptoregs(lwp), sizeof (*trp)); 1949 1950 1951 mutex_enter(&p->p_lock); 1952 lwp->lwp_cursig = SIGSEGV; 1953 mutex_exit(&p->p_lock); 1954 1955 /* 1956 * Terminate all LWPs but don't discard them. If another lwp beat 1957 * us to the punch by calling exit(), evaporate now. 1958 */ 1959 proc_is_exiting(p); 1960 if (exitlwps(1) != 0) { 1961 mutex_enter(&p->p_lock); 1962 lwp_exit(); 1963 } 1964 1965 if (auditing) /* audit core dump */ 1966 audit_core_start(SIGSEGV); 1967 v = core(SIGSEGV, B_FALSE); 1968 if (auditing) /* audit core dump */ 1969 audit_core_finish(v ? CLD_KILLED : CLD_DUMPED); 1970 exit(v ? CLD_KILLED : CLD_DUMPED, SIGSEGV); 1971 return (0); 1972 } 1973 1974 /* 1975 * dump_tss() - Display the TSS structure 1976 */ 1977 1978 #if !defined(__xpv) 1979 #if defined(__amd64) 1980 1981 static void 1982 dump_tss(void) 1983 { 1984 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */ 1985 struct tss *tss = CPU->cpu_tss; 1986 1987 printf(tss_fmt, "tss_rsp0", (void *)tss->tss_rsp0); 1988 printf(tss_fmt, "tss_rsp1", (void *)tss->tss_rsp1); 1989 printf(tss_fmt, "tss_rsp2", (void *)tss->tss_rsp2); 1990 1991 printf(tss_fmt, "tss_ist1", (void *)tss->tss_ist1); 1992 printf(tss_fmt, "tss_ist2", (void *)tss->tss_ist2); 1993 printf(tss_fmt, "tss_ist3", (void *)tss->tss_ist3); 1994 printf(tss_fmt, "tss_ist4", (void *)tss->tss_ist4); 1995 printf(tss_fmt, "tss_ist5", (void *)tss->tss_ist5); 1996 printf(tss_fmt, "tss_ist6", (void *)tss->tss_ist6); 1997 printf(tss_fmt, "tss_ist7", (void *)tss->tss_ist7); 1998 } 1999 2000 #elif defined(__i386) 2001 2002 static void 2003 dump_tss(void) 2004 { 2005 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */ 2006 struct tss *tss = CPU->cpu_tss; 2007 2008 printf(tss_fmt, "tss_link", (void *)(uintptr_t)tss->tss_link); 2009 printf(tss_fmt, "tss_esp0", (void *)(uintptr_t)tss->tss_esp0); 2010 printf(tss_fmt, "tss_ss0", (void *)(uintptr_t)tss->tss_ss0); 2011 printf(tss_fmt, "tss_esp1", (void *)(uintptr_t)tss->tss_esp1); 2012 printf(tss_fmt, "tss_ss1", (void *)(uintptr_t)tss->tss_ss1); 2013 printf(tss_fmt, "tss_esp2", (void *)(uintptr_t)tss->tss_esp2); 2014 printf(tss_fmt, "tss_ss2", (void *)(uintptr_t)tss->tss_ss2); 2015 printf(tss_fmt, "tss_cr3", (void *)(uintptr_t)tss->tss_cr3); 2016 printf(tss_fmt, "tss_eip", (void *)(uintptr_t)tss->tss_eip); 2017 printf(tss_fmt, "tss_eflags", (void *)(uintptr_t)tss->tss_eflags); 2018 printf(tss_fmt, "tss_eax", (void *)(uintptr_t)tss->tss_eax); 2019 printf(tss_fmt, "tss_ebx", (void *)(uintptr_t)tss->tss_ebx); 2020 printf(tss_fmt, "tss_ecx", (void *)(uintptr_t)tss->tss_ecx); 2021 printf(tss_fmt, "tss_edx", (void *)(uintptr_t)tss->tss_edx); 2022 printf(tss_fmt, "tss_esp", (void *)(uintptr_t)tss->tss_esp); 2023 } 2024 2025 #endif /* __amd64 */ 2026 #endif /* !__xpv */ 2027 2028 #if defined(TRAPTRACE) 2029 2030 int ttrace_nrec = 10; /* number of records to dump out */ 2031 int ttrace_dump_nregs = 0; /* dump out this many records with regs too */ 2032 2033 /* 2034 * Dump out the last ttrace_nrec traptrace records on each CPU 2035 */ 2036 static void 2037 dump_ttrace(void) 2038 { 2039 trap_trace_ctl_t *ttc; 2040 trap_trace_rec_t *rec; 2041 uintptr_t current; 2042 int i, j, k; 2043 int n = NCPU; 2044 #if defined(__amd64) 2045 const char banner[] = 2046 "\ncpu address timestamp " 2047 "type vc handler pc\n"; 2048 const char fmt1[] = "%3d %016lx %12llx "; 2049 #elif defined(__i386) 2050 const char banner[] = 2051 "\ncpu address timestamp type vc handler pc\n"; 2052 const char fmt1[] = "%3d %08lx %12llx "; 2053 #endif 2054 const char fmt2[] = "%4s %3x "; 2055 const char fmt3[] = "%8s "; 2056 2057 if (ttrace_nrec == 0) 2058 return; 2059 2060 printf(banner); 2061 2062 for (i = 0; i < n; i++) { 2063 ttc = &trap_trace_ctl[i]; 2064 if (ttc->ttc_first == NULL) 2065 continue; 2066 2067 current = ttc->ttc_next - sizeof (trap_trace_rec_t); 2068 for (j = 0; j < ttrace_nrec; j++) { 2069 struct sysent *sys; 2070 struct autovec *vec; 2071 extern struct av_head autovect[]; 2072 int type; 2073 ulong_t off; 2074 char *sym, *stype; 2075 2076 if (current < ttc->ttc_first) 2077 current = 2078 ttc->ttc_limit - sizeof (trap_trace_rec_t); 2079 2080 if (current == NULL) 2081 continue; 2082 2083 rec = (trap_trace_rec_t *)current; 2084 2085 if (rec->ttr_stamp == 0) 2086 break; 2087 2088 printf(fmt1, i, (uintptr_t)rec, rec->ttr_stamp); 2089 2090 switch (rec->ttr_marker) { 2091 case TT_SYSCALL: 2092 case TT_SYSENTER: 2093 case TT_SYSC: 2094 case TT_SYSC64: 2095 #if defined(__amd64) 2096 sys = &sysent32[rec->ttr_sysnum]; 2097 switch (rec->ttr_marker) { 2098 case TT_SYSC64: 2099 sys = &sysent[rec->ttr_sysnum]; 2100 /*FALLTHROUGH*/ 2101 #elif defined(__i386) 2102 sys = &sysent[rec->ttr_sysnum]; 2103 switch (rec->ttr_marker) { 2104 case TT_SYSC64: 2105 #endif 2106 case TT_SYSC: 2107 stype = "sysc"; /* syscall */ 2108 break; 2109 case TT_SYSCALL: 2110 stype = "lcal"; /* lcall */ 2111 break; 2112 case TT_SYSENTER: 2113 stype = "syse"; /* sysenter */ 2114 break; 2115 default: 2116 break; 2117 } 2118 printf(fmt2, "sysc", rec->ttr_sysnum); 2119 if (sys != NULL) { 2120 sym = kobj_getsymname( 2121 (uintptr_t)sys->sy_callc, 2122 &off); 2123 if (sym != NULL) 2124 printf(fmt3, sym); 2125 else 2126 printf("%p ", sys->sy_callc); 2127 } else { 2128 printf(fmt3, "unknown"); 2129 } 2130 break; 2131 2132 case TT_INTERRUPT: 2133 printf(fmt2, "intr", rec->ttr_vector); 2134 if (get_intr_handler != NULL) 2135 vec = (struct autovec *) 2136 (*get_intr_handler) 2137 (rec->ttr_cpuid, rec->ttr_vector); 2138 else 2139 vec = 2140 autovect[rec->ttr_vector].avh_link; 2141 2142 if (vec != NULL) { 2143 sym = kobj_getsymname( 2144 (uintptr_t)vec->av_vector, &off); 2145 if (sym != NULL) 2146 printf(fmt3, sym); 2147 else 2148 printf("%p ", vec->av_vector); 2149 } else { 2150 printf(fmt3, "unknown "); 2151 } 2152 break; 2153 2154 case TT_TRAP: 2155 case TT_EVENT: 2156 type = rec->ttr_regs.r_trapno; 2157 printf(fmt2, "trap", type); 2158 if (type < TRAP_TYPES) 2159 printf(" #%s ", 2160 trap_type_mnemonic[type]); 2161 else 2162 switch (type) { 2163 case T_AST: 2164 printf(fmt3, "ast"); 2165 break; 2166 default: 2167 printf(fmt3, ""); 2168 break; 2169 } 2170 break; 2171 2172 default: 2173 break; 2174 } 2175 2176 sym = kobj_getsymname(rec->ttr_regs.r_pc, &off); 2177 if (sym != NULL) 2178 printf("%s+%lx\n", sym, off); 2179 else 2180 printf("%lx\n", rec->ttr_regs.r_pc); 2181 2182 if (ttrace_dump_nregs-- > 0) { 2183 int s; 2184 2185 if (rec->ttr_marker == TT_INTERRUPT) 2186 printf( 2187 "\t\tipl %x spl %x pri %x\n", 2188 rec->ttr_ipl, 2189 rec->ttr_spl, 2190 rec->ttr_pri); 2191 2192 dumpregs(&rec->ttr_regs); 2193 2194 printf("\t%3s: %p\n\n", " ct", 2195 (void *)rec->ttr_curthread); 2196 2197 /* 2198 * print out the pc stack that we recorded 2199 * at trap time (if any) 2200 */ 2201 for (s = 0; s < rec->ttr_sdepth; s++) { 2202 uintptr_t fullpc; 2203 2204 if (s >= TTR_STACK_DEPTH) { 2205 printf("ttr_sdepth corrupt\n"); 2206 break; 2207 } 2208 2209 fullpc = (uintptr_t)rec->ttr_stack[s]; 2210 2211 sym = kobj_getsymname(fullpc, &off); 2212 if (sym != NULL) 2213 printf("-> %s+0x%lx()\n", 2214 sym, off); 2215 else 2216 printf("-> 0x%lx()\n", fullpc); 2217 } 2218 printf("\n"); 2219 } 2220 current -= sizeof (trap_trace_rec_t); 2221 } 2222 } 2223 } 2224 2225 #endif /* TRAPTRACE */ 2226 2227 void 2228 panic_showtrap(struct panic_trap_info *tip) 2229 { 2230 showregs(tip->trap_type, tip->trap_regs, tip->trap_addr); 2231 2232 #if defined(TRAPTRACE) 2233 dump_ttrace(); 2234 #endif 2235 2236 #if !defined(__xpv) 2237 if (tip->trap_type == T_DBLFLT) 2238 dump_tss(); 2239 #endif 2240 } 2241 2242 void 2243 panic_savetrap(panic_data_t *pdp, struct panic_trap_info *tip) 2244 { 2245 panic_saveregs(pdp, tip->trap_regs); 2246 } 2247