1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PCI configuration space access routines 29 */ 30 31 #include <sys/systm.h> 32 #include <sys/psw.h> 33 #include <sys/bootconf.h> 34 #include <sys/reboot.h> 35 #include <sys/pci_impl.h> 36 #include <sys/pci_cfgspace.h> 37 #include <sys/pci_cfgspace_impl.h> 38 #include <sys/pci_cfgacc.h> 39 #if defined(__xpv) 40 #include <sys/hypervisor.h> 41 #endif 42 43 #if defined(__xpv) 44 int pci_max_nbus = 0xFE; 45 #endif 46 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN; 47 int pci_bios_maxbus; 48 int pci_bios_mech; 49 int pci_bios_vers; 50 51 /* 52 * These two variables can be used to force a configuration mechanism or 53 * to force which function is used to probe for the presence of the PCI bus. 54 */ 55 int PCI_CFG_TYPE = 0; 56 int PCI_PROBE_TYPE = 0; 57 58 /* 59 * No valid mcfg_mem_base by default, and accessing pci config space 60 * in mem-mapped way is disabled. 61 */ 62 uint64_t mcfg_mem_base = 0; 63 uint8_t mcfg_bus_start = 0; 64 uint8_t mcfg_bus_end = 0xff; 65 66 /* 67 * These function pointers lead to the actual implementation routines 68 * for configuration space access. Normally they lead to either the 69 * pci_mech1_* or pci_mech2_* routines, but they can also lead to 70 * routines that work around chipset bugs. 71 * These functions are accessing pci config space via I/O way. 72 * Pci_cfgacc_get/put functions shoul be used as more common interfaces, 73 * which also provide accessing pci config space via mem-mapped way. 74 */ 75 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg); 76 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg); 77 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg); 78 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val); 79 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val); 80 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val); 81 82 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req); 83 84 /* 85 * Internal routines 86 */ 87 static int pci_check(void); 88 89 #if !defined(__xpv) 90 static int pci_check_bios(void); 91 static int pci_get_cfg_type(void); 92 #endif 93 94 /* all config-space access routines share this one... */ 95 kmutex_t pcicfg_mutex; 96 97 /* ..except Orion and Neptune, which have to have their own */ 98 kmutex_t pcicfg_chipset_mutex; 99 100 void 101 pci_cfgspace_init(void) 102 { 103 mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN, 104 (ddi_iblock_cookie_t)ipltospl(15)); 105 mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN, 106 (ddi_iblock_cookie_t)ipltospl(15)); 107 if (!pci_check()) { 108 mutex_destroy(&pcicfg_mutex); 109 mutex_destroy(&pcicfg_chipset_mutex); 110 } 111 } 112 113 /* 114 * This code determines if this system supports PCI/PCIE and which 115 * type of configuration access method is used 116 */ 117 static int 118 pci_check(void) 119 { 120 uint64_t ecfginfo[4]; 121 122 /* 123 * Only do this once. NB: If this is not a PCI system, and we 124 * get called twice, we can't detect it and will probably die 125 * horribly when we try to ask the BIOS whether PCI is present. 126 * This code is safe *ONLY* during system startup when the 127 * BIOS is still available. 128 */ 129 if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN) 130 return (TRUE); 131 132 #if defined(__xpv) 133 /* 134 * only support PCI config mechanism 1 in i86xpv. This should be fine 135 * since the other ones are workarounds for old broken H/W which won't 136 * be supported in i86xpv anyway. 137 */ 138 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 139 pci_bios_cfg_type = PCI_MECHANISM_1; 140 pci_getb_func = pci_mech1_getb; 141 pci_getw_func = pci_mech1_getw; 142 pci_getl_func = pci_mech1_getl; 143 pci_putb_func = pci_mech1_putb; 144 pci_putw_func = pci_mech1_putw; 145 pci_putl_func = pci_mech1_putl; 146 147 /* 148 * Since we can't get the BIOS info in i86xpv, we will do an 149 * exhaustive search of all PCI buses. We have to do this until 150 * we start using the PCI information in ACPI. 151 */ 152 pci_bios_maxbus = pci_max_nbus; 153 } 154 #else /* !__xpv */ 155 156 pci_bios_cfg_type = pci_check_bios(); 157 158 if (pci_bios_cfg_type == PCI_MECHANISM_NONE) 159 pci_bios_cfg_type = PCI_MECHANISM_1; /* default to mech 1 */ 160 161 switch (pci_get_cfg_type()) { 162 case PCI_MECHANISM_1: 163 if (pci_is_broken_orion()) { 164 pci_getb_func = pci_orion_getb; 165 pci_getw_func = pci_orion_getw; 166 pci_getl_func = pci_orion_getl; 167 pci_putb_func = pci_orion_putb; 168 pci_putw_func = pci_orion_putw; 169 pci_putl_func = pci_orion_putl; 170 } else { 171 pci_getb_func = pci_mech1_getb; 172 pci_getw_func = pci_mech1_getw; 173 pci_getl_func = pci_mech1_getl; 174 pci_putb_func = pci_mech1_putb; 175 pci_putw_func = pci_mech1_putw; 176 pci_putl_func = pci_mech1_putl; 177 } 178 break; 179 180 case PCI_MECHANISM_2: 181 if (pci_check_neptune()) { 182 /* 183 * The BIOS for some systems with the Intel 184 * Neptune chipset seem to default to #2 even 185 * though the chipset can do #1. Override 186 * the BIOS so that MP systems will work 187 * correctly. 188 */ 189 190 pci_getb_func = pci_neptune_getb; 191 pci_getw_func = pci_neptune_getw; 192 pci_getl_func = pci_neptune_getl; 193 pci_putb_func = pci_neptune_putb; 194 pci_putw_func = pci_neptune_putw; 195 pci_putl_func = pci_neptune_putl; 196 } else { 197 pci_getb_func = pci_mech2_getb; 198 pci_getw_func = pci_mech2_getw; 199 pci_getl_func = pci_mech2_getl; 200 pci_putb_func = pci_mech2_putb; 201 pci_putw_func = pci_mech2_putw; 202 pci_putl_func = pci_mech2_putl; 203 } 204 break; 205 206 default: 207 return (FALSE); 208 } 209 #endif /* __xpv */ 210 211 /* 212 * Try to get a valid mcfg_mem_base in early boot 213 * If failed, leave mem-mapped pci config space accessing disabled 214 * until pci boot code (pci_autoconfig) makes sure this is a PCIE 215 * platform. 216 */ 217 if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) { 218 mcfg_mem_base = ecfginfo[0]; 219 mcfg_bus_start = ecfginfo[2]; 220 mcfg_bus_end = ecfginfo[3]; 221 } 222 223 /* See pci_cfgacc.c */ 224 pci_cfgacc_acc_p = pci_cfgacc_acc; 225 226 return (TRUE); 227 } 228 229 #if !defined(__xpv) 230 231 static int 232 pci_check_bios(void) 233 { 234 struct bop_regs regs; 235 uint32_t carryflag; 236 uint16_t ax, dx; 237 238 bzero(®s, sizeof (regs)); 239 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT; 240 241 BOP_DOINT(bootops, 0x1a, ®s); 242 carryflag = regs.eflags & PS_C; 243 ax = regs.eax.word.ax; 244 dx = regs.edx.word.dx; 245 246 /* the carry flag must not be set */ 247 if (carryflag != 0) 248 return (PCI_MECHANISM_NONE); 249 250 if (dx != ('P' | 'C'<<8)) 251 return (PCI_MECHANISM_NONE); 252 253 /* ah (the high byte of ax) must be zero */ 254 if ((ax & 0xff00) != 0) 255 return (PCI_MECHANISM_NONE); 256 257 pci_bios_mech = (ax & 0x3); 258 pci_bios_vers = regs.ebx.word.bx; 259 pci_bios_maxbus = (regs.ecx.word.cx & 0xff); 260 261 switch (pci_bios_mech) { 262 default: /* ?!? */ 263 case 0: /* supports neither? */ 264 return (PCI_MECHANISM_NONE); 265 266 case 1: 267 case 3: /* supports both */ 268 return (PCI_MECHANISM_1); 269 270 case 2: 271 return (PCI_MECHANISM_2); 272 } 273 } 274 275 static int 276 pci_get_cfg_type(void) 277 { 278 /* Check to see if the config mechanism has been set in /etc/system */ 279 switch (PCI_CFG_TYPE) { 280 default: 281 case 0: 282 break; 283 case 1: 284 return (PCI_MECHANISM_1); 285 case 2: 286 return (PCI_MECHANISM_2); 287 case -1: 288 return (PCI_MECHANISM_NONE); 289 } 290 291 /* call one of the PCI detection algorithms */ 292 switch (PCI_PROBE_TYPE) { 293 default: 294 case 0: 295 /* From pci_check() and pci_check_bios() */ 296 return (pci_bios_cfg_type); 297 case -1: 298 return (PCI_MECHANISM_NONE); 299 } 300 } 301 302 #endif /* __xpv */ 303