1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2016 Joyent, Inc. 31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/thread.h> 36 #include <sys/cpuvar.h> 37 #include <sys/cpu.h> 38 #include <sys/t_lock.h> 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/disp.h> 42 #include <sys/class.h> 43 #include <sys/cmn_err.h> 44 #include <sys/debug.h> 45 #include <sys/note.h> 46 #include <sys/asm_linkage.h> 47 #include <sys/x_call.h> 48 #include <sys/systm.h> 49 #include <sys/var.h> 50 #include <sys/vtrace.h> 51 #include <vm/hat.h> 52 #include <vm/as.h> 53 #include <vm/seg_kmem.h> 54 #include <vm/seg_kp.h> 55 #include <sys/segments.h> 56 #include <sys/kmem.h> 57 #include <sys/stack.h> 58 #include <sys/smp_impldefs.h> 59 #include <sys/x86_archext.h> 60 #include <sys/machsystm.h> 61 #include <sys/traptrace.h> 62 #include <sys/clock.h> 63 #include <sys/cpc_impl.h> 64 #include <sys/pg.h> 65 #include <sys/cmt.h> 66 #include <sys/dtrace.h> 67 #include <sys/archsystm.h> 68 #include <sys/fp.h> 69 #include <sys/reboot.h> 70 #include <sys/kdi_machimpl.h> 71 #include <vm/hat_i86.h> 72 #include <vm/vm_dep.h> 73 #include <sys/memnode.h> 74 #include <sys/pci_cfgspace.h> 75 #include <sys/mach_mmu.h> 76 #include <sys/sysmacros.h> 77 #if defined(__xpv) 78 #include <sys/hypervisor.h> 79 #endif 80 #include <sys/cpu_module.h> 81 #include <sys/ontrap.h> 82 83 struct cpu cpus[1]; /* CPU data */ 84 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 85 struct cpu *cpu_free_list; /* list for released CPUs */ 86 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 87 88 #define cpu_next_free cpu_prev 89 90 /* 91 * Useful for disabling MP bring-up on a MP capable system. 92 */ 93 int use_mp = 1; 94 95 /* 96 * to be set by a PSM to indicate what cpus 97 * are sitting around on the system. 98 */ 99 cpuset_t mp_cpus; 100 101 /* 102 * This variable is used by the hat layer to decide whether or not 103 * critical sections are needed to prevent race conditions. For sun4m, 104 * this variable is set once enough MP initialization has been done in 105 * order to allow cross calls. 106 */ 107 int flushes_require_xcalls; 108 109 cpuset_t cpu_ready_set; /* initialized in startup() */ 110 111 static void mp_startup_boot(void); 112 static void mp_startup_hotplug(void); 113 114 static void cpu_sep_enable(void); 115 static void cpu_sep_disable(void); 116 static void cpu_asysc_enable(void); 117 static void cpu_asysc_disable(void); 118 119 /* 120 * Init CPU info - get CPU type info for processor_info system call. 121 */ 122 void 123 init_cpu_info(struct cpu *cp) 124 { 125 processor_info_t *pi = &cp->cpu_type_info; 126 127 /* 128 * Get clock-frequency property for the CPU. 129 */ 130 pi->pi_clock = cpu_freq; 131 132 /* 133 * Current frequency in Hz. 134 */ 135 cp->cpu_curr_clock = cpu_freq_hz; 136 137 /* 138 * Supported frequencies. 139 */ 140 if (cp->cpu_supp_freqs == NULL) { 141 cpu_set_supp_freqs(cp, NULL); 142 } 143 144 (void) strcpy(pi->pi_processor_type, "i386"); 145 if (fpu_exists) 146 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 147 148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 150 151 /* 152 * If called for the BSP, cp is equal to current CPU. 153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info 154 * of current CPU as default values for cpu_idstr and cpu_brandstr. 155 * They will be corrected in mp_startup_common() after cpuid_pass1() 156 * has been invoked on target CPU. 157 */ 158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 160 } 161 162 /* 163 * Configure syscall support on this CPU. 164 */ 165 /*ARGSUSED*/ 166 void 167 init_cpu_syscall(struct cpu *cp) 168 { 169 kpreempt_disable(); 170 171 #if defined(__amd64) 172 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 173 is_x86_feature(x86_featureset, X86FSET_ASYSC)) { 174 175 #if !defined(__lint) 176 /* 177 * The syscall instruction imposes a certain ordering on 178 * segment selectors, so we double-check that ordering 179 * here. 180 */ 181 ASSERT(KDS_SEL == KCS_SEL + 8); 182 ASSERT(UDS_SEL == U32CS_SEL + 8); 183 ASSERT(UCS_SEL == U32CS_SEL + 16); 184 #endif 185 /* 186 * Turn syscall/sysret extensions on. 187 */ 188 cpu_asysc_enable(); 189 190 /* 191 * Program the magic registers .. 192 */ 193 wrmsr(MSR_AMD_STAR, 194 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 195 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 196 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 197 198 /* 199 * This list of flags is masked off the incoming 200 * %rfl when we enter the kernel. 201 */ 202 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 203 } 204 #endif 205 206 /* 207 * On 32-bit kernels, we use sysenter/sysexit because it's too 208 * hard to use syscall/sysret, and it is more portable anyway. 209 * 210 * On 64-bit kernels on Nocona machines, the 32-bit syscall 211 * variant isn't available to 32-bit applications, but sysenter is. 212 */ 213 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 214 is_x86_feature(x86_featureset, X86FSET_SEP)) { 215 216 #if !defined(__lint) 217 /* 218 * The sysenter instruction imposes a certain ordering on 219 * segment selectors, so we double-check that ordering 220 * here. See "sysenter" in Intel document 245471-012, "IA-32 221 * Intel Architecture Software Developer's Manual Volume 2: 222 * Instruction Set Reference" 223 */ 224 ASSERT(KDS_SEL == KCS_SEL + 8); 225 226 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 227 ASSERT32(UDS_SEL == UCS_SEL + 8); 228 229 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 230 ASSERT64(UDS_SEL == U32CS_SEL + 8); 231 #endif 232 233 cpu_sep_enable(); 234 235 /* 236 * resume() sets this value to the base of the threads stack 237 * via a context handler. 238 */ 239 wrmsr(MSR_INTC_SEP_ESP, 0); 240 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 241 } 242 243 kpreempt_enable(); 244 } 245 246 #if !defined(__xpv) 247 /* 248 * Configure per-cpu ID GDT 249 */ 250 static void 251 init_cpu_id_gdt(struct cpu *cp) 252 { 253 /* Write cpu_id into limit field of GDT for usermode retrieval */ 254 #if defined(__amd64) 255 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id, 256 SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32); 257 #elif defined(__i386) 258 set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA, 259 SEL_UPL, SDP_BYTES, SDP_OP32); 260 #endif 261 } 262 #endif /* !defined(__xpv) */ 263 264 /* 265 * Multiprocessor initialization. 266 * 267 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 268 * startup and idle threads for the specified CPU. 269 * Parameter boot is true for boot time operations and is false for CPU 270 * DR operations. 271 */ 272 static struct cpu * 273 mp_cpu_configure_common(int cpun, boolean_t boot) 274 { 275 struct cpu *cp; 276 kthread_id_t tp; 277 caddr_t sp; 278 proc_t *procp; 279 #if !defined(__xpv) 280 extern int idle_cpu_prefer_mwait; 281 extern void cpu_idle_mwait(); 282 #endif 283 extern void idle(); 284 extern void cpu_idle(); 285 286 #ifdef TRAPTRACE 287 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 288 #endif 289 290 ASSERT(MUTEX_HELD(&cpu_lock)); 291 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 292 293 if (cpu_free_list == NULL) { 294 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 295 } else { 296 cp = cpu_free_list; 297 cpu_free_list = cp->cpu_next_free; 298 } 299 300 cp->cpu_m.mcpu_istamp = cpun << 16; 301 302 /* Create per CPU specific threads in the process p0. */ 303 procp = &p0; 304 305 /* 306 * Initialize the dispatcher first. 307 */ 308 disp_cpu_init(cp); 309 310 cpu_vm_data_init(cp); 311 312 /* 313 * Allocate and initialize the startup thread for this CPU. 314 * Interrupt and process switch stacks get allocated later 315 * when the CPU starts running. 316 */ 317 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 318 TS_STOPPED, maxclsyspri); 319 320 /* 321 * Set state to TS_ONPROC since this thread will start running 322 * as soon as the CPU comes online. 323 * 324 * All the other fields of the thread structure are setup by 325 * thread_create(). 326 */ 327 THREAD_ONPROC(tp, cp); 328 tp->t_preempt = 1; 329 tp->t_bound_cpu = cp; 330 tp->t_affinitycnt = 1; 331 tp->t_cpu = cp; 332 tp->t_disp_queue = cp->cpu_disp; 333 334 /* 335 * Setup thread to start in mp_startup_common. 336 */ 337 sp = tp->t_stk; 338 tp->t_sp = (uintptr_t)(sp - MINFRAME); 339 #if defined(__amd64) 340 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 341 #endif 342 /* 343 * Setup thread start entry point for boot or hotplug. 344 */ 345 if (boot) { 346 tp->t_pc = (uintptr_t)mp_startup_boot; 347 } else { 348 tp->t_pc = (uintptr_t)mp_startup_hotplug; 349 } 350 351 cp->cpu_id = cpun; 352 cp->cpu_self = cp; 353 cp->cpu_thread = tp; 354 cp->cpu_lwp = NULL; 355 cp->cpu_dispthread = tp; 356 cp->cpu_dispatch_pri = DISP_PRIO(tp); 357 358 /* 359 * cpu_base_spl must be set explicitly here to prevent any blocking 360 * operations in mp_startup_common from causing the spl of the cpu 361 * to drop to 0 (allowing device interrupts before we're ready) in 362 * resume(). 363 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 364 * As an extra bit of security on DEBUG kernels, this is enforced with 365 * an assertion in mp_startup_common() -- before cpu_base_spl is set 366 * to its proper value. 367 */ 368 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 369 370 /* 371 * Now, initialize per-CPU idle thread for this CPU. 372 */ 373 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 374 375 cp->cpu_idle_thread = tp; 376 377 tp->t_preempt = 1; 378 tp->t_bound_cpu = cp; 379 tp->t_affinitycnt = 1; 380 tp->t_cpu = cp; 381 tp->t_disp_queue = cp->cpu_disp; 382 383 /* 384 * Bootstrap the CPU's PG data 385 */ 386 pg_cpu_bootstrap(cp); 387 388 /* 389 * Perform CPC initialization on the new CPU. 390 */ 391 kcpc_hw_init(cp); 392 393 /* 394 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 395 * for each CPU. 396 */ 397 setup_vaddr_for_ppcopy(cp); 398 399 /* 400 * Allocate page for new GDT and initialize from current GDT. 401 */ 402 #if !defined(__lint) 403 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 404 #endif 405 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 406 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 407 408 #if defined(__i386) 409 /* 410 * setup kernel %gs. 411 */ 412 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 413 SEL_KPL, 0, 1); 414 #endif 415 416 /* 417 * If we have more than one node, each cpu gets a copy of IDT 418 * local to its node. If this is a Pentium box, we use cpu 0's 419 * IDT. cpu 0's IDT has been made read-only to workaround the 420 * cmpxchgl register bug 421 */ 422 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 423 #if !defined(__lint) 424 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 425 #endif 426 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 427 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 428 } else { 429 cp->cpu_idt = CPU->cpu_idt; 430 } 431 432 /* 433 * alloc space for cpuid info 434 */ 435 cpuid_alloc_space(cp); 436 #if !defined(__xpv) 437 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) && 438 idle_cpu_prefer_mwait) { 439 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp); 440 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 441 } else 442 #endif 443 cp->cpu_m.mcpu_idle_cpu = cpu_idle; 444 445 init_cpu_info(cp); 446 447 #if !defined(__xpv) 448 init_cpu_id_gdt(cp); 449 #endif 450 451 /* 452 * alloc space for ucode_info 453 */ 454 ucode_alloc_space(cp); 455 xc_init_cpu(cp); 456 hat_cpu_online(cp); 457 458 #ifdef TRAPTRACE 459 /* 460 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 461 */ 462 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 463 ttc->ttc_next = ttc->ttc_first; 464 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 465 #endif 466 467 /* 468 * Record that we have another CPU. 469 */ 470 /* 471 * Initialize the interrupt threads for this CPU 472 */ 473 cpu_intr_alloc(cp, NINTR_THREADS); 474 475 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 476 cpu_set_state(cp); 477 478 /* 479 * Add CPU to list of available CPUs. It'll be on the active list 480 * after mp_startup_common(). 481 */ 482 cpu_add_unit(cp); 483 484 return (cp); 485 } 486 487 /* 488 * Undo what was done in mp_cpu_configure_common 489 */ 490 static void 491 mp_cpu_unconfigure_common(struct cpu *cp, int error) 492 { 493 ASSERT(MUTEX_HELD(&cpu_lock)); 494 495 /* 496 * Remove the CPU from the list of available CPUs. 497 */ 498 cpu_del_unit(cp->cpu_id); 499 500 if (error == ETIMEDOUT) { 501 /* 502 * The cpu was started, but never *seemed* to run any 503 * code in the kernel; it's probably off spinning in its 504 * own private world, though with potential references to 505 * our kmem-allocated IDTs and GDTs (for example). 506 * 507 * Worse still, it may actually wake up some time later, 508 * so rather than guess what it might or might not do, we 509 * leave the fundamental data structures intact. 510 */ 511 cp->cpu_flags = 0; 512 return; 513 } 514 515 /* 516 * At this point, the only threads bound to this CPU should 517 * special per-cpu threads: it's idle thread, it's pause threads, 518 * and it's interrupt threads. Clean these up. 519 */ 520 cpu_destroy_bound_threads(cp); 521 cp->cpu_idle_thread = NULL; 522 523 /* 524 * Free the interrupt stack. 525 */ 526 segkp_release(segkp, 527 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 528 cp->cpu_intr_stack = NULL; 529 530 #ifdef TRAPTRACE 531 /* 532 * Discard the trap trace buffer 533 */ 534 { 535 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 536 537 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 538 ttc->ttc_first = NULL; 539 } 540 #endif 541 542 hat_cpu_offline(cp); 543 544 ucode_free_space(cp); 545 546 /* Free CPU ID string and brand string. */ 547 if (cp->cpu_idstr) { 548 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN); 549 cp->cpu_idstr = NULL; 550 } 551 if (cp->cpu_brandstr) { 552 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN); 553 cp->cpu_brandstr = NULL; 554 } 555 556 #if !defined(__xpv) 557 if (cp->cpu_m.mcpu_mwait != NULL) { 558 cpuid_mwait_free(cp); 559 cp->cpu_m.mcpu_mwait = NULL; 560 } 561 #endif 562 cpuid_free_space(cp); 563 564 if (cp->cpu_idt != CPU->cpu_idt) 565 kmem_free(cp->cpu_idt, PAGESIZE); 566 cp->cpu_idt = NULL; 567 568 kmem_free(cp->cpu_gdt, PAGESIZE); 569 cp->cpu_gdt = NULL; 570 571 if (cp->cpu_supp_freqs != NULL) { 572 size_t len = strlen(cp->cpu_supp_freqs) + 1; 573 kmem_free(cp->cpu_supp_freqs, len); 574 cp->cpu_supp_freqs = NULL; 575 } 576 577 teardown_vaddr_for_ppcopy(cp); 578 579 kcpc_hw_fini(cp); 580 581 cp->cpu_dispthread = NULL; 582 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 583 584 cpu_vm_data_destroy(cp); 585 586 xc_fini_cpu(cp); 587 disp_cpu_fini(cp); 588 589 ASSERT(cp != CPU0); 590 bzero(cp, sizeof (*cp)); 591 cp->cpu_next_free = cpu_free_list; 592 cpu_free_list = cp; 593 } 594 595 /* 596 * Apply workarounds for known errata, and warn about those that are absent. 597 * 598 * System vendors occasionally create configurations which contain different 599 * revisions of the CPUs that are almost but not exactly the same. At the 600 * time of writing, this meant that their clock rates were the same, their 601 * feature sets were the same, but the required workaround were -not- 602 * necessarily the same. So, this routine is invoked on -every- CPU soon 603 * after starting to make sure that the resulting system contains the most 604 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 605 * system. 606 * 607 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 608 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata 609 * prior to acknowledging their readiness to the master, so this routine will 610 * never be executed by multiple CPUs in parallel, thus making updates to 611 * global data safe. 612 * 613 * These workarounds are based on Rev 3.57 of the Revision Guide for 614 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 615 */ 616 617 #if defined(OPTERON_ERRATUM_88) 618 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 619 #endif 620 621 #if defined(OPTERON_ERRATUM_91) 622 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 623 #endif 624 625 #if defined(OPTERON_ERRATUM_93) 626 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 627 #endif 628 629 #if defined(OPTERON_ERRATUM_95) 630 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 631 #endif 632 633 #if defined(OPTERON_ERRATUM_100) 634 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 635 #endif 636 637 #if defined(OPTERON_ERRATUM_108) 638 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 639 #endif 640 641 #if defined(OPTERON_ERRATUM_109) 642 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 643 #endif 644 645 #if defined(OPTERON_ERRATUM_121) 646 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 647 #endif 648 649 #if defined(OPTERON_ERRATUM_122) 650 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 651 #endif 652 653 #if defined(OPTERON_ERRATUM_123) 654 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 655 #endif 656 657 #if defined(OPTERON_ERRATUM_131) 658 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 659 #endif 660 661 #if defined(OPTERON_WORKAROUND_6336786) 662 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 663 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 664 #endif 665 666 #if defined(OPTERON_WORKAROUND_6323525) 667 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 668 #endif 669 670 #if defined(OPTERON_ERRATUM_298) 671 int opteron_erratum_298; 672 #endif 673 674 #if defined(OPTERON_ERRATUM_721) 675 int opteron_erratum_721; 676 #endif 677 678 static void 679 workaround_warning(cpu_t *cp, uint_t erratum) 680 { 681 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 682 cp->cpu_id, erratum); 683 } 684 685 static void 686 workaround_applied(uint_t erratum) 687 { 688 if (erratum > 1000000) 689 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 690 erratum); 691 else 692 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 693 erratum); 694 } 695 696 static void 697 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 698 { 699 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 700 cp->cpu_id, rw, msr, error); 701 } 702 703 /* 704 * Determine the number of nodes in a Hammer / Greyhound / Griffin family 705 * system. 706 */ 707 static uint_t 708 opteron_get_nnodes(void) 709 { 710 static uint_t nnodes = 0; 711 712 if (nnodes == 0) { 713 #ifdef DEBUG 714 uint_t family; 715 716 /* 717 * This routine uses a PCI config space based mechanism 718 * for retrieving the number of nodes in the system. 719 * Device 24, function 0, offset 0x60 as used here is not 720 * AMD processor architectural, and may not work on processor 721 * families other than those listed below. 722 * 723 * Callers of this routine must ensure that we're running on 724 * a processor which supports this mechanism. 725 * The assertion below is meant to catch calls on unsupported 726 * processors. 727 */ 728 family = cpuid_getfamily(CPU); 729 ASSERT(family == 0xf || family == 0x10 || family == 0x11); 730 #endif /* DEBUG */ 731 732 /* 733 * Obtain the number of nodes in the system from 734 * bits [6:4] of the Node ID register on node 0. 735 * 736 * The actual node count is NodeID[6:4] + 1 737 * 738 * The Node ID register is accessed via function 0, 739 * offset 0x60. Node 0 is device 24. 740 */ 741 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 742 } 743 return (nnodes); 744 } 745 746 uint_t 747 do_erratum_298(struct cpu *cpu) 748 { 749 static int osvwrc = -3; 750 extern int osvw_opteron_erratum(cpu_t *, uint_t); 751 752 /* 753 * L2 Eviction May Occur During Processor Operation To Set 754 * Accessed or Dirty Bit. 755 */ 756 if (osvwrc == -3) { 757 osvwrc = osvw_opteron_erratum(cpu, 298); 758 } else { 759 /* osvw return codes should be consistent for all cpus */ 760 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 761 } 762 763 switch (osvwrc) { 764 case 0: /* erratum is not present: do nothing */ 765 break; 766 case 1: /* erratum is present: BIOS workaround applied */ 767 /* 768 * check if workaround is actually in place and issue warning 769 * if not. 770 */ 771 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 772 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 773 #if defined(OPTERON_ERRATUM_298) 774 opteron_erratum_298++; 775 #else 776 workaround_warning(cpu, 298); 777 return (1); 778 #endif 779 } 780 break; 781 case -1: /* cannot determine via osvw: check cpuid */ 782 if ((cpuid_opteron_erratum(cpu, 298) > 0) && 783 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 784 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 785 #if defined(OPTERON_ERRATUM_298) 786 opteron_erratum_298++; 787 #else 788 workaround_warning(cpu, 298); 789 return (1); 790 #endif 791 } 792 break; 793 } 794 return (0); 795 } 796 797 uint_t 798 workaround_errata(struct cpu *cpu) 799 { 800 uint_t missing = 0; 801 802 ASSERT(cpu == CPU); 803 804 /*LINTED*/ 805 if (cpuid_opteron_erratum(cpu, 88) > 0) { 806 /* 807 * SWAPGS May Fail To Read Correct GS Base 808 */ 809 #if defined(OPTERON_ERRATUM_88) 810 /* 811 * The workaround is an mfence in the relevant assembler code 812 */ 813 opteron_erratum_88++; 814 #else 815 workaround_warning(cpu, 88); 816 missing++; 817 #endif 818 } 819 820 if (cpuid_opteron_erratum(cpu, 91) > 0) { 821 /* 822 * Software Prefetches May Report A Page Fault 823 */ 824 #if defined(OPTERON_ERRATUM_91) 825 /* 826 * fix is in trap.c 827 */ 828 opteron_erratum_91++; 829 #else 830 workaround_warning(cpu, 91); 831 missing++; 832 #endif 833 } 834 835 if (cpuid_opteron_erratum(cpu, 93) > 0) { 836 /* 837 * RSM Auto-Halt Restart Returns to Incorrect RIP 838 */ 839 #if defined(OPTERON_ERRATUM_93) 840 /* 841 * fix is in trap.c 842 */ 843 opteron_erratum_93++; 844 #else 845 workaround_warning(cpu, 93); 846 missing++; 847 #endif 848 } 849 850 /*LINTED*/ 851 if (cpuid_opteron_erratum(cpu, 95) > 0) { 852 /* 853 * RET Instruction May Return to Incorrect EIP 854 */ 855 #if defined(OPTERON_ERRATUM_95) 856 #if defined(_LP64) 857 /* 858 * Workaround this by ensuring that 32-bit user code and 859 * 64-bit kernel code never occupy the same address 860 * range mod 4G. 861 */ 862 if (_userlimit32 > 0xc0000000ul) 863 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 864 865 /*LINTED*/ 866 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 867 opteron_erratum_95++; 868 #endif /* _LP64 */ 869 #else 870 workaround_warning(cpu, 95); 871 missing++; 872 #endif 873 } 874 875 if (cpuid_opteron_erratum(cpu, 100) > 0) { 876 /* 877 * Compatibility Mode Branches Transfer to Illegal Address 878 */ 879 #if defined(OPTERON_ERRATUM_100) 880 /* 881 * fix is in trap.c 882 */ 883 opteron_erratum_100++; 884 #else 885 workaround_warning(cpu, 100); 886 missing++; 887 #endif 888 } 889 890 /*LINTED*/ 891 if (cpuid_opteron_erratum(cpu, 108) > 0) { 892 /* 893 * CPUID Instruction May Return Incorrect Model Number In 894 * Some Processors 895 */ 896 #if defined(OPTERON_ERRATUM_108) 897 /* 898 * (Our cpuid-handling code corrects the model number on 899 * those processors) 900 */ 901 #else 902 workaround_warning(cpu, 108); 903 missing++; 904 #endif 905 } 906 907 /*LINTED*/ 908 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 909 /* 910 * Certain Reverse REP MOVS May Produce Unpredictable Behavior 911 */ 912 #if defined(OPTERON_ERRATUM_109) 913 /* 914 * The "workaround" is to print a warning to upgrade the BIOS 915 */ 916 uint64_t value; 917 const uint_t msr = MSR_AMD_PATCHLEVEL; 918 int err; 919 920 if ((err = checked_rdmsr(msr, &value)) != 0) { 921 msr_warning(cpu, "rd", msr, err); 922 workaround_warning(cpu, 109); 923 missing++; 924 } 925 if (value == 0) 926 opteron_erratum_109++; 927 #else 928 workaround_warning(cpu, 109); 929 missing++; 930 #endif 931 /*CONSTANTCONDITION*/ 932 } while (0); 933 934 /*LINTED*/ 935 if (cpuid_opteron_erratum(cpu, 121) > 0) { 936 /* 937 * Sequential Execution Across Non_Canonical Boundary Caused 938 * Processor Hang 939 */ 940 #if defined(OPTERON_ERRATUM_121) 941 #if defined(_LP64) 942 /* 943 * Erratum 121 is only present in long (64 bit) mode. 944 * Workaround is to include the page immediately before the 945 * va hole to eliminate the possibility of system hangs due to 946 * sequential execution across the va hole boundary. 947 */ 948 if (opteron_erratum_121) 949 opteron_erratum_121++; 950 else { 951 if (hole_start) { 952 hole_start -= PAGESIZE; 953 } else { 954 /* 955 * hole_start not yet initialized by 956 * mmu_init. Initialize hole_start 957 * with value to be subtracted. 958 */ 959 hole_start = PAGESIZE; 960 } 961 opteron_erratum_121++; 962 } 963 #endif /* _LP64 */ 964 #else 965 workaround_warning(cpu, 121); 966 missing++; 967 #endif 968 } 969 970 /*LINTED*/ 971 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 972 /* 973 * TLB Flush Filter May Cause Coherency Problem in 974 * Multiprocessor Systems 975 */ 976 #if defined(OPTERON_ERRATUM_122) 977 uint64_t value; 978 const uint_t msr = MSR_AMD_HWCR; 979 int error; 980 981 /* 982 * Erratum 122 is only present in MP configurations (multi-core 983 * or multi-processor). 984 */ 985 #if defined(__xpv) 986 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 987 break; 988 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 989 break; 990 #else 991 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 992 cpuid_get_ncpu_per_chip(cpu) == 1) 993 break; 994 #endif 995 /* disable TLB Flush Filter */ 996 997 if ((error = checked_rdmsr(msr, &value)) != 0) { 998 msr_warning(cpu, "rd", msr, error); 999 workaround_warning(cpu, 122); 1000 missing++; 1001 } else { 1002 value |= (uint64_t)AMD_HWCR_FFDIS; 1003 if ((error = checked_wrmsr(msr, value)) != 0) { 1004 msr_warning(cpu, "wr", msr, error); 1005 workaround_warning(cpu, 122); 1006 missing++; 1007 } 1008 } 1009 opteron_erratum_122++; 1010 #else 1011 workaround_warning(cpu, 122); 1012 missing++; 1013 #endif 1014 /*CONSTANTCONDITION*/ 1015 } while (0); 1016 1017 /*LINTED*/ 1018 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 1019 /* 1020 * Bypassed Reads May Cause Data Corruption of System Hang in 1021 * Dual Core Processors 1022 */ 1023 #if defined(OPTERON_ERRATUM_123) 1024 uint64_t value; 1025 const uint_t msr = MSR_AMD_PATCHLEVEL; 1026 int err; 1027 1028 /* 1029 * Erratum 123 applies only to multi-core cpus. 1030 */ 1031 if (cpuid_get_ncpu_per_chip(cpu) < 2) 1032 break; 1033 #if defined(__xpv) 1034 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1035 break; 1036 #endif 1037 /* 1038 * The "workaround" is to print a warning to upgrade the BIOS 1039 */ 1040 if ((err = checked_rdmsr(msr, &value)) != 0) { 1041 msr_warning(cpu, "rd", msr, err); 1042 workaround_warning(cpu, 123); 1043 missing++; 1044 } 1045 if (value == 0) 1046 opteron_erratum_123++; 1047 #else 1048 workaround_warning(cpu, 123); 1049 missing++; 1050 1051 #endif 1052 /*CONSTANTCONDITION*/ 1053 } while (0); 1054 1055 /*LINTED*/ 1056 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 1057 /* 1058 * Multiprocessor Systems with Four or More Cores May Deadlock 1059 * Waiting for a Probe Response 1060 */ 1061 #if defined(OPTERON_ERRATUM_131) 1062 uint64_t nbcfg; 1063 const uint_t msr = MSR_AMD_NB_CFG; 1064 const uint64_t wabits = 1065 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1066 int error; 1067 1068 /* 1069 * Erratum 131 applies to any system with four or more cores. 1070 */ 1071 if (opteron_erratum_131) 1072 break; 1073 #if defined(__xpv) 1074 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1075 break; 1076 if (xpv_nr_phys_cpus() < 4) 1077 break; 1078 #else 1079 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1080 break; 1081 #endif 1082 /* 1083 * Print a warning if neither of the workarounds for 1084 * erratum 131 is present. 1085 */ 1086 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1087 msr_warning(cpu, "rd", msr, error); 1088 workaround_warning(cpu, 131); 1089 missing++; 1090 } else if ((nbcfg & wabits) == 0) { 1091 opteron_erratum_131++; 1092 } else { 1093 /* cannot have both workarounds set */ 1094 ASSERT((nbcfg & wabits) != wabits); 1095 } 1096 #else 1097 workaround_warning(cpu, 131); 1098 missing++; 1099 #endif 1100 /*CONSTANTCONDITION*/ 1101 } while (0); 1102 1103 /* 1104 * This isn't really an erratum, but for convenience the 1105 * detection/workaround code lives here and in cpuid_opteron_erratum. 1106 */ 1107 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1108 #if defined(OPTERON_WORKAROUND_6336786) 1109 /* 1110 * Disable C1-Clock ramping on multi-core/multi-processor 1111 * K8 platforms to guard against TSC drift. 1112 */ 1113 if (opteron_workaround_6336786) { 1114 opteron_workaround_6336786++; 1115 #if defined(__xpv) 1116 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1117 xpv_nr_phys_cpus() > 1) || 1118 opteron_workaround_6336786_UP) { 1119 /* 1120 * XXPV Hmm. We can't walk the Northbridges on 1121 * the hypervisor; so just complain and drive 1122 * on. This probably needs to be fixed in 1123 * the hypervisor itself. 1124 */ 1125 opteron_workaround_6336786++; 1126 workaround_warning(cpu, 6336786); 1127 #else /* __xpv */ 1128 } else if ((opteron_get_nnodes() * 1129 cpuid_get_ncpu_per_chip(cpu) > 1) || 1130 opteron_workaround_6336786_UP) { 1131 1132 uint_t node, nnodes; 1133 uint8_t data; 1134 1135 nnodes = opteron_get_nnodes(); 1136 for (node = 0; node < nnodes; node++) { 1137 /* 1138 * Clear PMM7[1:0] (function 3, offset 0x87) 1139 * Northbridge device is the node id + 24. 1140 */ 1141 data = pci_getb_func(0, node + 24, 3, 0x87); 1142 data &= 0xFC; 1143 pci_putb_func(0, node + 24, 3, 0x87, data); 1144 } 1145 opteron_workaround_6336786++; 1146 #endif /* __xpv */ 1147 } 1148 #else 1149 workaround_warning(cpu, 6336786); 1150 missing++; 1151 #endif 1152 } 1153 1154 /*LINTED*/ 1155 /* 1156 * Mutex primitives don't work as expected. 1157 */ 1158 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1159 #if defined(OPTERON_WORKAROUND_6323525) 1160 /* 1161 * This problem only occurs with 2 or more cores. If bit in 1162 * MSR_AMD_BU_CFG set, then not applicable. The workaround 1163 * is to patch the semaphone routines with the lfence 1164 * instruction to provide necessary load memory barrier with 1165 * possible subsequent read-modify-write ops. 1166 * 1167 * It is too early in boot to call the patch routine so 1168 * set erratum variable to be done in startup_end(). 1169 */ 1170 if (opteron_workaround_6323525) { 1171 opteron_workaround_6323525++; 1172 #if defined(__xpv) 1173 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) { 1174 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1175 /* 1176 * XXPV Use dom0_msr here when extended 1177 * operations are supported? 1178 */ 1179 if (xpv_nr_phys_cpus() > 1) 1180 opteron_workaround_6323525++; 1181 } else { 1182 /* 1183 * We have no way to tell how many physical 1184 * cpus there are, or even if this processor 1185 * has the problem, so enable the workaround 1186 * unconditionally (at some performance cost). 1187 */ 1188 opteron_workaround_6323525++; 1189 } 1190 #else /* __xpv */ 1191 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) && 1192 ((opteron_get_nnodes() * 1193 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1194 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1195 opteron_workaround_6323525++; 1196 #endif /* __xpv */ 1197 } 1198 #else 1199 workaround_warning(cpu, 6323525); 1200 missing++; 1201 #endif 1202 } 1203 1204 missing += do_erratum_298(cpu); 1205 1206 if (cpuid_opteron_erratum(cpu, 721) > 0) { 1207 #if defined(OPTERON_ERRATUM_721) 1208 on_trap_data_t otd; 1209 1210 if (!on_trap(&otd, OT_DATA_ACCESS)) 1211 wrmsr(MSR_AMD_DE_CFG, 1212 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721); 1213 no_trap(); 1214 1215 opteron_erratum_721++; 1216 #else 1217 workaround_warning(cpu, 721); 1218 missing++; 1219 #endif 1220 } 1221 1222 #ifdef __xpv 1223 return (0); 1224 #else 1225 return (missing); 1226 #endif 1227 } 1228 1229 void 1230 workaround_errata_end() 1231 { 1232 #if defined(OPTERON_ERRATUM_88) 1233 if (opteron_erratum_88) 1234 workaround_applied(88); 1235 #endif 1236 #if defined(OPTERON_ERRATUM_91) 1237 if (opteron_erratum_91) 1238 workaround_applied(91); 1239 #endif 1240 #if defined(OPTERON_ERRATUM_93) 1241 if (opteron_erratum_93) 1242 workaround_applied(93); 1243 #endif 1244 #if defined(OPTERON_ERRATUM_95) 1245 if (opteron_erratum_95) 1246 workaround_applied(95); 1247 #endif 1248 #if defined(OPTERON_ERRATUM_100) 1249 if (opteron_erratum_100) 1250 workaround_applied(100); 1251 #endif 1252 #if defined(OPTERON_ERRATUM_108) 1253 if (opteron_erratum_108) 1254 workaround_applied(108); 1255 #endif 1256 #if defined(OPTERON_ERRATUM_109) 1257 if (opteron_erratum_109) { 1258 cmn_err(CE_WARN, 1259 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1260 " processor\nerratum 109 was not detected; updating your" 1261 " system's BIOS to a version\ncontaining this" 1262 " microcode patch is HIGHLY recommended or erroneous" 1263 " system\noperation may occur.\n"); 1264 } 1265 #endif 1266 #if defined(OPTERON_ERRATUM_121) 1267 if (opteron_erratum_121) 1268 workaround_applied(121); 1269 #endif 1270 #if defined(OPTERON_ERRATUM_122) 1271 if (opteron_erratum_122) 1272 workaround_applied(122); 1273 #endif 1274 #if defined(OPTERON_ERRATUM_123) 1275 if (opteron_erratum_123) { 1276 cmn_err(CE_WARN, 1277 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1278 " processor\nerratum 123 was not detected; updating your" 1279 " system's BIOS to a version\ncontaining this" 1280 " microcode patch is HIGHLY recommended or erroneous" 1281 " system\noperation may occur.\n"); 1282 } 1283 #endif 1284 #if defined(OPTERON_ERRATUM_131) 1285 if (opteron_erratum_131) { 1286 cmn_err(CE_WARN, 1287 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1288 " processor\nerratum 131 was not detected; updating your" 1289 " system's BIOS to a version\ncontaining this" 1290 " microcode patch is HIGHLY recommended or erroneous" 1291 " system\noperation may occur.\n"); 1292 } 1293 #endif 1294 #if defined(OPTERON_WORKAROUND_6336786) 1295 if (opteron_workaround_6336786) 1296 workaround_applied(6336786); 1297 #endif 1298 #if defined(OPTERON_WORKAROUND_6323525) 1299 if (opteron_workaround_6323525) 1300 workaround_applied(6323525); 1301 #endif 1302 #if defined(OPTERON_ERRATUM_298) 1303 if (opteron_erratum_298) { 1304 cmn_err(CE_WARN, 1305 "BIOS microcode patch for AMD 64/Opteron(tm)" 1306 " processor\nerratum 298 was not detected; updating your" 1307 " system's BIOS to a version\ncontaining this" 1308 " microcode patch is HIGHLY recommended or erroneous" 1309 " system\noperation may occur.\n"); 1310 } 1311 #endif 1312 #if defined(OPTERON_ERRATUM_721) 1313 if (opteron_erratum_721) 1314 workaround_applied(721); 1315 #endif 1316 } 1317 1318 /* 1319 * The procset_slave and procset_master are used to synchronize 1320 * between the control CPU and the target CPU when starting CPUs. 1321 */ 1322 static cpuset_t procset_slave, procset_master; 1323 1324 static void 1325 mp_startup_wait(cpuset_t *sp, processorid_t cpuid) 1326 { 1327 cpuset_t tempset; 1328 1329 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid); 1330 tempset = *(volatile cpuset_t *)sp) { 1331 SMT_PAUSE(); 1332 } 1333 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid); 1334 } 1335 1336 static void 1337 mp_startup_signal(cpuset_t *sp, processorid_t cpuid) 1338 { 1339 cpuset_t tempset; 1340 1341 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid); 1342 for (tempset = *sp; CPU_IN_SET(tempset, cpuid); 1343 tempset = *(volatile cpuset_t *)sp) { 1344 SMT_PAUSE(); 1345 } 1346 } 1347 1348 int 1349 mp_start_cpu_common(cpu_t *cp, boolean_t boot) 1350 { 1351 _NOTE(ARGUNUSED(boot)); 1352 1353 void *ctx; 1354 int delays; 1355 int error = 0; 1356 cpuset_t tempset; 1357 processorid_t cpuid; 1358 #ifndef __xpv 1359 extern void cpupm_init(cpu_t *); 1360 #endif 1361 1362 ASSERT(cp != NULL); 1363 cpuid = cp->cpu_id; 1364 ctx = mach_cpucontext_alloc(cp); 1365 if (ctx == NULL) { 1366 cmn_err(CE_WARN, 1367 "cpu%d: failed to allocate context", cp->cpu_id); 1368 return (EAGAIN); 1369 } 1370 error = mach_cpu_start(cp, ctx); 1371 if (error != 0) { 1372 cmn_err(CE_WARN, 1373 "cpu%d: failed to start, error %d", cp->cpu_id, error); 1374 mach_cpucontext_free(cp, ctx, error); 1375 return (error); 1376 } 1377 1378 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid); 1379 delays++) { 1380 if (delays == 500) { 1381 /* 1382 * After five seconds, things are probably looking 1383 * a bit bleak - explain the hang. 1384 */ 1385 cmn_err(CE_NOTE, "cpu%d: started, " 1386 "but not running in the kernel yet", cpuid); 1387 } else if (delays > 2000) { 1388 /* 1389 * We waited at least 20 seconds, bail .. 1390 */ 1391 error = ETIMEDOUT; 1392 cmn_err(CE_WARN, "cpu%d: timed out", cpuid); 1393 mach_cpucontext_free(cp, ctx, error); 1394 return (error); 1395 } 1396 1397 /* 1398 * wait at least 10ms, then check again.. 1399 */ 1400 delay(USEC_TO_TICK_ROUNDUP(10000)); 1401 tempset = *((volatile cpuset_t *)&procset_slave); 1402 } 1403 CPUSET_ATOMIC_DEL(procset_slave, cpuid); 1404 1405 mach_cpucontext_free(cp, ctx, 0); 1406 1407 #ifndef __xpv 1408 if (tsc_gethrtime_enable) 1409 tsc_sync_master(cpuid); 1410 #endif 1411 1412 if (dtrace_cpu_init != NULL) { 1413 (*dtrace_cpu_init)(cpuid); 1414 } 1415 1416 /* 1417 * During CPU DR operations, the cpu_lock is held by current 1418 * (the control) thread. We can't release the cpu_lock here 1419 * because that will break the CPU DR logic. 1420 * On the other hand, CPUPM and processor group initialization 1421 * routines need to access the cpu_lock. So we invoke those 1422 * routines here on behalf of mp_startup_common(). 1423 * 1424 * CPUPM and processor group initialization routines depend 1425 * on the cpuid probing results. Wait for mp_startup_common() 1426 * to signal that cpuid probing is done. 1427 */ 1428 mp_startup_wait(&procset_slave, cpuid); 1429 #ifndef __xpv 1430 cpupm_init(cp); 1431 #endif 1432 (void) pg_cpu_init(cp, B_FALSE); 1433 cpu_set_state(cp); 1434 mp_startup_signal(&procset_master, cpuid); 1435 1436 return (0); 1437 } 1438 1439 /* 1440 * Start a single cpu, assuming that the kernel context is available 1441 * to successfully start another cpu. 1442 * 1443 * (For example, real mode code is mapped into the right place 1444 * in memory and is ready to be run.) 1445 */ 1446 int 1447 start_cpu(processorid_t who) 1448 { 1449 cpu_t *cp; 1450 int error = 0; 1451 cpuset_t tempset; 1452 1453 ASSERT(who != 0); 1454 1455 /* 1456 * Check if there's at least a Mbyte of kmem available 1457 * before attempting to start the cpu. 1458 */ 1459 if (kmem_avail() < 1024 * 1024) { 1460 /* 1461 * Kick off a reap in case that helps us with 1462 * later attempts .. 1463 */ 1464 kmem_reap(); 1465 return (ENOMEM); 1466 } 1467 1468 /* 1469 * First configure cpu. 1470 */ 1471 cp = mp_cpu_configure_common(who, B_TRUE); 1472 ASSERT(cp != NULL); 1473 1474 /* 1475 * Then start cpu. 1476 */ 1477 error = mp_start_cpu_common(cp, B_TRUE); 1478 if (error != 0) { 1479 mp_cpu_unconfigure_common(cp, error); 1480 return (error); 1481 } 1482 1483 mutex_exit(&cpu_lock); 1484 tempset = cpu_ready_set; 1485 while (!CPU_IN_SET(tempset, who)) { 1486 drv_usecwait(1); 1487 tempset = *((volatile cpuset_t *)&cpu_ready_set); 1488 } 1489 mutex_enter(&cpu_lock); 1490 1491 return (0); 1492 } 1493 1494 void 1495 start_other_cpus(int cprboot) 1496 { 1497 _NOTE(ARGUNUSED(cprboot)); 1498 1499 uint_t who; 1500 uint_t bootcpuid = 0; 1501 1502 /* 1503 * Initialize our own cpu_info. 1504 */ 1505 init_cpu_info(CPU); 1506 1507 #if !defined(__xpv) 1508 init_cpu_id_gdt(CPU); 1509 #endif 1510 1511 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 1512 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 1513 1514 /* 1515 * Initialize our syscall handlers 1516 */ 1517 init_cpu_syscall(CPU); 1518 1519 /* 1520 * Take the boot cpu out of the mp_cpus set because we know 1521 * it's already running. Add it to the cpu_ready_set for 1522 * precisely the same reason. 1523 */ 1524 CPUSET_DEL(mp_cpus, bootcpuid); 1525 CPUSET_ADD(cpu_ready_set, bootcpuid); 1526 1527 /* 1528 * skip the rest of this if 1529 * . only 1 cpu dectected and system isn't hotplug-capable 1530 * . not using MP 1531 */ 1532 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) || 1533 use_mp == 0) { 1534 if (use_mp == 0) 1535 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1536 goto done; 1537 } 1538 1539 /* 1540 * perform such initialization as is needed 1541 * to be able to take CPUs on- and off-line. 1542 */ 1543 cpu_pause_init(); 1544 1545 xc_init_cpu(CPU); /* initialize processor crosscalls */ 1546 1547 if (mach_cpucontext_init() != 0) 1548 goto done; 1549 1550 flushes_require_xcalls = 1; 1551 1552 /* 1553 * We lock our affinity to the master CPU to ensure that all slave CPUs 1554 * do their TSC syncs with the same CPU. 1555 */ 1556 affinity_set(CPU_CURRENT); 1557 1558 for (who = 0; who < NCPU; who++) { 1559 if (!CPU_IN_SET(mp_cpus, who)) 1560 continue; 1561 ASSERT(who != bootcpuid); 1562 1563 mutex_enter(&cpu_lock); 1564 if (start_cpu(who) != 0) 1565 CPUSET_DEL(mp_cpus, who); 1566 cpu_state_change_notify(who, CPU_SETUP); 1567 mutex_exit(&cpu_lock); 1568 } 1569 1570 /* Free the space allocated to hold the microcode file */ 1571 ucode_cleanup(); 1572 1573 affinity_clear(); 1574 1575 mach_cpucontext_fini(); 1576 1577 done: 1578 if (get_hwenv() == HW_NATIVE) 1579 workaround_errata_end(); 1580 cmi_post_mpstartup(); 1581 1582 if (use_mp && ncpus != boot_max_ncpus) { 1583 cmn_err(CE_NOTE, 1584 "System detected %d cpus, but " 1585 "only %d cpu(s) were enabled during boot.", 1586 boot_max_ncpus, ncpus); 1587 cmn_err(CE_NOTE, 1588 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1589 "See eeprom(1M)."); 1590 } 1591 } 1592 1593 int 1594 mp_cpu_configure(int cpuid) 1595 { 1596 cpu_t *cp; 1597 1598 if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1599 return (ENOTSUP); 1600 } 1601 1602 cp = cpu_get(cpuid); 1603 if (cp != NULL) { 1604 return (EALREADY); 1605 } 1606 1607 /* 1608 * Check if there's at least a Mbyte of kmem available 1609 * before attempting to start the cpu. 1610 */ 1611 if (kmem_avail() < 1024 * 1024) { 1612 /* 1613 * Kick off a reap in case that helps us with 1614 * later attempts .. 1615 */ 1616 kmem_reap(); 1617 return (ENOMEM); 1618 } 1619 1620 cp = mp_cpu_configure_common(cpuid, B_FALSE); 1621 ASSERT(cp != NULL && cpu_get(cpuid) == cp); 1622 1623 return (cp != NULL ? 0 : EAGAIN); 1624 } 1625 1626 int 1627 mp_cpu_unconfigure(int cpuid) 1628 { 1629 cpu_t *cp; 1630 1631 if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1632 return (ENOTSUP); 1633 } else if (cpuid < 0 || cpuid >= max_ncpus) { 1634 return (EINVAL); 1635 } 1636 1637 cp = cpu_get(cpuid); 1638 if (cp == NULL) { 1639 return (ENODEV); 1640 } 1641 mp_cpu_unconfigure_common(cp, 0); 1642 1643 return (0); 1644 } 1645 1646 /* 1647 * Startup function for 'other' CPUs (besides boot cpu). 1648 * Called from real_mode_start. 1649 * 1650 * WARNING: until CPU_READY is set, mp_startup_common and routines called by 1651 * mp_startup_common should not call routines (e.g. kmem_free) that could call 1652 * hat_unload which requires CPU_READY to be set. 1653 */ 1654 static void 1655 mp_startup_common(boolean_t boot) 1656 { 1657 cpu_t *cp = CPU; 1658 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; 1659 extern void cpu_event_init_cpu(cpu_t *); 1660 1661 /* 1662 * We need to get TSC on this proc synced (i.e., any delta 1663 * from cpu0 accounted for) as soon as we can, because many 1664 * many things use gethrtime/pc_gethrestime, including 1665 * interrupts, cmn_err, etc. Before we can do that, we want to 1666 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that 1667 * right away. 1668 */ 1669 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES)); 1670 cpuid_pass1(cp, new_x86_featureset); 1671 1672 if (boot && get_hwenv() == HW_NATIVE && 1673 cpuid_getvendor(CPU) == X86_VENDOR_Intel && 1674 cpuid_getfamily(CPU) == 6 && 1675 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 1676 is_x86_feature(new_x86_featureset, X86FSET_TSC)) { 1677 (void) wrmsr(REG_TSC, 0UL); 1678 } 1679 1680 /* Let the control CPU continue into tsc_sync_master() */ 1681 mp_startup_signal(&procset_slave, cp->cpu_id); 1682 1683 #ifndef __xpv 1684 if (tsc_gethrtime_enable) 1685 tsc_sync_slave(); 1686 #endif 1687 1688 /* 1689 * Once this was done from assembly, but it's safer here; if 1690 * it blocks, we need to be able to swtch() to and from, and 1691 * since we get here by calling t_pc, we need to do that call 1692 * before swtch() overwrites it. 1693 */ 1694 (void) (*ap_mlsetup)(); 1695 1696 #ifndef __xpv 1697 /* 1698 * Program this cpu's PAT 1699 */ 1700 pat_sync(); 1701 #endif 1702 1703 /* 1704 * Set up TSC_AUX to contain the cpuid for this processor 1705 * for the rdtscp instruction. 1706 */ 1707 if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 1708 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1709 1710 /* 1711 * Initialize this CPU's syscall handlers 1712 */ 1713 init_cpu_syscall(cp); 1714 1715 /* 1716 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1717 * highest level at which a routine is permitted to block on 1718 * an adaptive mutex (allows for cpu poke interrupt in case 1719 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1720 * device interrupts that may end up in the hat layer issuing cross 1721 * calls before CPU_READY is set. 1722 */ 1723 splx(ipltospl(LOCK_LEVEL)); 1724 sti(); 1725 1726 /* 1727 * Do a sanity check to make sure this new CPU is a sane thing 1728 * to add to the collection of processors running this system. 1729 * 1730 * XXX Clearly this needs to get more sophisticated, if x86 1731 * systems start to get built out of heterogenous CPUs; as is 1732 * likely to happen once the number of processors in a configuration 1733 * gets large enough. 1734 */ 1735 if (compare_x86_featureset(x86_featureset, new_x86_featureset) == 1736 B_FALSE) { 1737 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id); 1738 print_x86_featureset(new_x86_featureset); 1739 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1740 } 1741 1742 /* 1743 * We do not support cpus with mixed monitor/mwait support if the 1744 * boot cpu supports monitor/mwait. 1745 */ 1746 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) != 1747 is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) 1748 panic("unsupported mixed cpu monitor/mwait support detected"); 1749 1750 /* 1751 * We could be more sophisticated here, and just mark the CPU 1752 * as "faulted" but at this point we'll opt for the easier 1753 * answer of dying horribly. Provided the boot cpu is ok, 1754 * the system can be recovered by booting with use_mp set to zero. 1755 */ 1756 if (workaround_errata(cp) != 0) 1757 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1758 1759 /* 1760 * We can touch cpu_flags here without acquiring the cpu_lock here 1761 * because the cpu_lock is held by the control CPU which is running 1762 * mp_start_cpu_common(). 1763 * Need to clear CPU_QUIESCED flag before calling any function which 1764 * may cause thread context switching, such as kmem_alloc() etc. 1765 * The idle thread checks for CPU_QUIESCED flag and loops for ever if 1766 * it's set. So the startup thread may have no chance to switch back 1767 * again if it's switched away with CPU_QUIESCED set. 1768 */ 1769 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED); 1770 1771 /* 1772 * Setup this processor for XSAVE. 1773 */ 1774 if (fp_save_mech == FP_XSAVE) { 1775 xsave_setup_msr(cp); 1776 } 1777 1778 cpuid_pass2(cp); 1779 cpuid_pass3(cp); 1780 cpuid_pass4(cp, NULL); 1781 1782 /* 1783 * Correct cpu_idstr and cpu_brandstr on target CPU after 1784 * cpuid_pass1() is done. 1785 */ 1786 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN); 1787 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN); 1788 1789 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 1790 1791 post_startup_cpu_fixups(); 1792 1793 cpu_event_init_cpu(cp); 1794 1795 /* 1796 * Enable preemption here so that contention for any locks acquired 1797 * later in mp_startup_common may be preempted if the thread owning 1798 * those locks is continuously executing on other CPUs (for example, 1799 * this CPU must be preemptible to allow other CPUs to pause it during 1800 * their startup phases). It's safe to enable preemption here because 1801 * the CPU state is pretty-much fully constructed. 1802 */ 1803 curthread->t_preempt = 0; 1804 1805 /* The base spl should still be at LOCK LEVEL here */ 1806 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1807 set_base_spl(); /* Restore the spl to its proper value */ 1808 1809 pghw_physid_create(cp); 1810 /* 1811 * Delegate initialization tasks, which need to access the cpu_lock, 1812 * to mp_start_cpu_common() because we can't acquire the cpu_lock here 1813 * during CPU DR operations. 1814 */ 1815 mp_startup_signal(&procset_slave, cp->cpu_id); 1816 mp_startup_wait(&procset_master, cp->cpu_id); 1817 pg_cmt_cpu_startup(cp); 1818 1819 if (boot) { 1820 mutex_enter(&cpu_lock); 1821 cp->cpu_flags &= ~CPU_OFFLINE; 1822 cpu_enable_intr(cp); 1823 cpu_add_active(cp); 1824 mutex_exit(&cpu_lock); 1825 } 1826 1827 /* Enable interrupts */ 1828 (void) spl0(); 1829 1830 /* 1831 * Fill out cpu_ucode_info. Update microcode if necessary. 1832 */ 1833 ucode_check(cp); 1834 1835 #ifndef __xpv 1836 { 1837 /* 1838 * Set up the CPU module for this CPU. This can't be done 1839 * before this CPU is made CPU_READY, because we may (in 1840 * heterogeneous systems) need to go load another CPU module. 1841 * The act of attempting to load a module may trigger a 1842 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1843 */ 1844 cmi_hdl_t hdl; 1845 1846 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1847 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1848 if (is_x86_feature(x86_featureset, X86FSET_MCA)) 1849 cmi_mca_init(hdl); 1850 cp->cpu_m.mcpu_cmi_hdl = hdl; 1851 } 1852 } 1853 #endif /* __xpv */ 1854 1855 if (boothowto & RB_DEBUG) 1856 kdi_cpu_init(); 1857 1858 (void) mach_cpu_create_device_node(cp, NULL); 1859 1860 /* 1861 * Setting the bit in cpu_ready_set must be the last operation in 1862 * processor initialization; the boot CPU will continue to boot once 1863 * it sees this bit set for all active CPUs. 1864 */ 1865 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1866 1867 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1868 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1869 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n", 1870 cp->cpu_id); 1871 1872 /* 1873 * Now we are done with the startup thread, so free it up. 1874 */ 1875 thread_exit(); 1876 panic("mp_startup: cannot return"); 1877 /*NOTREACHED*/ 1878 } 1879 1880 /* 1881 * Startup function for 'other' CPUs at boot time (besides boot cpu). 1882 */ 1883 static void 1884 mp_startup_boot(void) 1885 { 1886 mp_startup_common(B_TRUE); 1887 } 1888 1889 /* 1890 * Startup function for hotplug CPUs at runtime. 1891 */ 1892 void 1893 mp_startup_hotplug(void) 1894 { 1895 mp_startup_common(B_FALSE); 1896 } 1897 1898 /* 1899 * Start CPU on user request. 1900 */ 1901 /* ARGSUSED */ 1902 int 1903 mp_cpu_start(struct cpu *cp) 1904 { 1905 ASSERT(MUTEX_HELD(&cpu_lock)); 1906 return (0); 1907 } 1908 1909 /* 1910 * Stop CPU on user request. 1911 */ 1912 int 1913 mp_cpu_stop(struct cpu *cp) 1914 { 1915 extern int cbe_psm_timer_mode; 1916 ASSERT(MUTEX_HELD(&cpu_lock)); 1917 1918 #ifdef __xpv 1919 /* 1920 * We can't offline vcpu0. 1921 */ 1922 if (cp->cpu_id == 0) 1923 return (EBUSY); 1924 #endif 1925 1926 /* 1927 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1928 * can't stop it. (This is true only for machines with no TSC.) 1929 */ 1930 1931 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1932 return (EBUSY); 1933 1934 return (0); 1935 } 1936 1937 /* 1938 * Take the specified CPU out of participation in interrupts. 1939 */ 1940 int 1941 cpu_disable_intr(struct cpu *cp) 1942 { 1943 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1944 return (EBUSY); 1945 1946 cp->cpu_flags &= ~CPU_ENABLE; 1947 return (0); 1948 } 1949 1950 /* 1951 * Allow the specified CPU to participate in interrupts. 1952 */ 1953 void 1954 cpu_enable_intr(struct cpu *cp) 1955 { 1956 ASSERT(MUTEX_HELD(&cpu_lock)); 1957 cp->cpu_flags |= CPU_ENABLE; 1958 psm_enable_intr(cp->cpu_id); 1959 } 1960 1961 void 1962 mp_cpu_faulted_enter(struct cpu *cp) 1963 { 1964 #ifdef __xpv 1965 _NOTE(ARGUNUSED(cp)); 1966 #else 1967 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 1968 1969 if (hdl != NULL) { 1970 cmi_hdl_hold(hdl); 1971 } else { 1972 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1973 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1974 } 1975 if (hdl != NULL) { 1976 cmi_faulted_enter(hdl); 1977 cmi_hdl_rele(hdl); 1978 } 1979 #endif 1980 } 1981 1982 void 1983 mp_cpu_faulted_exit(struct cpu *cp) 1984 { 1985 #ifdef __xpv 1986 _NOTE(ARGUNUSED(cp)); 1987 #else 1988 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 1989 1990 if (hdl != NULL) { 1991 cmi_hdl_hold(hdl); 1992 } else { 1993 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1994 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1995 } 1996 if (hdl != NULL) { 1997 cmi_faulted_exit(hdl); 1998 cmi_hdl_rele(hdl); 1999 } 2000 #endif 2001 } 2002 2003 /* 2004 * The following two routines are used as context operators on threads belonging 2005 * to processes with a private LDT (see sysi86). Due to the rarity of such 2006 * processes, these routines are currently written for best code readability and 2007 * organization rather than speed. We could avoid checking x86_featureset at 2008 * every context switch by installing different context ops, depending on 2009 * x86_featureset, at LDT creation time -- one for each combination of fast 2010 * syscall features. 2011 */ 2012 2013 /*ARGSUSED*/ 2014 void 2015 cpu_fast_syscall_disable(void *arg) 2016 { 2017 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 2018 is_x86_feature(x86_featureset, X86FSET_SEP)) 2019 cpu_sep_disable(); 2020 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 2021 is_x86_feature(x86_featureset, X86FSET_ASYSC)) 2022 cpu_asysc_disable(); 2023 } 2024 2025 /*ARGSUSED*/ 2026 void 2027 cpu_fast_syscall_enable(void *arg) 2028 { 2029 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 2030 is_x86_feature(x86_featureset, X86FSET_SEP)) 2031 cpu_sep_enable(); 2032 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 2033 is_x86_feature(x86_featureset, X86FSET_ASYSC)) 2034 cpu_asysc_enable(); 2035 } 2036 2037 static void 2038 cpu_sep_enable(void) 2039 { 2040 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 2041 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2042 2043 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 2044 } 2045 2046 static void 2047 cpu_sep_disable(void) 2048 { 2049 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 2050 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2051 2052 /* 2053 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 2054 * the sysenter or sysexit instruction to trigger a #gp fault. 2055 */ 2056 wrmsr(MSR_INTC_SEP_CS, 0); 2057 } 2058 2059 static void 2060 cpu_asysc_enable(void) 2061 { 2062 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 2063 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2064 2065 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 2066 (uint64_t)(uintptr_t)AMD_EFER_SCE); 2067 } 2068 2069 static void 2070 cpu_asysc_disable(void) 2071 { 2072 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 2073 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2074 2075 /* 2076 * Turn off the SCE (syscall enable) bit in the EFER register. Software 2077 * executing syscall or sysret with this bit off will incur a #ud trap. 2078 */ 2079 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 2080 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 2081 } 2082