1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/thread.h> 31 #include <sys/cpuvar.h> 32 #include <sys/t_lock.h> 33 #include <sys/param.h> 34 #include <sys/proc.h> 35 #include <sys/disp.h> 36 #include <sys/class.h> 37 #include <sys/cmn_err.h> 38 #include <sys/debug.h> 39 #include <sys/asm_linkage.h> 40 #include <sys/x_call.h> 41 #include <sys/systm.h> 42 #include <sys/var.h> 43 #include <sys/vtrace.h> 44 #include <vm/hat.h> 45 #include <vm/as.h> 46 #include <vm/seg_kmem.h> 47 #include <vm/seg_kp.h> 48 #include <sys/segments.h> 49 #include <sys/kmem.h> 50 #include <sys/stack.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/x86_archext.h> 53 #include <sys/machsystm.h> 54 #include <sys/traptrace.h> 55 #include <sys/clock.h> 56 #include <sys/cpc_impl.h> 57 #include <sys/pg.h> 58 #include <sys/cmt.h> 59 #include <sys/dtrace.h> 60 #include <sys/archsystm.h> 61 #include <sys/fp.h> 62 #include <sys/reboot.h> 63 #include <sys/kdi_machimpl.h> 64 #include <vm/hat_i86.h> 65 #include <sys/memnode.h> 66 #include <sys/pci_cfgspace.h> 67 #include <sys/mach_mmu.h> 68 #include <sys/sysmacros.h> 69 #include <sys/cpu_module.h> 70 71 struct cpu cpus[1]; /* CPU data */ 72 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 73 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 74 75 /* 76 * Useful for disabling MP bring-up on a MP capable system. 77 */ 78 int use_mp = 1; 79 80 /* 81 * to be set by a PSM to indicate what cpus 82 * are sitting around on the system. 83 */ 84 cpuset_t mp_cpus; 85 86 /* 87 * This variable is used by the hat layer to decide whether or not 88 * critical sections are needed to prevent race conditions. For sun4m, 89 * this variable is set once enough MP initialization has been done in 90 * order to allow cross calls. 91 */ 92 int flushes_require_xcalls; 93 cpuset_t cpu_ready_set = 1; 94 95 static void mp_startup(void); 96 97 static void cpu_sep_enable(void); 98 static void cpu_sep_disable(void); 99 static void cpu_asysc_enable(void); 100 static void cpu_asysc_disable(void); 101 102 extern int tsc_gethrtime_enable; 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 (void) strcpy(pi->pi_processor_type, "i386"); 119 if (fpu_exists) 120 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 121 122 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 123 124 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 125 (void) strcpy(cp->cpu_idstr, buf); 126 127 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 128 129 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 130 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 131 (void) strcpy(cp->cpu_brandstr, buf); 132 133 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 134 } 135 136 /* 137 * Configure syscall support on this CPU. 138 */ 139 /*ARGSUSED*/ 140 static void 141 init_cpu_syscall(struct cpu *cp) 142 { 143 kpreempt_disable(); 144 145 #if defined(__amd64) 146 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 147 148 #if !defined(__lint) 149 /* 150 * The syscall instruction imposes a certain ordering on 151 * segment selectors, so we double-check that ordering 152 * here. 153 */ 154 ASSERT(KDS_SEL == KCS_SEL + 8); 155 ASSERT(UDS_SEL == U32CS_SEL + 8); 156 ASSERT(UCS_SEL == U32CS_SEL + 16); 157 #endif 158 /* 159 * Turn syscall/sysret extensions on. 160 */ 161 cpu_asysc_enable(); 162 163 /* 164 * Program the magic registers .. 165 */ 166 wrmsr(MSR_AMD_STAR, 167 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 168 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 169 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 170 171 /* 172 * This list of flags is masked off the incoming 173 * %rfl when we enter the kernel. 174 */ 175 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 176 } 177 #endif 178 179 /* 180 * On 32-bit kernels, we use sysenter/sysexit because it's too 181 * hard to use syscall/sysret, and it is more portable anyway. 182 * 183 * On 64-bit kernels on Nocona machines, the 32-bit syscall 184 * variant isn't available to 32-bit applications, but sysenter is. 185 */ 186 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 187 188 #if !defined(__lint) 189 /* 190 * The sysenter instruction imposes a certain ordering on 191 * segment selectors, so we double-check that ordering 192 * here. See "sysenter" in Intel document 245471-012, "IA-32 193 * Intel Architecture Software Developer's Manual Volume 2: 194 * Instruction Set Reference" 195 */ 196 ASSERT(KDS_SEL == KCS_SEL + 8); 197 198 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 199 ASSERT32(UDS_SEL == UCS_SEL + 8); 200 201 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 202 ASSERT64(UDS_SEL == U32CS_SEL + 8); 203 #endif 204 205 cpu_sep_enable(); 206 207 /* 208 * resume() sets this value to the base of the threads stack 209 * via a context handler. 210 */ 211 wrmsr(MSR_INTC_SEP_ESP, 0); 212 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 213 } 214 215 kpreempt_enable(); 216 } 217 218 /* 219 * Multiprocessor initialization. 220 * 221 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 222 * startup and idle threads for the specified CPU. 223 */ 224 struct cpu * 225 mp_startup_init(int cpun) 226 { 227 struct cpu *cp; 228 kthread_id_t tp; 229 caddr_t sp; 230 proc_t *procp; 231 extern void idle(); 232 233 #ifdef TRAPTRACE 234 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 235 #endif 236 237 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 238 239 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 240 procp = curthread->t_procp; 241 242 mutex_enter(&cpu_lock); 243 /* 244 * Initialize the dispatcher first. 245 */ 246 disp_cpu_init(cp); 247 mutex_exit(&cpu_lock); 248 249 cpu_vm_data_init(cp); 250 251 /* 252 * Allocate and initialize the startup thread for this CPU. 253 * Interrupt and process switch stacks get allocated later 254 * when the CPU starts running. 255 */ 256 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 257 TS_STOPPED, maxclsyspri); 258 259 /* 260 * Set state to TS_ONPROC since this thread will start running 261 * as soon as the CPU comes online. 262 * 263 * All the other fields of the thread structure are setup by 264 * thread_create(). 265 */ 266 THREAD_ONPROC(tp, cp); 267 tp->t_preempt = 1; 268 tp->t_bound_cpu = cp; 269 tp->t_affinitycnt = 1; 270 tp->t_cpu = cp; 271 tp->t_disp_queue = cp->cpu_disp; 272 273 /* 274 * Setup thread to start in mp_startup. 275 */ 276 sp = tp->t_stk; 277 tp->t_pc = (uintptr_t)mp_startup; 278 tp->t_sp = (uintptr_t)(sp - MINFRAME); 279 #if defined(__amd64) 280 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 281 #endif 282 283 cp->cpu_id = cpun; 284 cp->cpu_self = cp; 285 cp->cpu_thread = tp; 286 cp->cpu_lwp = NULL; 287 cp->cpu_dispthread = tp; 288 cp->cpu_dispatch_pri = DISP_PRIO(tp); 289 290 /* 291 * cpu_base_spl must be set explicitly here to prevent any blocking 292 * operations in mp_startup from causing the spl of the cpu to drop 293 * to 0 (allowing device interrupts before we're ready) in resume(). 294 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 295 * As an extra bit of security on DEBUG kernels, this is enforced with 296 * an assertion in mp_startup() -- before cpu_base_spl is set to its 297 * proper value. 298 */ 299 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 300 301 /* 302 * Now, initialize per-CPU idle thread for this CPU. 303 */ 304 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 305 306 cp->cpu_idle_thread = tp; 307 308 tp->t_preempt = 1; 309 tp->t_bound_cpu = cp; 310 tp->t_affinitycnt = 1; 311 tp->t_cpu = cp; 312 tp->t_disp_queue = cp->cpu_disp; 313 314 /* 315 * Bootstrap the CPU's PG data 316 */ 317 pg_cpu_bootstrap(cp); 318 319 /* 320 * Perform CPC initialization on the new CPU. 321 */ 322 kcpc_hw_init(cp); 323 324 /* 325 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 326 * for each CPU. 327 */ 328 setup_vaddr_for_ppcopy(cp); 329 330 /* 331 * Allocate page for new GDT and initialize from current GDT. 332 */ 333 #if !defined(__lint) 334 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 335 #endif 336 cp->cpu_m.mcpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 337 bcopy(CPU->cpu_m.mcpu_gdt, cp->cpu_m.mcpu_gdt, 338 (sizeof (*cp->cpu_m.mcpu_gdt) * NGDT)); 339 340 #if defined(__i386) 341 /* 342 * setup kernel %gs. 343 */ 344 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 345 SEL_KPL, 0, 1); 346 #endif 347 348 /* 349 * If we have more than one node, each cpu gets a copy of IDT 350 * local to its node. If this is a Pentium box, we use cpu 0's 351 * IDT. cpu 0's IDT has been made read-only to workaround the 352 * cmpxchgl register bug 353 */ 354 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 355 struct machcpu *mcpu = &cp->cpu_m; 356 357 mcpu->mcpu_idt = kmem_alloc(sizeof (idt0), KM_SLEEP); 358 bcopy(idt0, mcpu->mcpu_idt, sizeof (idt0)); 359 } else { 360 cp->cpu_m.mcpu_idt = CPU->cpu_m.mcpu_idt; 361 } 362 363 /* 364 * Get interrupt priority data from cpu 0. 365 */ 366 cp->cpu_pri_data = CPU->cpu_pri_data; 367 368 /* 369 * alloc space for cpuid info 370 */ 371 cpuid_alloc_space(cp); 372 373 hat_cpu_online(cp); 374 375 #ifdef TRAPTRACE 376 /* 377 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 378 */ 379 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 380 ttc->ttc_next = ttc->ttc_first; 381 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 382 #endif 383 /* 384 * Record that we have another CPU. 385 */ 386 mutex_enter(&cpu_lock); 387 /* 388 * Initialize the interrupt threads for this CPU 389 */ 390 cpu_intr_alloc(cp, NINTR_THREADS); 391 /* 392 * Add CPU to list of available CPUs. It'll be on the active list 393 * after mp_startup(). 394 */ 395 cpu_add_unit(cp); 396 mutex_exit(&cpu_lock); 397 398 return (cp); 399 } 400 401 /* 402 * Undo what was done in mp_startup_init 403 */ 404 static void 405 mp_startup_fini(struct cpu *cp, int error) 406 { 407 mutex_enter(&cpu_lock); 408 409 /* 410 * Remove the CPU from the list of available CPUs. 411 */ 412 cpu_del_unit(cp->cpu_id); 413 414 if (error == ETIMEDOUT) { 415 /* 416 * The cpu was started, but never *seemed* to run any 417 * code in the kernel; it's probably off spinning in its 418 * own private world, though with potential references to 419 * our kmem-allocated IDTs and GDTs (for example). 420 * 421 * Worse still, it may actually wake up some time later, 422 * so rather than guess what it might or might not do, we 423 * leave the fundamental data structures intact. 424 */ 425 cp->cpu_flags = 0; 426 mutex_exit(&cpu_lock); 427 return; 428 } 429 430 /* 431 * At this point, the only threads bound to this CPU should 432 * special per-cpu threads: it's idle thread, it's pause threads, 433 * and it's interrupt threads. Clean these up. 434 */ 435 cpu_destroy_bound_threads(cp); 436 cp->cpu_idle_thread = NULL; 437 438 /* 439 * Free the interrupt stack. 440 */ 441 segkp_release(segkp, 442 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 443 444 mutex_exit(&cpu_lock); 445 446 #ifdef TRAPTRACE 447 /* 448 * Discard the trap trace buffer 449 */ 450 { 451 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 452 453 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 454 ttc->ttc_first = NULL; 455 } 456 #endif 457 458 hat_cpu_offline(cp); 459 460 cpuid_free_space(cp); 461 462 if (cp->cpu_m.mcpu_idt != CPU->cpu_m.mcpu_idt) 463 kmem_free(cp->cpu_m.mcpu_idt, sizeof (idt0)); 464 cp->cpu_m.mcpu_idt = NULL; 465 466 kmem_free(cp->cpu_m.mcpu_gdt, PAGESIZE); 467 cp->cpu_m.mcpu_gdt = NULL; 468 469 teardown_vaddr_for_ppcopy(cp); 470 471 kcpc_hw_fini(cp); 472 473 cp->cpu_dispthread = NULL; 474 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 475 476 cpu_vm_data_destroy(cp); 477 478 mutex_enter(&cpu_lock); 479 disp_cpu_fini(cp); 480 mutex_exit(&cpu_lock); 481 482 kmem_free(cp, sizeof (*cp)); 483 } 484 485 /* 486 * Apply workarounds for known errata, and warn about those that are absent. 487 * 488 * System vendors occasionally create configurations which contain different 489 * revisions of the CPUs that are almost but not exactly the same. At the 490 * time of writing, this meant that their clock rates were the same, their 491 * feature sets were the same, but the required workaround were -not- 492 * necessarily the same. So, this routine is invoked on -every- CPU soon 493 * after starting to make sure that the resulting system contains the most 494 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 495 * system. 496 * 497 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 498 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 499 * to acknowledging their readiness to the master, so this routine will 500 * never be executed by multiple CPUs in parallel, thus making updates to 501 * global data safe. 502 * 503 * These workarounds are based on Rev 3.57 of the Revision Guide for 504 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 505 */ 506 507 #if defined(OPTERON_ERRATUM_88) 508 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 509 #endif 510 511 #if defined(OPTERON_ERRATUM_91) 512 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 513 #endif 514 515 #if defined(OPTERON_ERRATUM_93) 516 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 517 #endif 518 519 #if defined(OPTERON_ERRATUM_95) 520 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 521 #endif 522 523 #if defined(OPTERON_ERRATUM_100) 524 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 525 #endif 526 527 #if defined(OPTERON_ERRATUM_108) 528 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 529 #endif 530 531 #if defined(OPTERON_ERRATUM_109) 532 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 533 #endif 534 535 #if defined(OPTERON_ERRATUM_121) 536 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 537 #endif 538 539 #if defined(OPTERON_ERRATUM_122) 540 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 541 #endif 542 543 #if defined(OPTERON_ERRATUM_123) 544 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 545 #endif 546 547 #if defined(OPTERON_ERRATUM_131) 548 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 549 #endif 550 551 #if defined(OPTERON_WORKAROUND_6336786) 552 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 553 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 554 #endif 555 556 #if defined(OPTERON_WORKAROUND_6323525) 557 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 558 #endif 559 560 static void 561 workaround_warning(cpu_t *cp, uint_t erratum) 562 { 563 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 564 cp->cpu_id, erratum); 565 } 566 567 static void 568 workaround_applied(uint_t erratum) 569 { 570 if (erratum > 1000000) 571 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 572 erratum); 573 else 574 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 575 erratum); 576 } 577 578 static void 579 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 580 { 581 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 582 cp->cpu_id, rw, msr, error); 583 } 584 585 uint_t 586 workaround_errata(struct cpu *cpu) 587 { 588 uint_t missing = 0; 589 590 ASSERT(cpu == CPU); 591 592 /*LINTED*/ 593 if (cpuid_opteron_erratum(cpu, 88) > 0) { 594 /* 595 * SWAPGS May Fail To Read Correct GS Base 596 */ 597 #if defined(OPTERON_ERRATUM_88) 598 /* 599 * The workaround is an mfence in the relevant assembler code 600 */ 601 opteron_erratum_88++; 602 #else 603 workaround_warning(cpu, 88); 604 missing++; 605 #endif 606 } 607 608 if (cpuid_opteron_erratum(cpu, 91) > 0) { 609 /* 610 * Software Prefetches May Report A Page Fault 611 */ 612 #if defined(OPTERON_ERRATUM_91) 613 /* 614 * fix is in trap.c 615 */ 616 opteron_erratum_91++; 617 #else 618 workaround_warning(cpu, 91); 619 missing++; 620 #endif 621 } 622 623 if (cpuid_opteron_erratum(cpu, 93) > 0) { 624 /* 625 * RSM Auto-Halt Restart Returns to Incorrect RIP 626 */ 627 #if defined(OPTERON_ERRATUM_93) 628 /* 629 * fix is in trap.c 630 */ 631 opteron_erratum_93++; 632 #else 633 workaround_warning(cpu, 93); 634 missing++; 635 #endif 636 } 637 638 /*LINTED*/ 639 if (cpuid_opteron_erratum(cpu, 95) > 0) { 640 /* 641 * RET Instruction May Return to Incorrect EIP 642 */ 643 #if defined(OPTERON_ERRATUM_95) 644 #if defined(_LP64) 645 /* 646 * Workaround this by ensuring that 32-bit user code and 647 * 64-bit kernel code never occupy the same address 648 * range mod 4G. 649 */ 650 if (_userlimit32 > 0xc0000000ul) 651 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 652 653 /*LINTED*/ 654 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 655 opteron_erratum_95++; 656 #endif /* _LP64 */ 657 #else 658 workaround_warning(cpu, 95); 659 missing++; 660 #endif 661 } 662 663 if (cpuid_opteron_erratum(cpu, 100) > 0) { 664 /* 665 * Compatibility Mode Branches Transfer to Illegal Address 666 */ 667 #if defined(OPTERON_ERRATUM_100) 668 /* 669 * fix is in trap.c 670 */ 671 opteron_erratum_100++; 672 #else 673 workaround_warning(cpu, 100); 674 missing++; 675 #endif 676 } 677 678 /*LINTED*/ 679 if (cpuid_opteron_erratum(cpu, 108) > 0) { 680 /* 681 * CPUID Instruction May Return Incorrect Model Number In 682 * Some Processors 683 */ 684 #if defined(OPTERON_ERRATUM_108) 685 /* 686 * (Our cpuid-handling code corrects the model number on 687 * those processors) 688 */ 689 #else 690 workaround_warning(cpu, 108); 691 missing++; 692 #endif 693 } 694 695 /*LINTED*/ 696 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 697 /* 698 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 699 */ 700 #if defined(OPTERON_ERRATUM_109) 701 /* 702 * The "workaround" is to print a warning to upgrade the BIOS 703 */ 704 uint64_t value; 705 const uint_t msr = MSR_AMD_PATCHLEVEL; 706 int err; 707 708 if ((err = checked_rdmsr(msr, &value)) != 0) { 709 msr_warning(cpu, "rd", msr, err); 710 workaround_warning(cpu, 109); 711 missing++; 712 } 713 if (value == 0) 714 opteron_erratum_109++; 715 #else 716 workaround_warning(cpu, 109); 717 missing++; 718 #endif 719 /*CONSTANTCONDITION*/ 720 } while (0); 721 722 /*LINTED*/ 723 if (cpuid_opteron_erratum(cpu, 121) > 0) { 724 /* 725 * Sequential Execution Across Non_Canonical Boundary Caused 726 * Processor Hang 727 */ 728 #if defined(OPTERON_ERRATUM_121) 729 #if defined(_LP64) 730 /* 731 * Erratum 121 is only present in long (64 bit) mode. 732 * Workaround is to include the page immediately before the 733 * va hole to eliminate the possibility of system hangs due to 734 * sequential execution across the va hole boundary. 735 */ 736 if (opteron_erratum_121) 737 opteron_erratum_121++; 738 else { 739 if (hole_start) { 740 hole_start -= PAGESIZE; 741 } else { 742 /* 743 * hole_start not yet initialized by 744 * mmu_init. Initialize hole_start 745 * with value to be subtracted. 746 */ 747 hole_start = PAGESIZE; 748 } 749 opteron_erratum_121++; 750 } 751 #endif /* _LP64 */ 752 #else 753 workaround_warning(cpu, 121); 754 missing++; 755 #endif 756 } 757 758 /*LINTED*/ 759 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 760 /* 761 * TLB Flush Filter May Cause Coherency Problem in 762 * Multiprocessor Systems 763 */ 764 #if defined(OPTERON_ERRATUM_122) 765 uint64_t value; 766 const uint_t msr = MSR_AMD_HWCR; 767 int error; 768 769 /* 770 * Erratum 122 is only present in MP configurations (multi-core 771 * or multi-processor). 772 */ 773 if (!opteron_erratum_122 && lgrp_plat_node_cnt == 1 && 774 cpuid_get_ncpu_per_chip(cpu) == 1) 775 break; 776 777 /* disable TLB Flush Filter */ 778 779 if ((error = checked_rdmsr(msr, &value)) != 0) { 780 msr_warning(cpu, "rd", msr, error); 781 workaround_warning(cpu, 122); 782 missing++; 783 } else { 784 value |= (uint64_t)AMD_HWCR_FFDIS; 785 if ((error = checked_wrmsr(msr, value)) != 0) { 786 msr_warning(cpu, "wr", msr, error); 787 workaround_warning(cpu, 122); 788 missing++; 789 } 790 } 791 opteron_erratum_122++; 792 #else 793 workaround_warning(cpu, 122); 794 missing++; 795 #endif 796 /*CONSTANTCONDITION*/ 797 } while (0); 798 799 /*LINTED*/ 800 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 801 /* 802 * Bypassed Reads May Cause Data Corruption of System Hang in 803 * Dual Core Processors 804 */ 805 #if defined(OPTERON_ERRATUM_123) 806 uint64_t value; 807 const uint_t msr = MSR_AMD_PATCHLEVEL; 808 int err; 809 810 /* 811 * Erratum 123 applies only to multi-core cpus. 812 */ 813 if (cpuid_get_ncpu_per_chip(cpu) < 2) 814 break; 815 816 /* 817 * The "workaround" is to print a warning to upgrade the BIOS 818 */ 819 if ((err = checked_rdmsr(msr, &value)) != 0) { 820 msr_warning(cpu, "rd", msr, err); 821 workaround_warning(cpu, 123); 822 missing++; 823 } 824 if (value == 0) 825 opteron_erratum_123++; 826 #else 827 workaround_warning(cpu, 123); 828 missing++; 829 830 #endif 831 /*CONSTANTCONDITION*/ 832 } while (0); 833 834 /*LINTED*/ 835 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 836 /* 837 * Multiprocessor Systems with Four or More Cores May Deadlock 838 * Waiting for a Probe Response 839 */ 840 #if defined(OPTERON_ERRATUM_131) 841 uint64_t nbcfg; 842 const uint_t msr = MSR_AMD_NB_CFG; 843 const uint64_t wabits = 844 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 845 int error; 846 847 /* 848 * Erratum 131 applies to any system with four or more cores. 849 */ 850 if (opteron_erratum_131) 851 break; 852 853 if (lgrp_plat_node_cnt * cpuid_get_ncpu_per_chip(cpu) < 4) 854 break; 855 856 /* 857 * Print a warning if neither of the workarounds for 858 * erratum 131 is present. 859 */ 860 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 861 msr_warning(cpu, "rd", msr, error); 862 workaround_warning(cpu, 131); 863 missing++; 864 } else if ((nbcfg & wabits) == 0) { 865 opteron_erratum_131++; 866 } else { 867 /* cannot have both workarounds set */ 868 ASSERT((nbcfg & wabits) != wabits); 869 } 870 #else 871 workaround_warning(cpu, 131); 872 missing++; 873 #endif 874 /*CONSTANTCONDITION*/ 875 } while (0); 876 877 /* 878 * This isn't really an erratum, but for convenience the 879 * detection/workaround code lives here and in cpuid_opteron_erratum. 880 */ 881 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 882 #if defined(OPTERON_WORKAROUND_6336786) 883 /* 884 * Disable C1-Clock ramping on multi-core/multi-processor 885 * K8 platforms to guard against TSC drift. 886 */ 887 if (opteron_workaround_6336786) { 888 opteron_workaround_6336786++; 889 } else if ((lgrp_plat_node_cnt * 890 cpuid_get_ncpu_per_chip(cpu) > 1) || 891 opteron_workaround_6336786_UP) { 892 int node; 893 uint8_t data; 894 895 for (node = 0; node < lgrp_plat_node_cnt; node++) { 896 /* 897 * Clear PMM7[1:0] (function 3, offset 0x87) 898 * Northbridge device is the node id + 24. 899 */ 900 data = pci_getb_func(0, node + 24, 3, 0x87); 901 data &= 0xFC; 902 pci_putb_func(0, node + 24, 3, 0x87, data); 903 } 904 opteron_workaround_6336786++; 905 } 906 #else 907 workaround_warning(cpu, 6336786); 908 missing++; 909 #endif 910 } 911 912 /*LINTED*/ 913 /* 914 * Mutex primitives don't work as expected. 915 */ 916 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 917 #if defined(OPTERON_WORKAROUND_6323525) 918 /* 919 * This problem only occurs with 2 or more cores. If bit in 920 * MSR_BU_CFG set, then not applicable. The workaround 921 * is to patch the semaphone routines with the lfence 922 * instruction to provide necessary load memory barrier with 923 * possible subsequent read-modify-write ops. 924 * 925 * It is too early in boot to call the patch routine so 926 * set erratum variable to be done in startup_end(). 927 */ 928 if (opteron_workaround_6323525) { 929 opteron_workaround_6323525++; 930 } else if ((x86_feature & X86_SSE2) && ((lgrp_plat_node_cnt * 931 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 932 if ((xrdmsr(MSR_BU_CFG) & 0x02) == 0) 933 opteron_workaround_6323525++; 934 } 935 #else 936 workaround_warning(cpu, 6323525); 937 missing++; 938 #endif 939 } 940 941 return (missing); 942 } 943 944 void 945 workaround_errata_end() 946 { 947 #if defined(OPTERON_ERRATUM_88) 948 if (opteron_erratum_88) 949 workaround_applied(88); 950 #endif 951 #if defined(OPTERON_ERRATUM_91) 952 if (opteron_erratum_91) 953 workaround_applied(91); 954 #endif 955 #if defined(OPTERON_ERRATUM_93) 956 if (opteron_erratum_93) 957 workaround_applied(93); 958 #endif 959 #if defined(OPTERON_ERRATUM_95) 960 if (opteron_erratum_95) 961 workaround_applied(95); 962 #endif 963 #if defined(OPTERON_ERRATUM_100) 964 if (opteron_erratum_100) 965 workaround_applied(100); 966 #endif 967 #if defined(OPTERON_ERRATUM_108) 968 if (opteron_erratum_108) 969 workaround_applied(108); 970 #endif 971 #if defined(OPTERON_ERRATUM_109) 972 if (opteron_erratum_109) { 973 cmn_err(CE_WARN, 974 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 975 " processor\nerratum 109 was not detected; updating your" 976 " system's BIOS to a version\ncontaining this" 977 " microcode patch is HIGHLY recommended or erroneous" 978 " system\noperation may occur.\n"); 979 } 980 #endif 981 #if defined(OPTERON_ERRATUM_121) 982 if (opteron_erratum_121) 983 workaround_applied(121); 984 #endif 985 #if defined(OPTERON_ERRATUM_122) 986 if (opteron_erratum_122) 987 workaround_applied(122); 988 #endif 989 #if defined(OPTERON_ERRATUM_123) 990 if (opteron_erratum_123) { 991 cmn_err(CE_WARN, 992 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 993 " processor\nerratum 123 was not detected; updating your" 994 " system's BIOS to a version\ncontaining this" 995 " microcode patch is HIGHLY recommended or erroneous" 996 " system\noperation may occur.\n"); 997 } 998 #endif 999 #if defined(OPTERON_ERRATUM_131) 1000 if (opteron_erratum_131) { 1001 cmn_err(CE_WARN, 1002 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1003 " processor\nerratum 131 was not detected; updating your" 1004 " system's BIOS to a version\ncontaining this" 1005 " microcode patch is HIGHLY recommended or erroneous" 1006 " system\noperation may occur.\n"); 1007 } 1008 #endif 1009 #if defined(OPTERON_WORKAROUND_6336786) 1010 if (opteron_workaround_6336786) 1011 workaround_applied(6336786); 1012 #endif 1013 #if defined(OPTERON_WORKAROUND_6323525) 1014 if (opteron_workaround_6323525) 1015 workaround_applied(6323525); 1016 #endif 1017 } 1018 1019 static cpuset_t procset; 1020 1021 /* 1022 * Start a single cpu, assuming that the kernel context is available 1023 * to successfully start another cpu. 1024 * 1025 * (For example, real mode code is mapped into the right place 1026 * in memory and is ready to be run.) 1027 */ 1028 int 1029 start_cpu(processorid_t who) 1030 { 1031 void *ctx; 1032 cpu_t *cp; 1033 int delays; 1034 int error = 0; 1035 1036 ASSERT(who != 0); 1037 1038 /* 1039 * Check if there's at least a Mbyte of kmem available 1040 * before attempting to start the cpu. 1041 */ 1042 if (kmem_avail() < 1024 * 1024) { 1043 /* 1044 * Kick off a reap in case that helps us with 1045 * later attempts .. 1046 */ 1047 kmem_reap(); 1048 return (ENOMEM); 1049 } 1050 1051 cp = mp_startup_init(who); 1052 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1053 (error = mach_cpu_start(cp, ctx)) != 0) { 1054 1055 /* 1056 * Something went wrong before we even started it 1057 */ 1058 if (ctx) 1059 cmn_err(CE_WARN, 1060 "cpu%d: failed to start error %d", 1061 cp->cpu_id, error); 1062 else 1063 cmn_err(CE_WARN, 1064 "cpu%d: failed to allocate context", cp->cpu_id); 1065 1066 if (ctx) 1067 mach_cpucontext_free(cp, ctx, error); 1068 else 1069 error = EAGAIN; /* hmm. */ 1070 mp_startup_fini(cp, error); 1071 return (error); 1072 } 1073 1074 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1075 if (delays == 500) { 1076 /* 1077 * After five seconds, things are probably looking 1078 * a bit bleak - explain the hang. 1079 */ 1080 cmn_err(CE_NOTE, "cpu%d: started, " 1081 "but not running in the kernel yet", who); 1082 } else if (delays > 2000) { 1083 /* 1084 * We waited at least 20 seconds, bail .. 1085 */ 1086 error = ETIMEDOUT; 1087 cmn_err(CE_WARN, "cpu%d: timed out", who); 1088 mach_cpucontext_free(cp, ctx, error); 1089 mp_startup_fini(cp, error); 1090 return (error); 1091 } 1092 1093 /* 1094 * wait at least 10ms, then check again.. 1095 */ 1096 delay(USEC_TO_TICK_ROUNDUP(10000)); 1097 } 1098 1099 mach_cpucontext_free(cp, ctx, 0); 1100 1101 if (tsc_gethrtime_enable) 1102 tsc_sync_master(who); 1103 1104 if (dtrace_cpu_init != NULL) { 1105 /* 1106 * DTrace CPU initialization expects cpu_lock to be held. 1107 */ 1108 mutex_enter(&cpu_lock); 1109 (*dtrace_cpu_init)(who); 1110 mutex_exit(&cpu_lock); 1111 } 1112 1113 while (!CPU_IN_SET(cpu_ready_set, who)) 1114 delay(1); 1115 1116 return (0); 1117 } 1118 1119 1120 /*ARGSUSED*/ 1121 void 1122 start_other_cpus(int cprboot) 1123 { 1124 uint_t who; 1125 uint_t skipped = 0; 1126 uint_t bootcpuid = 0; 1127 1128 /* 1129 * Initialize our own cpu_info. 1130 */ 1131 init_cpu_info(CPU); 1132 1133 /* 1134 * Initialize our syscall handlers 1135 */ 1136 init_cpu_syscall(CPU); 1137 1138 /* 1139 * Take the boot cpu out of the mp_cpus set because we know 1140 * it's already running. Add it to the cpu_ready_set for 1141 * precisely the same reason. 1142 */ 1143 CPUSET_DEL(mp_cpus, bootcpuid); 1144 CPUSET_ADD(cpu_ready_set, bootcpuid); 1145 1146 /* 1147 * if only 1 cpu or not using MP, skip the rest of this 1148 */ 1149 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1150 if (use_mp == 0) 1151 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1152 goto done; 1153 } 1154 1155 /* 1156 * perform such initialization as is needed 1157 * to be able to take CPUs on- and off-line. 1158 */ 1159 cpu_pause_init(); 1160 1161 xc_init(); /* initialize processor crosscalls */ 1162 1163 if (mach_cpucontext_init() != 0) 1164 goto done; 1165 1166 flushes_require_xcalls = 1; 1167 1168 /* 1169 * We lock our affinity to the master CPU to ensure that all slave CPUs 1170 * do their TSC syncs with the same CPU. 1171 */ 1172 affinity_set(CPU_CURRENT); 1173 1174 for (who = 0; who < NCPU; who++) { 1175 1176 if (!CPU_IN_SET(mp_cpus, who)) 1177 continue; 1178 ASSERT(who != bootcpuid); 1179 if (ncpus >= max_ncpus) { 1180 skipped = who; 1181 continue; 1182 } 1183 if (start_cpu(who) != 0) 1184 CPUSET_DEL(mp_cpus, who); 1185 } 1186 1187 affinity_clear(); 1188 1189 if (skipped) { 1190 cmn_err(CE_NOTE, 1191 "System detected %d cpus, but " 1192 "only %d cpu(s) were enabled during boot.", 1193 skipped + 1, ncpus); 1194 cmn_err(CE_NOTE, 1195 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1196 "See eeprom(1M)."); 1197 } 1198 1199 done: 1200 workaround_errata_end(); 1201 mach_cpucontext_fini(); 1202 1203 cmi_post_mpstartup(); 1204 } 1205 1206 /* 1207 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1208 */ 1209 /*ARGSUSED*/ 1210 int 1211 mp_cpu_configure(int cpuid) 1212 { 1213 return (ENOTSUP); /* not supported */ 1214 } 1215 1216 /*ARGSUSED*/ 1217 int 1218 mp_cpu_unconfigure(int cpuid) 1219 { 1220 return (ENOTSUP); /* not supported */ 1221 } 1222 1223 /* 1224 * Startup function for 'other' CPUs (besides boot cpu). 1225 * Called from real_mode_start. 1226 * 1227 * WARNING: until CPU_READY is set, mp_startup and routines called by 1228 * mp_startup should not call routines (e.g. kmem_free) that could call 1229 * hat_unload which requires CPU_READY to be set. 1230 */ 1231 void 1232 mp_startup(void) 1233 { 1234 struct cpu *cp = CPU; 1235 uint_t new_x86_feature; 1236 1237 /* 1238 * We need to get TSC on this proc synced (i.e., any delta 1239 * from cpu0 accounted for) as soon as we can, because many 1240 * many things use gethrtime/pc_gethrestime, including 1241 * interrupts, cmn_err, etc. 1242 */ 1243 1244 /* Let cpu0 continue into tsc_sync_master() */ 1245 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1246 1247 if (tsc_gethrtime_enable) 1248 tsc_sync_slave(); 1249 1250 /* 1251 * Once this was done from assembly, but it's safer here; if 1252 * it blocks, we need to be able to swtch() to and from, and 1253 * since we get here by calling t_pc, we need to do that call 1254 * before swtch() overwrites it. 1255 */ 1256 1257 (void) (*ap_mlsetup)(); 1258 1259 new_x86_feature = cpuid_pass1(cp); 1260 1261 /* 1262 * We need to Sync MTRR with cpu0's MTRR. We have to do 1263 * this with interrupts disabled. 1264 */ 1265 if (x86_feature & X86_MTRR) 1266 mtrr_sync(); 1267 1268 /* 1269 * Set up TSC_AUX to contain the cpuid for this processor 1270 * for the rdtscp instruction. 1271 */ 1272 if (x86_feature & X86_TSCP) 1273 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1274 1275 /* 1276 * Initialize this CPU's syscall handlers 1277 */ 1278 init_cpu_syscall(cp); 1279 1280 /* 1281 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1282 * highest level at which a routine is permitted to block on 1283 * an adaptive mutex (allows for cpu poke interrupt in case 1284 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1285 * device interrupts that may end up in the hat layer issuing cross 1286 * calls before CPU_READY is set. 1287 */ 1288 splx(ipltospl(LOCK_LEVEL)); 1289 sti(); 1290 1291 /* 1292 * Do a sanity check to make sure this new CPU is a sane thing 1293 * to add to the collection of processors running this system. 1294 * 1295 * XXX Clearly this needs to get more sophisticated, if x86 1296 * systems start to get built out of heterogenous CPUs; as is 1297 * likely to happen once the number of processors in a configuration 1298 * gets large enough. 1299 */ 1300 if ((x86_feature & new_x86_feature) != x86_feature) { 1301 cmn_err(CE_CONT, "?cpu%d: %b\n", 1302 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1303 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1304 } 1305 1306 /* 1307 * We could be more sophisticated here, and just mark the CPU 1308 * as "faulted" but at this point we'll opt for the easier 1309 * answer of dieing horribly. Provided the boot cpu is ok, 1310 * the system can be recovered by booting with use_mp set to zero. 1311 */ 1312 if (workaround_errata(cp) != 0) 1313 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1314 1315 cpuid_pass2(cp); 1316 cpuid_pass3(cp); 1317 (void) cpuid_pass4(cp); 1318 1319 init_cpu_info(cp); 1320 1321 mutex_enter(&cpu_lock); 1322 /* 1323 * Processor group initialization for this CPU is dependent on the 1324 * cpuid probing, which must be done in the context of the current 1325 * CPU. 1326 */ 1327 pghw_physid_create(cp); 1328 pg_cpu_init(cp); 1329 pg_cmt_cpu_startup(cp); 1330 1331 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_ENABLE | CPU_EXISTS; 1332 cpu_add_active(cp); 1333 1334 if (dtrace_cpu_init != NULL) { 1335 (*dtrace_cpu_init)(cp->cpu_id); 1336 } 1337 1338 mutex_exit(&cpu_lock); 1339 1340 /* 1341 * Enable preemption here so that contention for any locks acquired 1342 * later in mp_startup may be preempted if the thread owning those 1343 * locks is continously executing on other CPUs (for example, this 1344 * CPU must be preemptible to allow other CPUs to pause it during their 1345 * startup phases). It's safe to enable preemption here because the 1346 * CPU state is pretty-much fully constructed. 1347 */ 1348 curthread->t_preempt = 0; 1349 1350 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1351 1352 /* The base spl should still be at LOCK LEVEL here */ 1353 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1354 set_base_spl(); /* Restore the spl to its proper value */ 1355 1356 (void) spl0(); /* enable interrupts */ 1357 1358 /* 1359 * Set up the CPU module for this CPU. This can't be done before 1360 * this CPU is made CPU_READY, because we may (in heterogeneous systems) 1361 * need to go load another CPU module. The act of attempting to load 1362 * a module may trigger a cross-call, which will ASSERT unless this 1363 * cpu is CPU_READY. 1364 */ 1365 cmi_init(); 1366 1367 if (x86_feature & X86_MCA) 1368 cmi_mca_init(); 1369 1370 if (boothowto & RB_DEBUG) 1371 kdi_cpu_init(); 1372 1373 /* 1374 * Setting the bit in cpu_ready_set must be the last operation in 1375 * processor initialization; the boot CPU will continue to boot once 1376 * it sees this bit set for all active CPUs. 1377 */ 1378 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1379 1380 /* 1381 * Because mp_startup() gets fired off after init() starts, we 1382 * can't use the '?' trick to do 'boot -v' printing - so we 1383 * always direct the 'cpu .. online' messages to the log. 1384 */ 1385 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1386 cp->cpu_id); 1387 1388 /* 1389 * Now we are done with the startup thread, so free it up. 1390 */ 1391 thread_exit(); 1392 panic("mp_startup: cannot return"); 1393 /*NOTREACHED*/ 1394 } 1395 1396 1397 /* 1398 * Start CPU on user request. 1399 */ 1400 /* ARGSUSED */ 1401 int 1402 mp_cpu_start(struct cpu *cp) 1403 { 1404 ASSERT(MUTEX_HELD(&cpu_lock)); 1405 return (0); 1406 } 1407 1408 /* 1409 * Stop CPU on user request. 1410 */ 1411 /* ARGSUSED */ 1412 int 1413 mp_cpu_stop(struct cpu *cp) 1414 { 1415 extern int cbe_psm_timer_mode; 1416 ASSERT(MUTEX_HELD(&cpu_lock)); 1417 1418 /* 1419 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1420 * can't stop it. (This is true only for machines with no TSC.) 1421 */ 1422 1423 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1424 return (1); 1425 1426 return (0); 1427 } 1428 1429 /* 1430 * Take the specified CPU out of participation in interrupts. 1431 */ 1432 int 1433 cpu_disable_intr(struct cpu *cp) 1434 { 1435 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1436 return (EBUSY); 1437 1438 cp->cpu_flags &= ~CPU_ENABLE; 1439 return (0); 1440 } 1441 1442 /* 1443 * Allow the specified CPU to participate in interrupts. 1444 */ 1445 void 1446 cpu_enable_intr(struct cpu *cp) 1447 { 1448 ASSERT(MUTEX_HELD(&cpu_lock)); 1449 cp->cpu_flags |= CPU_ENABLE; 1450 psm_enable_intr(cp->cpu_id); 1451 } 1452 1453 1454 1455 void 1456 mp_cpu_faulted_enter(struct cpu *cp) 1457 { 1458 cmi_faulted_enter(cp); 1459 } 1460 1461 void 1462 mp_cpu_faulted_exit(struct cpu *cp) 1463 { 1464 cmi_faulted_exit(cp); 1465 } 1466 1467 /* 1468 * The following two routines are used as context operators on threads belonging 1469 * to processes with a private LDT (see sysi86). Due to the rarity of such 1470 * processes, these routines are currently written for best code readability and 1471 * organization rather than speed. We could avoid checking x86_feature at every 1472 * context switch by installing different context ops, depending on the 1473 * x86_feature flags, at LDT creation time -- one for each combination of fast 1474 * syscall feature flags. 1475 */ 1476 1477 /*ARGSUSED*/ 1478 void 1479 cpu_fast_syscall_disable(void *arg) 1480 { 1481 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1482 cpu_sep_disable(); 1483 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1484 cpu_asysc_disable(); 1485 } 1486 1487 /*ARGSUSED*/ 1488 void 1489 cpu_fast_syscall_enable(void *arg) 1490 { 1491 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1492 cpu_sep_enable(); 1493 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1494 cpu_asysc_enable(); 1495 } 1496 1497 static void 1498 cpu_sep_enable(void) 1499 { 1500 ASSERT(x86_feature & X86_SEP); 1501 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1502 1503 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1504 } 1505 1506 static void 1507 cpu_sep_disable(void) 1508 { 1509 ASSERT(x86_feature & X86_SEP); 1510 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1511 1512 /* 1513 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1514 * the sysenter or sysexit instruction to trigger a #gp fault. 1515 */ 1516 wrmsr(MSR_INTC_SEP_CS, 0); 1517 } 1518 1519 static void 1520 cpu_asysc_enable(void) 1521 { 1522 ASSERT(x86_feature & X86_ASYSC); 1523 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1524 1525 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1526 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1527 } 1528 1529 static void 1530 cpu_asysc_disable(void) 1531 { 1532 ASSERT(x86_feature & X86_ASYSC); 1533 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1534 1535 /* 1536 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1537 * executing syscall or sysret with this bit off will incur a #ud trap. 1538 */ 1539 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1540 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1541 } 1542