1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 30 #include <sys/types.h> 31 #include <sys/thread.h> 32 #include <sys/cpuvar.h> 33 #include <sys/cpu.h> 34 #include <sys/t_lock.h> 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/disp.h> 38 #include <sys/class.h> 39 #include <sys/cmn_err.h> 40 #include <sys/debug.h> 41 #include <sys/note.h> 42 #include <sys/asm_linkage.h> 43 #include <sys/x_call.h> 44 #include <sys/systm.h> 45 #include <sys/var.h> 46 #include <sys/vtrace.h> 47 #include <vm/hat.h> 48 #include <vm/as.h> 49 #include <vm/seg_kmem.h> 50 #include <vm/seg_kp.h> 51 #include <sys/segments.h> 52 #include <sys/kmem.h> 53 #include <sys/stack.h> 54 #include <sys/smp_impldefs.h> 55 #include <sys/x86_archext.h> 56 #include <sys/machsystm.h> 57 #include <sys/traptrace.h> 58 #include <sys/clock.h> 59 #include <sys/cpc_impl.h> 60 #include <sys/pg.h> 61 #include <sys/cmt.h> 62 #include <sys/dtrace.h> 63 #include <sys/archsystm.h> 64 #include <sys/fp.h> 65 #include <sys/reboot.h> 66 #include <sys/kdi_machimpl.h> 67 #include <vm/hat_i86.h> 68 #include <vm/vm_dep.h> 69 #include <sys/memnode.h> 70 #include <sys/pci_cfgspace.h> 71 #include <sys/mach_mmu.h> 72 #include <sys/sysmacros.h> 73 #if defined(__xpv) 74 #include <sys/hypervisor.h> 75 #endif 76 #include <sys/cpu_module.h> 77 78 struct cpu cpus[1]; /* CPU data */ 79 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 80 struct cpu *cpu_free_list; /* list for released CPUs */ 81 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 82 83 #define cpu_next_free cpu_prev 84 85 /* 86 * Useful for disabling MP bring-up on a MP capable system. 87 */ 88 int use_mp = 1; 89 90 /* 91 * to be set by a PSM to indicate what cpus 92 * are sitting around on the system. 93 */ 94 cpuset_t mp_cpus; 95 96 /* 97 * This variable is used by the hat layer to decide whether or not 98 * critical sections are needed to prevent race conditions. For sun4m, 99 * this variable is set once enough MP initialization has been done in 100 * order to allow cross calls. 101 */ 102 int flushes_require_xcalls; 103 104 cpuset_t cpu_ready_set; /* initialized in startup() */ 105 106 static void mp_startup_boot(void); 107 static void mp_startup_hotplug(void); 108 109 static void cpu_sep_enable(void); 110 static void cpu_sep_disable(void); 111 static void cpu_asysc_enable(void); 112 static void cpu_asysc_disable(void); 113 114 /* 115 * Init CPU info - get CPU type info for processor_info system call. 116 */ 117 void 118 init_cpu_info(struct cpu *cp) 119 { 120 processor_info_t *pi = &cp->cpu_type_info; 121 122 /* 123 * Get clock-frequency property for the CPU. 124 */ 125 pi->pi_clock = cpu_freq; 126 127 /* 128 * Current frequency in Hz. 129 */ 130 cp->cpu_curr_clock = cpu_freq_hz; 131 132 /* 133 * Supported frequencies. 134 */ 135 if (cp->cpu_supp_freqs == NULL) { 136 cpu_set_supp_freqs(cp, NULL); 137 } 138 139 (void) strcpy(pi->pi_processor_type, "i386"); 140 if (fpu_exists) 141 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 142 143 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 144 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 145 146 /* 147 * If called for the BSP, cp is equal to current CPU. 148 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info 149 * of current CPU as default values for cpu_idstr and cpu_brandstr. 150 * They will be corrected in mp_startup_common() after cpuid_pass1() 151 * has been invoked on target CPU. 152 */ 153 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 154 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 155 } 156 157 /* 158 * Configure syscall support on this CPU. 159 */ 160 /*ARGSUSED*/ 161 void 162 init_cpu_syscall(struct cpu *cp) 163 { 164 kpreempt_disable(); 165 166 #if defined(__amd64) 167 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 168 is_x86_feature(x86_featureset, X86FSET_ASYSC)) { 169 170 #if !defined(__lint) 171 /* 172 * The syscall instruction imposes a certain ordering on 173 * segment selectors, so we double-check that ordering 174 * here. 175 */ 176 ASSERT(KDS_SEL == KCS_SEL + 8); 177 ASSERT(UDS_SEL == U32CS_SEL + 8); 178 ASSERT(UCS_SEL == U32CS_SEL + 16); 179 #endif 180 /* 181 * Turn syscall/sysret extensions on. 182 */ 183 cpu_asysc_enable(); 184 185 /* 186 * Program the magic registers .. 187 */ 188 wrmsr(MSR_AMD_STAR, 189 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 190 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 191 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 192 193 /* 194 * This list of flags is masked off the incoming 195 * %rfl when we enter the kernel. 196 */ 197 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 198 } 199 #endif 200 201 /* 202 * On 32-bit kernels, we use sysenter/sysexit because it's too 203 * hard to use syscall/sysret, and it is more portable anyway. 204 * 205 * On 64-bit kernels on Nocona machines, the 32-bit syscall 206 * variant isn't available to 32-bit applications, but sysenter is. 207 */ 208 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 209 is_x86_feature(x86_featureset, X86FSET_SEP)) { 210 211 #if !defined(__lint) 212 /* 213 * The sysenter instruction imposes a certain ordering on 214 * segment selectors, so we double-check that ordering 215 * here. See "sysenter" in Intel document 245471-012, "IA-32 216 * Intel Architecture Software Developer's Manual Volume 2: 217 * Instruction Set Reference" 218 */ 219 ASSERT(KDS_SEL == KCS_SEL + 8); 220 221 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 222 ASSERT32(UDS_SEL == UCS_SEL + 8); 223 224 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 225 ASSERT64(UDS_SEL == U32CS_SEL + 8); 226 #endif 227 228 cpu_sep_enable(); 229 230 /* 231 * resume() sets this value to the base of the threads stack 232 * via a context handler. 233 */ 234 wrmsr(MSR_INTC_SEP_ESP, 0); 235 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 236 } 237 238 kpreempt_enable(); 239 } 240 241 /* 242 * Multiprocessor initialization. 243 * 244 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 245 * startup and idle threads for the specified CPU. 246 * Parameter boot is true for boot time operations and is false for CPU 247 * DR operations. 248 */ 249 static struct cpu * 250 mp_cpu_configure_common(int cpun, boolean_t boot) 251 { 252 struct cpu *cp; 253 kthread_id_t tp; 254 caddr_t sp; 255 proc_t *procp; 256 #if !defined(__xpv) 257 extern int idle_cpu_prefer_mwait; 258 extern void cpu_idle_mwait(); 259 #endif 260 extern void idle(); 261 extern void cpu_idle(); 262 263 #ifdef TRAPTRACE 264 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 265 #endif 266 267 ASSERT(MUTEX_HELD(&cpu_lock)); 268 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 269 270 if (cpu_free_list == NULL) { 271 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 272 } else { 273 cp = cpu_free_list; 274 cpu_free_list = cp->cpu_next_free; 275 } 276 277 cp->cpu_m.mcpu_istamp = cpun << 16; 278 279 /* Create per CPU specific threads in the process p0. */ 280 procp = &p0; 281 282 /* 283 * Initialize the dispatcher first. 284 */ 285 disp_cpu_init(cp); 286 287 cpu_vm_data_init(cp); 288 289 /* 290 * Allocate and initialize the startup thread for this CPU. 291 * Interrupt and process switch stacks get allocated later 292 * when the CPU starts running. 293 */ 294 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 295 TS_STOPPED, maxclsyspri); 296 297 /* 298 * Set state to TS_ONPROC since this thread will start running 299 * as soon as the CPU comes online. 300 * 301 * All the other fields of the thread structure are setup by 302 * thread_create(). 303 */ 304 THREAD_ONPROC(tp, cp); 305 tp->t_preempt = 1; 306 tp->t_bound_cpu = cp; 307 tp->t_affinitycnt = 1; 308 tp->t_cpu = cp; 309 tp->t_disp_queue = cp->cpu_disp; 310 311 /* 312 * Setup thread to start in mp_startup_common. 313 */ 314 sp = tp->t_stk; 315 tp->t_sp = (uintptr_t)(sp - MINFRAME); 316 #if defined(__amd64) 317 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 318 #endif 319 /* 320 * Setup thread start entry point for boot or hotplug. 321 */ 322 if (boot) { 323 tp->t_pc = (uintptr_t)mp_startup_boot; 324 } else { 325 tp->t_pc = (uintptr_t)mp_startup_hotplug; 326 } 327 328 cp->cpu_id = cpun; 329 cp->cpu_self = cp; 330 cp->cpu_thread = tp; 331 cp->cpu_lwp = NULL; 332 cp->cpu_dispthread = tp; 333 cp->cpu_dispatch_pri = DISP_PRIO(tp); 334 335 /* 336 * cpu_base_spl must be set explicitly here to prevent any blocking 337 * operations in mp_startup_common from causing the spl of the cpu 338 * to drop to 0 (allowing device interrupts before we're ready) in 339 * resume(). 340 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 341 * As an extra bit of security on DEBUG kernels, this is enforced with 342 * an assertion in mp_startup_common() -- before cpu_base_spl is set 343 * to its proper value. 344 */ 345 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 346 347 /* 348 * Now, initialize per-CPU idle thread for this CPU. 349 */ 350 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 351 352 cp->cpu_idle_thread = tp; 353 354 tp->t_preempt = 1; 355 tp->t_bound_cpu = cp; 356 tp->t_affinitycnt = 1; 357 tp->t_cpu = cp; 358 tp->t_disp_queue = cp->cpu_disp; 359 360 /* 361 * Bootstrap the CPU's PG data 362 */ 363 pg_cpu_bootstrap(cp); 364 365 /* 366 * Perform CPC initialization on the new CPU. 367 */ 368 kcpc_hw_init(cp); 369 370 /* 371 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 372 * for each CPU. 373 */ 374 setup_vaddr_for_ppcopy(cp); 375 376 /* 377 * Allocate page for new GDT and initialize from current GDT. 378 */ 379 #if !defined(__lint) 380 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 381 #endif 382 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 383 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 384 385 #if defined(__i386) 386 /* 387 * setup kernel %gs. 388 */ 389 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 390 SEL_KPL, 0, 1); 391 #endif 392 393 /* 394 * If we have more than one node, each cpu gets a copy of IDT 395 * local to its node. If this is a Pentium box, we use cpu 0's 396 * IDT. cpu 0's IDT has been made read-only to workaround the 397 * cmpxchgl register bug 398 */ 399 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 400 #if !defined(__lint) 401 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 402 #endif 403 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 404 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 405 } else { 406 cp->cpu_idt = CPU->cpu_idt; 407 } 408 409 /* 410 * Get interrupt priority data from cpu 0. 411 */ 412 cp->cpu_pri_data = CPU->cpu_pri_data; 413 414 /* 415 * alloc space for cpuid info 416 */ 417 cpuid_alloc_space(cp); 418 #if !defined(__xpv) 419 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) && 420 idle_cpu_prefer_mwait) { 421 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp); 422 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 423 } else 424 #endif 425 cp->cpu_m.mcpu_idle_cpu = cpu_idle; 426 427 init_cpu_info(cp); 428 429 /* 430 * alloc space for ucode_info 431 */ 432 ucode_alloc_space(cp); 433 xc_init_cpu(cp); 434 hat_cpu_online(cp); 435 436 #ifdef TRAPTRACE 437 /* 438 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 439 */ 440 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 441 ttc->ttc_next = ttc->ttc_first; 442 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 443 #endif 444 445 /* 446 * Record that we have another CPU. 447 */ 448 /* 449 * Initialize the interrupt threads for this CPU 450 */ 451 cpu_intr_alloc(cp, NINTR_THREADS); 452 453 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 454 cpu_set_state(cp); 455 456 /* 457 * Add CPU to list of available CPUs. It'll be on the active list 458 * after mp_startup_common(). 459 */ 460 cpu_add_unit(cp); 461 462 return (cp); 463 } 464 465 /* 466 * Undo what was done in mp_cpu_configure_common 467 */ 468 static void 469 mp_cpu_unconfigure_common(struct cpu *cp, int error) 470 { 471 ASSERT(MUTEX_HELD(&cpu_lock)); 472 473 /* 474 * Remove the CPU from the list of available CPUs. 475 */ 476 cpu_del_unit(cp->cpu_id); 477 478 if (error == ETIMEDOUT) { 479 /* 480 * The cpu was started, but never *seemed* to run any 481 * code in the kernel; it's probably off spinning in its 482 * own private world, though with potential references to 483 * our kmem-allocated IDTs and GDTs (for example). 484 * 485 * Worse still, it may actually wake up some time later, 486 * so rather than guess what it might or might not do, we 487 * leave the fundamental data structures intact. 488 */ 489 cp->cpu_flags = 0; 490 return; 491 } 492 493 /* 494 * At this point, the only threads bound to this CPU should 495 * special per-cpu threads: it's idle thread, it's pause threads, 496 * and it's interrupt threads. Clean these up. 497 */ 498 cpu_destroy_bound_threads(cp); 499 cp->cpu_idle_thread = NULL; 500 501 /* 502 * Free the interrupt stack. 503 */ 504 segkp_release(segkp, 505 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 506 cp->cpu_intr_stack = NULL; 507 508 #ifdef TRAPTRACE 509 /* 510 * Discard the trap trace buffer 511 */ 512 { 513 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 514 515 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 516 ttc->ttc_first = NULL; 517 } 518 #endif 519 520 hat_cpu_offline(cp); 521 522 ucode_free_space(cp); 523 524 /* Free CPU ID string and brand string. */ 525 if (cp->cpu_idstr) { 526 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN); 527 cp->cpu_idstr = NULL; 528 } 529 if (cp->cpu_brandstr) { 530 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN); 531 cp->cpu_brandstr = NULL; 532 } 533 534 #if !defined(__xpv) 535 if (cp->cpu_m.mcpu_mwait != NULL) { 536 cpuid_mwait_free(cp); 537 cp->cpu_m.mcpu_mwait = NULL; 538 } 539 #endif 540 cpuid_free_space(cp); 541 542 if (cp->cpu_idt != CPU->cpu_idt) 543 kmem_free(cp->cpu_idt, PAGESIZE); 544 cp->cpu_idt = NULL; 545 546 kmem_free(cp->cpu_gdt, PAGESIZE); 547 cp->cpu_gdt = NULL; 548 549 if (cp->cpu_supp_freqs != NULL) { 550 size_t len = strlen(cp->cpu_supp_freqs) + 1; 551 kmem_free(cp->cpu_supp_freqs, len); 552 cp->cpu_supp_freqs = NULL; 553 } 554 555 teardown_vaddr_for_ppcopy(cp); 556 557 kcpc_hw_fini(cp); 558 559 cp->cpu_dispthread = NULL; 560 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 561 562 cpu_vm_data_destroy(cp); 563 564 xc_fini_cpu(cp); 565 disp_cpu_fini(cp); 566 567 ASSERT(cp != CPU0); 568 bzero(cp, sizeof (*cp)); 569 cp->cpu_next_free = cpu_free_list; 570 cpu_free_list = cp; 571 } 572 573 /* 574 * Apply workarounds for known errata, and warn about those that are absent. 575 * 576 * System vendors occasionally create configurations which contain different 577 * revisions of the CPUs that are almost but not exactly the same. At the 578 * time of writing, this meant that their clock rates were the same, their 579 * feature sets were the same, but the required workaround were -not- 580 * necessarily the same. So, this routine is invoked on -every- CPU soon 581 * after starting to make sure that the resulting system contains the most 582 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 583 * system. 584 * 585 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 586 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata 587 * prior to acknowledging their readiness to the master, so this routine will 588 * never be executed by multiple CPUs in parallel, thus making updates to 589 * global data safe. 590 * 591 * These workarounds are based on Rev 3.57 of the Revision Guide for 592 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 593 */ 594 595 #if defined(OPTERON_ERRATUM_88) 596 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 597 #endif 598 599 #if defined(OPTERON_ERRATUM_91) 600 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 601 #endif 602 603 #if defined(OPTERON_ERRATUM_93) 604 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 605 #endif 606 607 #if defined(OPTERON_ERRATUM_95) 608 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 609 #endif 610 611 #if defined(OPTERON_ERRATUM_100) 612 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 613 #endif 614 615 #if defined(OPTERON_ERRATUM_108) 616 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 617 #endif 618 619 #if defined(OPTERON_ERRATUM_109) 620 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 621 #endif 622 623 #if defined(OPTERON_ERRATUM_121) 624 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 625 #endif 626 627 #if defined(OPTERON_ERRATUM_122) 628 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 629 #endif 630 631 #if defined(OPTERON_ERRATUM_123) 632 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 633 #endif 634 635 #if defined(OPTERON_ERRATUM_131) 636 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 637 #endif 638 639 #if defined(OPTERON_WORKAROUND_6336786) 640 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 641 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 642 #endif 643 644 #if defined(OPTERON_WORKAROUND_6323525) 645 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 646 #endif 647 648 #if defined(OPTERON_ERRATUM_298) 649 int opteron_erratum_298; 650 #endif 651 652 #if defined(OPTERON_ERRATUM_721) 653 int opteron_erratum_721; 654 #endif 655 656 static void 657 workaround_warning(cpu_t *cp, uint_t erratum) 658 { 659 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 660 cp->cpu_id, erratum); 661 } 662 663 static void 664 workaround_applied(uint_t erratum) 665 { 666 if (erratum > 1000000) 667 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 668 erratum); 669 else 670 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 671 erratum); 672 } 673 674 static void 675 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 676 { 677 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 678 cp->cpu_id, rw, msr, error); 679 } 680 681 /* 682 * Determine the number of nodes in a Hammer / Greyhound / Griffin family 683 * system. 684 */ 685 static uint_t 686 opteron_get_nnodes(void) 687 { 688 static uint_t nnodes = 0; 689 690 if (nnodes == 0) { 691 #ifdef DEBUG 692 uint_t family; 693 694 /* 695 * This routine uses a PCI config space based mechanism 696 * for retrieving the number of nodes in the system. 697 * Device 24, function 0, offset 0x60 as used here is not 698 * AMD processor architectural, and may not work on processor 699 * families other than those listed below. 700 * 701 * Callers of this routine must ensure that we're running on 702 * a processor which supports this mechanism. 703 * The assertion below is meant to catch calls on unsupported 704 * processors. 705 */ 706 family = cpuid_getfamily(CPU); 707 ASSERT(family == 0xf || family == 0x10 || family == 0x11); 708 #endif /* DEBUG */ 709 710 /* 711 * Obtain the number of nodes in the system from 712 * bits [6:4] of the Node ID register on node 0. 713 * 714 * The actual node count is NodeID[6:4] + 1 715 * 716 * The Node ID register is accessed via function 0, 717 * offset 0x60. Node 0 is device 24. 718 */ 719 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 720 } 721 return (nnodes); 722 } 723 724 uint_t 725 do_erratum_298(struct cpu *cpu) 726 { 727 static int osvwrc = -3; 728 extern int osvw_opteron_erratum(cpu_t *, uint_t); 729 730 /* 731 * L2 Eviction May Occur During Processor Operation To Set 732 * Accessed or Dirty Bit. 733 */ 734 if (osvwrc == -3) { 735 osvwrc = osvw_opteron_erratum(cpu, 298); 736 } else { 737 /* osvw return codes should be consistent for all cpus */ 738 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 739 } 740 741 switch (osvwrc) { 742 case 0: /* erratum is not present: do nothing */ 743 break; 744 case 1: /* erratum is present: BIOS workaround applied */ 745 /* 746 * check if workaround is actually in place and issue warning 747 * if not. 748 */ 749 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 750 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 751 #if defined(OPTERON_ERRATUM_298) 752 opteron_erratum_298++; 753 #else 754 workaround_warning(cpu, 298); 755 return (1); 756 #endif 757 } 758 break; 759 case -1: /* cannot determine via osvw: check cpuid */ 760 if ((cpuid_opteron_erratum(cpu, 298) > 0) && 761 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 762 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 763 #if defined(OPTERON_ERRATUM_298) 764 opteron_erratum_298++; 765 #else 766 workaround_warning(cpu, 298); 767 return (1); 768 #endif 769 } 770 break; 771 } 772 return (0); 773 } 774 775 uint_t 776 workaround_errata(struct cpu *cpu) 777 { 778 uint_t missing = 0; 779 780 ASSERT(cpu == CPU); 781 782 /*LINTED*/ 783 if (cpuid_opteron_erratum(cpu, 88) > 0) { 784 /* 785 * SWAPGS May Fail To Read Correct GS Base 786 */ 787 #if defined(OPTERON_ERRATUM_88) 788 /* 789 * The workaround is an mfence in the relevant assembler code 790 */ 791 opteron_erratum_88++; 792 #else 793 workaround_warning(cpu, 88); 794 missing++; 795 #endif 796 } 797 798 if (cpuid_opteron_erratum(cpu, 91) > 0) { 799 /* 800 * Software Prefetches May Report A Page Fault 801 */ 802 #if defined(OPTERON_ERRATUM_91) 803 /* 804 * fix is in trap.c 805 */ 806 opteron_erratum_91++; 807 #else 808 workaround_warning(cpu, 91); 809 missing++; 810 #endif 811 } 812 813 if (cpuid_opteron_erratum(cpu, 93) > 0) { 814 /* 815 * RSM Auto-Halt Restart Returns to Incorrect RIP 816 */ 817 #if defined(OPTERON_ERRATUM_93) 818 /* 819 * fix is in trap.c 820 */ 821 opteron_erratum_93++; 822 #else 823 workaround_warning(cpu, 93); 824 missing++; 825 #endif 826 } 827 828 /*LINTED*/ 829 if (cpuid_opteron_erratum(cpu, 95) > 0) { 830 /* 831 * RET Instruction May Return to Incorrect EIP 832 */ 833 #if defined(OPTERON_ERRATUM_95) 834 #if defined(_LP64) 835 /* 836 * Workaround this by ensuring that 32-bit user code and 837 * 64-bit kernel code never occupy the same address 838 * range mod 4G. 839 */ 840 if (_userlimit32 > 0xc0000000ul) 841 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 842 843 /*LINTED*/ 844 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 845 opteron_erratum_95++; 846 #endif /* _LP64 */ 847 #else 848 workaround_warning(cpu, 95); 849 missing++; 850 #endif 851 } 852 853 if (cpuid_opteron_erratum(cpu, 100) > 0) { 854 /* 855 * Compatibility Mode Branches Transfer to Illegal Address 856 */ 857 #if defined(OPTERON_ERRATUM_100) 858 /* 859 * fix is in trap.c 860 */ 861 opteron_erratum_100++; 862 #else 863 workaround_warning(cpu, 100); 864 missing++; 865 #endif 866 } 867 868 /*LINTED*/ 869 if (cpuid_opteron_erratum(cpu, 108) > 0) { 870 /* 871 * CPUID Instruction May Return Incorrect Model Number In 872 * Some Processors 873 */ 874 #if defined(OPTERON_ERRATUM_108) 875 /* 876 * (Our cpuid-handling code corrects the model number on 877 * those processors) 878 */ 879 #else 880 workaround_warning(cpu, 108); 881 missing++; 882 #endif 883 } 884 885 /*LINTED*/ 886 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 887 /* 888 * Certain Reverse REP MOVS May Produce Unpredictable Behavior 889 */ 890 #if defined(OPTERON_ERRATUM_109) 891 /* 892 * The "workaround" is to print a warning to upgrade the BIOS 893 */ 894 uint64_t value; 895 const uint_t msr = MSR_AMD_PATCHLEVEL; 896 int err; 897 898 if ((err = checked_rdmsr(msr, &value)) != 0) { 899 msr_warning(cpu, "rd", msr, err); 900 workaround_warning(cpu, 109); 901 missing++; 902 } 903 if (value == 0) 904 opteron_erratum_109++; 905 #else 906 workaround_warning(cpu, 109); 907 missing++; 908 #endif 909 /*CONSTANTCONDITION*/ 910 } while (0); 911 912 /*LINTED*/ 913 if (cpuid_opteron_erratum(cpu, 121) > 0) { 914 /* 915 * Sequential Execution Across Non_Canonical Boundary Caused 916 * Processor Hang 917 */ 918 #if defined(OPTERON_ERRATUM_121) 919 #if defined(_LP64) 920 /* 921 * Erratum 121 is only present in long (64 bit) mode. 922 * Workaround is to include the page immediately before the 923 * va hole to eliminate the possibility of system hangs due to 924 * sequential execution across the va hole boundary. 925 */ 926 if (opteron_erratum_121) 927 opteron_erratum_121++; 928 else { 929 if (hole_start) { 930 hole_start -= PAGESIZE; 931 } else { 932 /* 933 * hole_start not yet initialized by 934 * mmu_init. Initialize hole_start 935 * with value to be subtracted. 936 */ 937 hole_start = PAGESIZE; 938 } 939 opteron_erratum_121++; 940 } 941 #endif /* _LP64 */ 942 #else 943 workaround_warning(cpu, 121); 944 missing++; 945 #endif 946 } 947 948 /*LINTED*/ 949 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 950 /* 951 * TLB Flush Filter May Cause Coherency Problem in 952 * Multiprocessor Systems 953 */ 954 #if defined(OPTERON_ERRATUM_122) 955 uint64_t value; 956 const uint_t msr = MSR_AMD_HWCR; 957 int error; 958 959 /* 960 * Erratum 122 is only present in MP configurations (multi-core 961 * or multi-processor). 962 */ 963 #if defined(__xpv) 964 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 965 break; 966 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 967 break; 968 #else 969 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 970 cpuid_get_ncpu_per_chip(cpu) == 1) 971 break; 972 #endif 973 /* disable TLB Flush Filter */ 974 975 if ((error = checked_rdmsr(msr, &value)) != 0) { 976 msr_warning(cpu, "rd", msr, error); 977 workaround_warning(cpu, 122); 978 missing++; 979 } else { 980 value |= (uint64_t)AMD_HWCR_FFDIS; 981 if ((error = checked_wrmsr(msr, value)) != 0) { 982 msr_warning(cpu, "wr", msr, error); 983 workaround_warning(cpu, 122); 984 missing++; 985 } 986 } 987 opteron_erratum_122++; 988 #else 989 workaround_warning(cpu, 122); 990 missing++; 991 #endif 992 /*CONSTANTCONDITION*/ 993 } while (0); 994 995 /*LINTED*/ 996 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 997 /* 998 * Bypassed Reads May Cause Data Corruption of System Hang in 999 * Dual Core Processors 1000 */ 1001 #if defined(OPTERON_ERRATUM_123) 1002 uint64_t value; 1003 const uint_t msr = MSR_AMD_PATCHLEVEL; 1004 int err; 1005 1006 /* 1007 * Erratum 123 applies only to multi-core cpus. 1008 */ 1009 if (cpuid_get_ncpu_per_chip(cpu) < 2) 1010 break; 1011 #if defined(__xpv) 1012 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1013 break; 1014 #endif 1015 /* 1016 * The "workaround" is to print a warning to upgrade the BIOS 1017 */ 1018 if ((err = checked_rdmsr(msr, &value)) != 0) { 1019 msr_warning(cpu, "rd", msr, err); 1020 workaround_warning(cpu, 123); 1021 missing++; 1022 } 1023 if (value == 0) 1024 opteron_erratum_123++; 1025 #else 1026 workaround_warning(cpu, 123); 1027 missing++; 1028 1029 #endif 1030 /*CONSTANTCONDITION*/ 1031 } while (0); 1032 1033 /*LINTED*/ 1034 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 1035 /* 1036 * Multiprocessor Systems with Four or More Cores May Deadlock 1037 * Waiting for a Probe Response 1038 */ 1039 #if defined(OPTERON_ERRATUM_131) 1040 uint64_t nbcfg; 1041 const uint_t msr = MSR_AMD_NB_CFG; 1042 const uint64_t wabits = 1043 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1044 int error; 1045 1046 /* 1047 * Erratum 131 applies to any system with four or more cores. 1048 */ 1049 if (opteron_erratum_131) 1050 break; 1051 #if defined(__xpv) 1052 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1053 break; 1054 if (xpv_nr_phys_cpus() < 4) 1055 break; 1056 #else 1057 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1058 break; 1059 #endif 1060 /* 1061 * Print a warning if neither of the workarounds for 1062 * erratum 131 is present. 1063 */ 1064 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1065 msr_warning(cpu, "rd", msr, error); 1066 workaround_warning(cpu, 131); 1067 missing++; 1068 } else if ((nbcfg & wabits) == 0) { 1069 opteron_erratum_131++; 1070 } else { 1071 /* cannot have both workarounds set */ 1072 ASSERT((nbcfg & wabits) != wabits); 1073 } 1074 #else 1075 workaround_warning(cpu, 131); 1076 missing++; 1077 #endif 1078 /*CONSTANTCONDITION*/ 1079 } while (0); 1080 1081 /* 1082 * This isn't really an erratum, but for convenience the 1083 * detection/workaround code lives here and in cpuid_opteron_erratum. 1084 */ 1085 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1086 #if defined(OPTERON_WORKAROUND_6336786) 1087 /* 1088 * Disable C1-Clock ramping on multi-core/multi-processor 1089 * K8 platforms to guard against TSC drift. 1090 */ 1091 if (opteron_workaround_6336786) { 1092 opteron_workaround_6336786++; 1093 #if defined(__xpv) 1094 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1095 xpv_nr_phys_cpus() > 1) || 1096 opteron_workaround_6336786_UP) { 1097 /* 1098 * XXPV Hmm. We can't walk the Northbridges on 1099 * the hypervisor; so just complain and drive 1100 * on. This probably needs to be fixed in 1101 * the hypervisor itself. 1102 */ 1103 opteron_workaround_6336786++; 1104 workaround_warning(cpu, 6336786); 1105 #else /* __xpv */ 1106 } else if ((opteron_get_nnodes() * 1107 cpuid_get_ncpu_per_chip(cpu) > 1) || 1108 opteron_workaround_6336786_UP) { 1109 1110 uint_t node, nnodes; 1111 uint8_t data; 1112 1113 nnodes = opteron_get_nnodes(); 1114 for (node = 0; node < nnodes; node++) { 1115 /* 1116 * Clear PMM7[1:0] (function 3, offset 0x87) 1117 * Northbridge device is the node id + 24. 1118 */ 1119 data = pci_getb_func(0, node + 24, 3, 0x87); 1120 data &= 0xFC; 1121 pci_putb_func(0, node + 24, 3, 0x87, data); 1122 } 1123 opteron_workaround_6336786++; 1124 #endif /* __xpv */ 1125 } 1126 #else 1127 workaround_warning(cpu, 6336786); 1128 missing++; 1129 #endif 1130 } 1131 1132 /*LINTED*/ 1133 /* 1134 * Mutex primitives don't work as expected. 1135 */ 1136 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1137 #if defined(OPTERON_WORKAROUND_6323525) 1138 /* 1139 * This problem only occurs with 2 or more cores. If bit in 1140 * MSR_AMD_BU_CFG set, then not applicable. The workaround 1141 * is to patch the semaphone routines with the lfence 1142 * instruction to provide necessary load memory barrier with 1143 * possible subsequent read-modify-write ops. 1144 * 1145 * It is too early in boot to call the patch routine so 1146 * set erratum variable to be done in startup_end(). 1147 */ 1148 if (opteron_workaround_6323525) { 1149 opteron_workaround_6323525++; 1150 #if defined(__xpv) 1151 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) { 1152 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1153 /* 1154 * XXPV Use dom0_msr here when extended 1155 * operations are supported? 1156 */ 1157 if (xpv_nr_phys_cpus() > 1) 1158 opteron_workaround_6323525++; 1159 } else { 1160 /* 1161 * We have no way to tell how many physical 1162 * cpus there are, or even if this processor 1163 * has the problem, so enable the workaround 1164 * unconditionally (at some performance cost). 1165 */ 1166 opteron_workaround_6323525++; 1167 } 1168 #else /* __xpv */ 1169 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) && 1170 ((opteron_get_nnodes() * 1171 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1172 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1173 opteron_workaround_6323525++; 1174 #endif /* __xpv */ 1175 } 1176 #else 1177 workaround_warning(cpu, 6323525); 1178 missing++; 1179 #endif 1180 } 1181 1182 missing += do_erratum_298(cpu); 1183 1184 if (cpuid_opteron_erratum(cpu, 721) > 0) { 1185 #if defined(OPTERON_ERRATUM_721) 1186 wrmsr(MSR_AMD_DE_CFG, rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721); 1187 opteron_erratum_721++; 1188 #else 1189 workaround_warning(cpu, 721); 1190 missing++; 1191 #endif 1192 } 1193 1194 #ifdef __xpv 1195 return (0); 1196 #else 1197 return (missing); 1198 #endif 1199 } 1200 1201 void 1202 workaround_errata_end() 1203 { 1204 #if defined(OPTERON_ERRATUM_88) 1205 if (opteron_erratum_88) 1206 workaround_applied(88); 1207 #endif 1208 #if defined(OPTERON_ERRATUM_91) 1209 if (opteron_erratum_91) 1210 workaround_applied(91); 1211 #endif 1212 #if defined(OPTERON_ERRATUM_93) 1213 if (opteron_erratum_93) 1214 workaround_applied(93); 1215 #endif 1216 #if defined(OPTERON_ERRATUM_95) 1217 if (opteron_erratum_95) 1218 workaround_applied(95); 1219 #endif 1220 #if defined(OPTERON_ERRATUM_100) 1221 if (opteron_erratum_100) 1222 workaround_applied(100); 1223 #endif 1224 #if defined(OPTERON_ERRATUM_108) 1225 if (opteron_erratum_108) 1226 workaround_applied(108); 1227 #endif 1228 #if defined(OPTERON_ERRATUM_109) 1229 if (opteron_erratum_109) { 1230 cmn_err(CE_WARN, 1231 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1232 " processor\nerratum 109 was not detected; updating your" 1233 " system's BIOS to a version\ncontaining this" 1234 " microcode patch is HIGHLY recommended or erroneous" 1235 " system\noperation may occur.\n"); 1236 } 1237 #endif 1238 #if defined(OPTERON_ERRATUM_121) 1239 if (opteron_erratum_121) 1240 workaround_applied(121); 1241 #endif 1242 #if defined(OPTERON_ERRATUM_122) 1243 if (opteron_erratum_122) 1244 workaround_applied(122); 1245 #endif 1246 #if defined(OPTERON_ERRATUM_123) 1247 if (opteron_erratum_123) { 1248 cmn_err(CE_WARN, 1249 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1250 " processor\nerratum 123 was not detected; updating your" 1251 " system's BIOS to a version\ncontaining this" 1252 " microcode patch is HIGHLY recommended or erroneous" 1253 " system\noperation may occur.\n"); 1254 } 1255 #endif 1256 #if defined(OPTERON_ERRATUM_131) 1257 if (opteron_erratum_131) { 1258 cmn_err(CE_WARN, 1259 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1260 " processor\nerratum 131 was not detected; updating your" 1261 " system's BIOS to a version\ncontaining this" 1262 " microcode patch is HIGHLY recommended or erroneous" 1263 " system\noperation may occur.\n"); 1264 } 1265 #endif 1266 #if defined(OPTERON_WORKAROUND_6336786) 1267 if (opteron_workaround_6336786) 1268 workaround_applied(6336786); 1269 #endif 1270 #if defined(OPTERON_WORKAROUND_6323525) 1271 if (opteron_workaround_6323525) 1272 workaround_applied(6323525); 1273 #endif 1274 #if defined(OPTERON_ERRATUM_298) 1275 if (opteron_erratum_298) { 1276 cmn_err(CE_WARN, 1277 "BIOS microcode patch for AMD 64/Opteron(tm)" 1278 " processor\nerratum 298 was not detected; updating your" 1279 " system's BIOS to a version\ncontaining this" 1280 " microcode patch is HIGHLY recommended or erroneous" 1281 " system\noperation may occur.\n"); 1282 } 1283 #endif 1284 #if defined(OPTERON_ERRATUM_721) 1285 if (opteron_erratum_721) 1286 workaround_applied(721); 1287 #endif 1288 } 1289 1290 /* 1291 * The procset_slave and procset_master are used to synchronize 1292 * between the control CPU and the target CPU when starting CPUs. 1293 */ 1294 static cpuset_t procset_slave, procset_master; 1295 1296 static void 1297 mp_startup_wait(cpuset_t *sp, processorid_t cpuid) 1298 { 1299 cpuset_t tempset; 1300 1301 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid); 1302 tempset = *(volatile cpuset_t *)sp) { 1303 SMT_PAUSE(); 1304 } 1305 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid); 1306 } 1307 1308 static void 1309 mp_startup_signal(cpuset_t *sp, processorid_t cpuid) 1310 { 1311 cpuset_t tempset; 1312 1313 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid); 1314 for (tempset = *sp; CPU_IN_SET(tempset, cpuid); 1315 tempset = *(volatile cpuset_t *)sp) { 1316 SMT_PAUSE(); 1317 } 1318 } 1319 1320 int 1321 mp_start_cpu_common(cpu_t *cp, boolean_t boot) 1322 { 1323 _NOTE(ARGUNUSED(boot)); 1324 1325 void *ctx; 1326 int delays; 1327 int error = 0; 1328 cpuset_t tempset; 1329 processorid_t cpuid; 1330 #ifndef __xpv 1331 extern void cpupm_init(cpu_t *); 1332 #endif 1333 1334 ASSERT(cp != NULL); 1335 cpuid = cp->cpu_id; 1336 ctx = mach_cpucontext_alloc(cp); 1337 if (ctx == NULL) { 1338 cmn_err(CE_WARN, 1339 "cpu%d: failed to allocate context", cp->cpu_id); 1340 return (EAGAIN); 1341 } 1342 error = mach_cpu_start(cp, ctx); 1343 if (error != 0) { 1344 cmn_err(CE_WARN, 1345 "cpu%d: failed to start, error %d", cp->cpu_id, error); 1346 mach_cpucontext_free(cp, ctx, error); 1347 return (error); 1348 } 1349 1350 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid); 1351 delays++) { 1352 if (delays == 500) { 1353 /* 1354 * After five seconds, things are probably looking 1355 * a bit bleak - explain the hang. 1356 */ 1357 cmn_err(CE_NOTE, "cpu%d: started, " 1358 "but not running in the kernel yet", cpuid); 1359 } else if (delays > 2000) { 1360 /* 1361 * We waited at least 20 seconds, bail .. 1362 */ 1363 error = ETIMEDOUT; 1364 cmn_err(CE_WARN, "cpu%d: timed out", cpuid); 1365 mach_cpucontext_free(cp, ctx, error); 1366 return (error); 1367 } 1368 1369 /* 1370 * wait at least 10ms, then check again.. 1371 */ 1372 delay(USEC_TO_TICK_ROUNDUP(10000)); 1373 tempset = *((volatile cpuset_t *)&procset_slave); 1374 } 1375 CPUSET_ATOMIC_DEL(procset_slave, cpuid); 1376 1377 mach_cpucontext_free(cp, ctx, 0); 1378 1379 #ifndef __xpv 1380 if (tsc_gethrtime_enable) 1381 tsc_sync_master(cpuid); 1382 #endif 1383 1384 if (dtrace_cpu_init != NULL) { 1385 (*dtrace_cpu_init)(cpuid); 1386 } 1387 1388 /* 1389 * During CPU DR operations, the cpu_lock is held by current 1390 * (the control) thread. We can't release the cpu_lock here 1391 * because that will break the CPU DR logic. 1392 * On the other hand, CPUPM and processor group initialization 1393 * routines need to access the cpu_lock. So we invoke those 1394 * routines here on behalf of mp_startup_common(). 1395 * 1396 * CPUPM and processor group initialization routines depend 1397 * on the cpuid probing results. Wait for mp_startup_common() 1398 * to signal that cpuid probing is done. 1399 */ 1400 mp_startup_wait(&procset_slave, cpuid); 1401 #ifndef __xpv 1402 cpupm_init(cp); 1403 #endif 1404 (void) pg_cpu_init(cp, B_FALSE); 1405 cpu_set_state(cp); 1406 mp_startup_signal(&procset_master, cpuid); 1407 1408 return (0); 1409 } 1410 1411 /* 1412 * Start a single cpu, assuming that the kernel context is available 1413 * to successfully start another cpu. 1414 * 1415 * (For example, real mode code is mapped into the right place 1416 * in memory and is ready to be run.) 1417 */ 1418 int 1419 start_cpu(processorid_t who) 1420 { 1421 cpu_t *cp; 1422 int error = 0; 1423 cpuset_t tempset; 1424 1425 ASSERT(who != 0); 1426 1427 /* 1428 * Check if there's at least a Mbyte of kmem available 1429 * before attempting to start the cpu. 1430 */ 1431 if (kmem_avail() < 1024 * 1024) { 1432 /* 1433 * Kick off a reap in case that helps us with 1434 * later attempts .. 1435 */ 1436 kmem_reap(); 1437 return (ENOMEM); 1438 } 1439 1440 /* 1441 * First configure cpu. 1442 */ 1443 cp = mp_cpu_configure_common(who, B_TRUE); 1444 ASSERT(cp != NULL); 1445 1446 /* 1447 * Then start cpu. 1448 */ 1449 error = mp_start_cpu_common(cp, B_TRUE); 1450 if (error != 0) { 1451 mp_cpu_unconfigure_common(cp, error); 1452 return (error); 1453 } 1454 1455 mutex_exit(&cpu_lock); 1456 tempset = cpu_ready_set; 1457 while (!CPU_IN_SET(tempset, who)) { 1458 drv_usecwait(1); 1459 tempset = *((volatile cpuset_t *)&cpu_ready_set); 1460 } 1461 mutex_enter(&cpu_lock); 1462 1463 return (0); 1464 } 1465 1466 void 1467 start_other_cpus(int cprboot) 1468 { 1469 _NOTE(ARGUNUSED(cprboot)); 1470 1471 uint_t who; 1472 uint_t bootcpuid = 0; 1473 1474 /* 1475 * Initialize our own cpu_info. 1476 */ 1477 init_cpu_info(CPU); 1478 1479 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 1480 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 1481 1482 /* 1483 * Initialize our syscall handlers 1484 */ 1485 init_cpu_syscall(CPU); 1486 1487 /* 1488 * Take the boot cpu out of the mp_cpus set because we know 1489 * it's already running. Add it to the cpu_ready_set for 1490 * precisely the same reason. 1491 */ 1492 CPUSET_DEL(mp_cpus, bootcpuid); 1493 CPUSET_ADD(cpu_ready_set, bootcpuid); 1494 1495 /* 1496 * skip the rest of this if 1497 * . only 1 cpu dectected and system isn't hotplug-capable 1498 * . not using MP 1499 */ 1500 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) || 1501 use_mp == 0) { 1502 if (use_mp == 0) 1503 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1504 goto done; 1505 } 1506 1507 /* 1508 * perform such initialization as is needed 1509 * to be able to take CPUs on- and off-line. 1510 */ 1511 cpu_pause_init(); 1512 1513 xc_init_cpu(CPU); /* initialize processor crosscalls */ 1514 1515 if (mach_cpucontext_init() != 0) 1516 goto done; 1517 1518 flushes_require_xcalls = 1; 1519 1520 /* 1521 * We lock our affinity to the master CPU to ensure that all slave CPUs 1522 * do their TSC syncs with the same CPU. 1523 */ 1524 affinity_set(CPU_CURRENT); 1525 1526 for (who = 0; who < NCPU; who++) { 1527 if (!CPU_IN_SET(mp_cpus, who)) 1528 continue; 1529 ASSERT(who != bootcpuid); 1530 1531 mutex_enter(&cpu_lock); 1532 if (start_cpu(who) != 0) 1533 CPUSET_DEL(mp_cpus, who); 1534 cpu_state_change_notify(who, CPU_SETUP); 1535 mutex_exit(&cpu_lock); 1536 } 1537 1538 /* Free the space allocated to hold the microcode file */ 1539 ucode_cleanup(); 1540 1541 affinity_clear(); 1542 1543 mach_cpucontext_fini(); 1544 1545 done: 1546 if (get_hwenv() == HW_NATIVE) 1547 workaround_errata_end(); 1548 cmi_post_mpstartup(); 1549 1550 if (use_mp && ncpus != boot_max_ncpus) { 1551 cmn_err(CE_NOTE, 1552 "System detected %d cpus, but " 1553 "only %d cpu(s) were enabled during boot.", 1554 boot_max_ncpus, ncpus); 1555 cmn_err(CE_NOTE, 1556 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1557 "See eeprom(1M)."); 1558 } 1559 } 1560 1561 int 1562 mp_cpu_configure(int cpuid) 1563 { 1564 cpu_t *cp; 1565 1566 if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1567 return (ENOTSUP); 1568 } 1569 1570 cp = cpu_get(cpuid); 1571 if (cp != NULL) { 1572 return (EALREADY); 1573 } 1574 1575 /* 1576 * Check if there's at least a Mbyte of kmem available 1577 * before attempting to start the cpu. 1578 */ 1579 if (kmem_avail() < 1024 * 1024) { 1580 /* 1581 * Kick off a reap in case that helps us with 1582 * later attempts .. 1583 */ 1584 kmem_reap(); 1585 return (ENOMEM); 1586 } 1587 1588 cp = mp_cpu_configure_common(cpuid, B_FALSE); 1589 ASSERT(cp != NULL && cpu_get(cpuid) == cp); 1590 1591 return (cp != NULL ? 0 : EAGAIN); 1592 } 1593 1594 int 1595 mp_cpu_unconfigure(int cpuid) 1596 { 1597 cpu_t *cp; 1598 1599 if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1600 return (ENOTSUP); 1601 } else if (cpuid < 0 || cpuid >= max_ncpus) { 1602 return (EINVAL); 1603 } 1604 1605 cp = cpu_get(cpuid); 1606 if (cp == NULL) { 1607 return (ENODEV); 1608 } 1609 mp_cpu_unconfigure_common(cp, 0); 1610 1611 return (0); 1612 } 1613 1614 /* 1615 * Startup function for 'other' CPUs (besides boot cpu). 1616 * Called from real_mode_start. 1617 * 1618 * WARNING: until CPU_READY is set, mp_startup_common and routines called by 1619 * mp_startup_common should not call routines (e.g. kmem_free) that could call 1620 * hat_unload which requires CPU_READY to be set. 1621 */ 1622 static void 1623 mp_startup_common(boolean_t boot) 1624 { 1625 cpu_t *cp = CPU; 1626 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; 1627 extern void cpu_event_init_cpu(cpu_t *); 1628 1629 /* 1630 * We need to get TSC on this proc synced (i.e., any delta 1631 * from cpu0 accounted for) as soon as we can, because many 1632 * many things use gethrtime/pc_gethrestime, including 1633 * interrupts, cmn_err, etc. 1634 */ 1635 1636 /* Let the control CPU continue into tsc_sync_master() */ 1637 mp_startup_signal(&procset_slave, cp->cpu_id); 1638 1639 #ifndef __xpv 1640 if (tsc_gethrtime_enable) 1641 tsc_sync_slave(); 1642 #endif 1643 1644 /* 1645 * Once this was done from assembly, but it's safer here; if 1646 * it blocks, we need to be able to swtch() to and from, and 1647 * since we get here by calling t_pc, we need to do that call 1648 * before swtch() overwrites it. 1649 */ 1650 (void) (*ap_mlsetup)(); 1651 1652 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES)); 1653 cpuid_pass1(cp, new_x86_featureset); 1654 1655 #ifndef __xpv 1656 /* 1657 * Program this cpu's PAT 1658 */ 1659 if (is_x86_feature(x86_featureset, X86FSET_PAT)) 1660 pat_sync(); 1661 #endif 1662 1663 /* 1664 * Set up TSC_AUX to contain the cpuid for this processor 1665 * for the rdtscp instruction. 1666 */ 1667 if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 1668 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1669 1670 /* 1671 * Initialize this CPU's syscall handlers 1672 */ 1673 init_cpu_syscall(cp); 1674 1675 /* 1676 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1677 * highest level at which a routine is permitted to block on 1678 * an adaptive mutex (allows for cpu poke interrupt in case 1679 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1680 * device interrupts that may end up in the hat layer issuing cross 1681 * calls before CPU_READY is set. 1682 */ 1683 splx(ipltospl(LOCK_LEVEL)); 1684 sti(); 1685 1686 /* 1687 * Do a sanity check to make sure this new CPU is a sane thing 1688 * to add to the collection of processors running this system. 1689 * 1690 * XXX Clearly this needs to get more sophisticated, if x86 1691 * systems start to get built out of heterogenous CPUs; as is 1692 * likely to happen once the number of processors in a configuration 1693 * gets large enough. 1694 */ 1695 if (compare_x86_featureset(x86_featureset, new_x86_featureset) == 1696 B_FALSE) { 1697 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id); 1698 print_x86_featureset(new_x86_featureset); 1699 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1700 } 1701 1702 /* 1703 * We do not support cpus with mixed monitor/mwait support if the 1704 * boot cpu supports monitor/mwait. 1705 */ 1706 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) != 1707 is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) 1708 panic("unsupported mixed cpu monitor/mwait support detected"); 1709 1710 /* 1711 * We could be more sophisticated here, and just mark the CPU 1712 * as "faulted" but at this point we'll opt for the easier 1713 * answer of dying horribly. Provided the boot cpu is ok, 1714 * the system can be recovered by booting with use_mp set to zero. 1715 */ 1716 if (workaround_errata(cp) != 0) 1717 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1718 1719 /* 1720 * We can touch cpu_flags here without acquiring the cpu_lock here 1721 * because the cpu_lock is held by the control CPU which is running 1722 * mp_start_cpu_common(). 1723 * Need to clear CPU_QUIESCED flag before calling any function which 1724 * may cause thread context switching, such as kmem_alloc() etc. 1725 * The idle thread checks for CPU_QUIESCED flag and loops for ever if 1726 * it's set. So the startup thread may have no chance to switch back 1727 * again if it's switched away with CPU_QUIESCED set. 1728 */ 1729 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED); 1730 1731 /* 1732 * Setup this processor for XSAVE. 1733 */ 1734 if (fp_save_mech == FP_XSAVE) { 1735 xsave_setup_msr(cp); 1736 } 1737 1738 cpuid_pass2(cp); 1739 cpuid_pass3(cp); 1740 (void) cpuid_pass4(cp); 1741 1742 /* 1743 * Correct cpu_idstr and cpu_brandstr on target CPU after 1744 * cpuid_pass1() is done. 1745 */ 1746 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN); 1747 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN); 1748 1749 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 1750 1751 post_startup_cpu_fixups(); 1752 1753 cpu_event_init_cpu(cp); 1754 1755 /* 1756 * Enable preemption here so that contention for any locks acquired 1757 * later in mp_startup_common may be preempted if the thread owning 1758 * those locks is continuously executing on other CPUs (for example, 1759 * this CPU must be preemptible to allow other CPUs to pause it during 1760 * their startup phases). It's safe to enable preemption here because 1761 * the CPU state is pretty-much fully constructed. 1762 */ 1763 curthread->t_preempt = 0; 1764 1765 /* The base spl should still be at LOCK LEVEL here */ 1766 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1767 set_base_spl(); /* Restore the spl to its proper value */ 1768 1769 pghw_physid_create(cp); 1770 /* 1771 * Delegate initialization tasks, which need to access the cpu_lock, 1772 * to mp_start_cpu_common() because we can't acquire the cpu_lock here 1773 * during CPU DR operations. 1774 */ 1775 mp_startup_signal(&procset_slave, cp->cpu_id); 1776 mp_startup_wait(&procset_master, cp->cpu_id); 1777 pg_cmt_cpu_startup(cp); 1778 1779 if (boot) { 1780 mutex_enter(&cpu_lock); 1781 cp->cpu_flags &= ~CPU_OFFLINE; 1782 cpu_enable_intr(cp); 1783 cpu_add_active(cp); 1784 mutex_exit(&cpu_lock); 1785 } 1786 1787 /* Enable interrupts */ 1788 (void) spl0(); 1789 1790 /* 1791 * Fill out cpu_ucode_info. Update microcode if necessary. 1792 */ 1793 ucode_check(cp); 1794 1795 #ifndef __xpv 1796 { 1797 /* 1798 * Set up the CPU module for this CPU. This can't be done 1799 * before this CPU is made CPU_READY, because we may (in 1800 * heterogeneous systems) need to go load another CPU module. 1801 * The act of attempting to load a module may trigger a 1802 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1803 */ 1804 cmi_hdl_t hdl; 1805 1806 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1807 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1808 if (is_x86_feature(x86_featureset, X86FSET_MCA)) 1809 cmi_mca_init(hdl); 1810 cp->cpu_m.mcpu_cmi_hdl = hdl; 1811 } 1812 } 1813 #endif /* __xpv */ 1814 1815 if (boothowto & RB_DEBUG) 1816 kdi_cpu_init(); 1817 1818 /* 1819 * Setting the bit in cpu_ready_set must be the last operation in 1820 * processor initialization; the boot CPU will continue to boot once 1821 * it sees this bit set for all active CPUs. 1822 */ 1823 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1824 1825 (void) mach_cpu_create_device_node(cp, NULL); 1826 1827 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1828 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1829 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n", 1830 cp->cpu_id); 1831 1832 /* 1833 * Now we are done with the startup thread, so free it up. 1834 */ 1835 thread_exit(); 1836 panic("mp_startup: cannot return"); 1837 /*NOTREACHED*/ 1838 } 1839 1840 /* 1841 * Startup function for 'other' CPUs at boot time (besides boot cpu). 1842 */ 1843 static void 1844 mp_startup_boot(void) 1845 { 1846 mp_startup_common(B_TRUE); 1847 } 1848 1849 /* 1850 * Startup function for hotplug CPUs at runtime. 1851 */ 1852 void 1853 mp_startup_hotplug(void) 1854 { 1855 mp_startup_common(B_FALSE); 1856 } 1857 1858 /* 1859 * Start CPU on user request. 1860 */ 1861 /* ARGSUSED */ 1862 int 1863 mp_cpu_start(struct cpu *cp) 1864 { 1865 ASSERT(MUTEX_HELD(&cpu_lock)); 1866 return (0); 1867 } 1868 1869 /* 1870 * Stop CPU on user request. 1871 */ 1872 int 1873 mp_cpu_stop(struct cpu *cp) 1874 { 1875 extern int cbe_psm_timer_mode; 1876 ASSERT(MUTEX_HELD(&cpu_lock)); 1877 1878 #ifdef __xpv 1879 /* 1880 * We can't offline vcpu0. 1881 */ 1882 if (cp->cpu_id == 0) 1883 return (EBUSY); 1884 #endif 1885 1886 /* 1887 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1888 * can't stop it. (This is true only for machines with no TSC.) 1889 */ 1890 1891 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1892 return (EBUSY); 1893 1894 return (0); 1895 } 1896 1897 /* 1898 * Take the specified CPU out of participation in interrupts. 1899 */ 1900 int 1901 cpu_disable_intr(struct cpu *cp) 1902 { 1903 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1904 return (EBUSY); 1905 1906 cp->cpu_flags &= ~CPU_ENABLE; 1907 return (0); 1908 } 1909 1910 /* 1911 * Allow the specified CPU to participate in interrupts. 1912 */ 1913 void 1914 cpu_enable_intr(struct cpu *cp) 1915 { 1916 ASSERT(MUTEX_HELD(&cpu_lock)); 1917 cp->cpu_flags |= CPU_ENABLE; 1918 psm_enable_intr(cp->cpu_id); 1919 } 1920 1921 void 1922 mp_cpu_faulted_enter(struct cpu *cp) 1923 { 1924 #ifdef __xpv 1925 _NOTE(ARGUNUSED(cp)); 1926 #else 1927 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 1928 1929 if (hdl != NULL) { 1930 cmi_hdl_hold(hdl); 1931 } else { 1932 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1933 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1934 } 1935 if (hdl != NULL) { 1936 cmi_faulted_enter(hdl); 1937 cmi_hdl_rele(hdl); 1938 } 1939 #endif 1940 } 1941 1942 void 1943 mp_cpu_faulted_exit(struct cpu *cp) 1944 { 1945 #ifdef __xpv 1946 _NOTE(ARGUNUSED(cp)); 1947 #else 1948 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 1949 1950 if (hdl != NULL) { 1951 cmi_hdl_hold(hdl); 1952 } else { 1953 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1954 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1955 } 1956 if (hdl != NULL) { 1957 cmi_faulted_exit(hdl); 1958 cmi_hdl_rele(hdl); 1959 } 1960 #endif 1961 } 1962 1963 /* 1964 * The following two routines are used as context operators on threads belonging 1965 * to processes with a private LDT (see sysi86). Due to the rarity of such 1966 * processes, these routines are currently written for best code readability and 1967 * organization rather than speed. We could avoid checking x86_featureset at 1968 * every context switch by installing different context ops, depending on 1969 * x86_featureset, at LDT creation time -- one for each combination of fast 1970 * syscall features. 1971 */ 1972 1973 /*ARGSUSED*/ 1974 void 1975 cpu_fast_syscall_disable(void *arg) 1976 { 1977 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1978 is_x86_feature(x86_featureset, X86FSET_SEP)) 1979 cpu_sep_disable(); 1980 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1981 is_x86_feature(x86_featureset, X86FSET_ASYSC)) 1982 cpu_asysc_disable(); 1983 } 1984 1985 /*ARGSUSED*/ 1986 void 1987 cpu_fast_syscall_enable(void *arg) 1988 { 1989 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1990 is_x86_feature(x86_featureset, X86FSET_SEP)) 1991 cpu_sep_enable(); 1992 if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1993 is_x86_feature(x86_featureset, X86FSET_ASYSC)) 1994 cpu_asysc_enable(); 1995 } 1996 1997 static void 1998 cpu_sep_enable(void) 1999 { 2000 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 2001 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2002 2003 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 2004 } 2005 2006 static void 2007 cpu_sep_disable(void) 2008 { 2009 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 2010 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2011 2012 /* 2013 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 2014 * the sysenter or sysexit instruction to trigger a #gp fault. 2015 */ 2016 wrmsr(MSR_INTC_SEP_CS, 0); 2017 } 2018 2019 static void 2020 cpu_asysc_enable(void) 2021 { 2022 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 2023 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2024 2025 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 2026 (uint64_t)(uintptr_t)AMD_EFER_SCE); 2027 } 2028 2029 static void 2030 cpu_asysc_disable(void) 2031 { 2032 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 2033 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 2034 2035 /* 2036 * Turn off the SCE (syscall enable) bit in the EFER register. Software 2037 * executing syscall or sysret with this bit off will incur a #ud trap. 2038 */ 2039 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 2040 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 2041 } 2042