1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/thread.h> 31 #include <sys/cpuvar.h> 32 #include <sys/t_lock.h> 33 #include <sys/param.h> 34 #include <sys/proc.h> 35 #include <sys/disp.h> 36 #include <sys/class.h> 37 #include <sys/cmn_err.h> 38 #include <sys/debug.h> 39 #include <sys/asm_linkage.h> 40 #include <sys/x_call.h> 41 #include <sys/systm.h> 42 #include <sys/var.h> 43 #include <sys/vtrace.h> 44 #include <vm/hat.h> 45 #include <vm/as.h> 46 #include <vm/seg_kmem.h> 47 #include <vm/seg_kp.h> 48 #include <sys/segments.h> 49 #include <sys/kmem.h> 50 #include <sys/stack.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/x86_archext.h> 53 #include <sys/machsystm.h> 54 #include <sys/traptrace.h> 55 #include <sys/clock.h> 56 #include <sys/cpc_impl.h> 57 #include <sys/pg.h> 58 #include <sys/cmt.h> 59 #include <sys/dtrace.h> 60 #include <sys/archsystm.h> 61 #include <sys/fp.h> 62 #include <sys/reboot.h> 63 #include <sys/kdi_machimpl.h> 64 #include <vm/hat_i86.h> 65 #include <sys/memnode.h> 66 #include <sys/pci_cfgspace.h> 67 #include <sys/mach_mmu.h> 68 #include <sys/sysmacros.h> 69 #if defined(__xpv) 70 #include <sys/hypervisor.h> 71 #endif 72 #include <sys/cpu_module.h> 73 74 struct cpu cpus[1]; /* CPU data */ 75 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 76 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 77 78 /* 79 * Useful for disabling MP bring-up on a MP capable system. 80 */ 81 int use_mp = 1; 82 83 /* 84 * to be set by a PSM to indicate what cpus 85 * are sitting around on the system. 86 */ 87 cpuset_t mp_cpus; 88 89 /* 90 * This variable is used by the hat layer to decide whether or not 91 * critical sections are needed to prevent race conditions. For sun4m, 92 * this variable is set once enough MP initialization has been done in 93 * order to allow cross calls. 94 */ 95 int flushes_require_xcalls; 96 97 cpuset_t cpu_ready_set; /* initialized in startup() */ 98 99 static void mp_startup(void); 100 101 static void cpu_sep_enable(void); 102 static void cpu_sep_disable(void); 103 static void cpu_asysc_enable(void); 104 static void cpu_asysc_disable(void); 105 106 /* 107 * Init CPU info - get CPU type info for processor_info system call. 108 */ 109 void 110 init_cpu_info(struct cpu *cp) 111 { 112 processor_info_t *pi = &cp->cpu_type_info; 113 char buf[CPU_IDSTRLEN]; 114 115 /* 116 * Get clock-frequency property for the CPU. 117 */ 118 pi->pi_clock = cpu_freq; 119 120 /* 121 * Current frequency in Hz. 122 */ 123 cp->cpu_curr_clock = cpu_freq_hz; 124 125 /* 126 * Supported frequencies. 127 */ 128 cpu_set_supp_freqs(cp, NULL); 129 130 (void) strcpy(pi->pi_processor_type, "i386"); 131 if (fpu_exists) 132 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 133 134 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 135 136 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 137 (void) strcpy(cp->cpu_idstr, buf); 138 139 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 140 141 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 142 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 143 (void) strcpy(cp->cpu_brandstr, buf); 144 145 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 146 } 147 148 /* 149 * Configure syscall support on this CPU. 150 */ 151 /*ARGSUSED*/ 152 void 153 init_cpu_syscall(struct cpu *cp) 154 { 155 kpreempt_disable(); 156 157 #if defined(__amd64) 158 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 159 160 #if !defined(__lint) 161 /* 162 * The syscall instruction imposes a certain ordering on 163 * segment selectors, so we double-check that ordering 164 * here. 165 */ 166 ASSERT(KDS_SEL == KCS_SEL + 8); 167 ASSERT(UDS_SEL == U32CS_SEL + 8); 168 ASSERT(UCS_SEL == U32CS_SEL + 16); 169 #endif 170 /* 171 * Turn syscall/sysret extensions on. 172 */ 173 cpu_asysc_enable(); 174 175 /* 176 * Program the magic registers .. 177 */ 178 wrmsr(MSR_AMD_STAR, 179 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 180 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 181 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 182 183 /* 184 * This list of flags is masked off the incoming 185 * %rfl when we enter the kernel. 186 */ 187 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 188 } 189 #endif 190 191 /* 192 * On 32-bit kernels, we use sysenter/sysexit because it's too 193 * hard to use syscall/sysret, and it is more portable anyway. 194 * 195 * On 64-bit kernels on Nocona machines, the 32-bit syscall 196 * variant isn't available to 32-bit applications, but sysenter is. 197 */ 198 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 199 200 #if !defined(__lint) 201 /* 202 * The sysenter instruction imposes a certain ordering on 203 * segment selectors, so we double-check that ordering 204 * here. See "sysenter" in Intel document 245471-012, "IA-32 205 * Intel Architecture Software Developer's Manual Volume 2: 206 * Instruction Set Reference" 207 */ 208 ASSERT(KDS_SEL == KCS_SEL + 8); 209 210 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 211 ASSERT32(UDS_SEL == UCS_SEL + 8); 212 213 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 214 ASSERT64(UDS_SEL == U32CS_SEL + 8); 215 #endif 216 217 cpu_sep_enable(); 218 219 /* 220 * resume() sets this value to the base of the threads stack 221 * via a context handler. 222 */ 223 wrmsr(MSR_INTC_SEP_ESP, 0); 224 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 225 } 226 227 kpreempt_enable(); 228 } 229 230 /* 231 * Multiprocessor initialization. 232 * 233 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 234 * startup and idle threads for the specified CPU. 235 */ 236 struct cpu * 237 mp_startup_init(int cpun) 238 { 239 struct cpu *cp; 240 kthread_id_t tp; 241 caddr_t sp; 242 proc_t *procp; 243 #if !defined(__xpv) 244 extern int idle_cpu_prefer_mwait; 245 #endif 246 extern void idle(); 247 248 #ifdef TRAPTRACE 249 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 250 #endif 251 252 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 253 254 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 255 #if !defined(__xpv) 256 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) 257 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 258 #endif 259 260 procp = curthread->t_procp; 261 262 mutex_enter(&cpu_lock); 263 /* 264 * Initialize the dispatcher first. 265 */ 266 disp_cpu_init(cp); 267 mutex_exit(&cpu_lock); 268 269 cpu_vm_data_init(cp); 270 271 /* 272 * Allocate and initialize the startup thread for this CPU. 273 * Interrupt and process switch stacks get allocated later 274 * when the CPU starts running. 275 */ 276 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 277 TS_STOPPED, maxclsyspri); 278 279 /* 280 * Set state to TS_ONPROC since this thread will start running 281 * as soon as the CPU comes online. 282 * 283 * All the other fields of the thread structure are setup by 284 * thread_create(). 285 */ 286 THREAD_ONPROC(tp, cp); 287 tp->t_preempt = 1; 288 tp->t_bound_cpu = cp; 289 tp->t_affinitycnt = 1; 290 tp->t_cpu = cp; 291 tp->t_disp_queue = cp->cpu_disp; 292 293 /* 294 * Setup thread to start in mp_startup. 295 */ 296 sp = tp->t_stk; 297 tp->t_pc = (uintptr_t)mp_startup; 298 tp->t_sp = (uintptr_t)(sp - MINFRAME); 299 #if defined(__amd64) 300 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 301 #endif 302 303 cp->cpu_id = cpun; 304 cp->cpu_self = cp; 305 cp->cpu_thread = tp; 306 cp->cpu_lwp = NULL; 307 cp->cpu_dispthread = tp; 308 cp->cpu_dispatch_pri = DISP_PRIO(tp); 309 310 /* 311 * cpu_base_spl must be set explicitly here to prevent any blocking 312 * operations in mp_startup from causing the spl of the cpu to drop 313 * to 0 (allowing device interrupts before we're ready) in resume(). 314 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 315 * As an extra bit of security on DEBUG kernels, this is enforced with 316 * an assertion in mp_startup() -- before cpu_base_spl is set to its 317 * proper value. 318 */ 319 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 320 321 /* 322 * Now, initialize per-CPU idle thread for this CPU. 323 */ 324 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 325 326 cp->cpu_idle_thread = tp; 327 328 tp->t_preempt = 1; 329 tp->t_bound_cpu = cp; 330 tp->t_affinitycnt = 1; 331 tp->t_cpu = cp; 332 tp->t_disp_queue = cp->cpu_disp; 333 334 /* 335 * Bootstrap the CPU's PG data 336 */ 337 pg_cpu_bootstrap(cp); 338 339 /* 340 * Perform CPC initialization on the new CPU. 341 */ 342 kcpc_hw_init(cp); 343 344 /* 345 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 346 * for each CPU. 347 */ 348 setup_vaddr_for_ppcopy(cp); 349 350 /* 351 * Allocate page for new GDT and initialize from current GDT. 352 */ 353 #if !defined(__lint) 354 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 355 #endif 356 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 357 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 358 359 #if defined(__i386) 360 /* 361 * setup kernel %gs. 362 */ 363 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 364 SEL_KPL, 0, 1); 365 #endif 366 367 /* 368 * If we have more than one node, each cpu gets a copy of IDT 369 * local to its node. If this is a Pentium box, we use cpu 0's 370 * IDT. cpu 0's IDT has been made read-only to workaround the 371 * cmpxchgl register bug 372 */ 373 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 374 #if !defined(__lint) 375 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 376 #endif 377 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 378 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 379 } else { 380 cp->cpu_idt = CPU->cpu_idt; 381 } 382 383 /* 384 * Get interrupt priority data from cpu 0. 385 */ 386 cp->cpu_pri_data = CPU->cpu_pri_data; 387 388 /* 389 * alloc space for cpuid info 390 */ 391 cpuid_alloc_space(cp); 392 393 #if !defined(__xpv) 394 /* 395 * alloc space for ucode_info 396 */ 397 ucode_alloc_space(cp); 398 #endif 399 400 hat_cpu_online(cp); 401 402 #ifdef TRAPTRACE 403 /* 404 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 405 */ 406 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 407 ttc->ttc_next = ttc->ttc_first; 408 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 409 #endif 410 /* 411 * Record that we have another CPU. 412 */ 413 mutex_enter(&cpu_lock); 414 /* 415 * Initialize the interrupt threads for this CPU 416 */ 417 cpu_intr_alloc(cp, NINTR_THREADS); 418 /* 419 * Add CPU to list of available CPUs. It'll be on the active list 420 * after mp_startup(). 421 */ 422 cpu_add_unit(cp); 423 mutex_exit(&cpu_lock); 424 425 return (cp); 426 } 427 428 /* 429 * Undo what was done in mp_startup_init 430 */ 431 static void 432 mp_startup_fini(struct cpu *cp, int error) 433 { 434 mutex_enter(&cpu_lock); 435 436 /* 437 * Remove the CPU from the list of available CPUs. 438 */ 439 cpu_del_unit(cp->cpu_id); 440 441 if (error == ETIMEDOUT) { 442 /* 443 * The cpu was started, but never *seemed* to run any 444 * code in the kernel; it's probably off spinning in its 445 * own private world, though with potential references to 446 * our kmem-allocated IDTs and GDTs (for example). 447 * 448 * Worse still, it may actually wake up some time later, 449 * so rather than guess what it might or might not do, we 450 * leave the fundamental data structures intact. 451 */ 452 cp->cpu_flags = 0; 453 mutex_exit(&cpu_lock); 454 return; 455 } 456 457 /* 458 * At this point, the only threads bound to this CPU should 459 * special per-cpu threads: it's idle thread, it's pause threads, 460 * and it's interrupt threads. Clean these up. 461 */ 462 cpu_destroy_bound_threads(cp); 463 cp->cpu_idle_thread = NULL; 464 465 /* 466 * Free the interrupt stack. 467 */ 468 segkp_release(segkp, 469 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 470 471 mutex_exit(&cpu_lock); 472 473 #ifdef TRAPTRACE 474 /* 475 * Discard the trap trace buffer 476 */ 477 { 478 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 479 480 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 481 ttc->ttc_first = NULL; 482 } 483 #endif 484 485 hat_cpu_offline(cp); 486 487 cpuid_free_space(cp); 488 489 #if !defined(__xpv) 490 ucode_free_space(cp); 491 #endif 492 493 if (cp->cpu_idt != CPU->cpu_idt) 494 kmem_free(cp->cpu_idt, PAGESIZE); 495 cp->cpu_idt = NULL; 496 497 kmem_free(cp->cpu_gdt, PAGESIZE); 498 cp->cpu_gdt = NULL; 499 500 teardown_vaddr_for_ppcopy(cp); 501 502 kcpc_hw_fini(cp); 503 504 cp->cpu_dispthread = NULL; 505 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 506 507 cpu_vm_data_destroy(cp); 508 509 mutex_enter(&cpu_lock); 510 disp_cpu_fini(cp); 511 mutex_exit(&cpu_lock); 512 513 #if !defined(__xpv) 514 if (cp->cpu_m.mcpu_mwait != NULL) 515 cpuid_mwait_free(cp); 516 #endif 517 kmem_free(cp, sizeof (*cp)); 518 } 519 520 /* 521 * Apply workarounds for known errata, and warn about those that are absent. 522 * 523 * System vendors occasionally create configurations which contain different 524 * revisions of the CPUs that are almost but not exactly the same. At the 525 * time of writing, this meant that their clock rates were the same, their 526 * feature sets were the same, but the required workaround were -not- 527 * necessarily the same. So, this routine is invoked on -every- CPU soon 528 * after starting to make sure that the resulting system contains the most 529 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 530 * system. 531 * 532 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 533 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 534 * to acknowledging their readiness to the master, so this routine will 535 * never be executed by multiple CPUs in parallel, thus making updates to 536 * global data safe. 537 * 538 * These workarounds are based on Rev 3.57 of the Revision Guide for 539 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 540 */ 541 542 #if defined(OPTERON_ERRATUM_88) 543 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 544 #endif 545 546 #if defined(OPTERON_ERRATUM_91) 547 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 548 #endif 549 550 #if defined(OPTERON_ERRATUM_93) 551 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 552 #endif 553 554 #if defined(OPTERON_ERRATUM_95) 555 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 556 #endif 557 558 #if defined(OPTERON_ERRATUM_100) 559 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 560 #endif 561 562 #if defined(OPTERON_ERRATUM_108) 563 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 564 #endif 565 566 #if defined(OPTERON_ERRATUM_109) 567 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 568 #endif 569 570 #if defined(OPTERON_ERRATUM_121) 571 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 572 #endif 573 574 #if defined(OPTERON_ERRATUM_122) 575 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 576 #endif 577 578 #if defined(OPTERON_ERRATUM_123) 579 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 580 #endif 581 582 #if defined(OPTERON_ERRATUM_131) 583 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 584 #endif 585 586 #if defined(OPTERON_WORKAROUND_6336786) 587 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 588 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 589 #endif 590 591 #if defined(OPTERON_WORKAROUND_6323525) 592 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 593 #endif 594 595 #if defined(OPTERON_ERRATUM_298) 596 int opteron_erratum_298; 597 #endif 598 599 static void 600 workaround_warning(cpu_t *cp, uint_t erratum) 601 { 602 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 603 cp->cpu_id, erratum); 604 } 605 606 static void 607 workaround_applied(uint_t erratum) 608 { 609 if (erratum > 1000000) 610 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 611 erratum); 612 else 613 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 614 erratum); 615 } 616 617 static void 618 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 619 { 620 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 621 cp->cpu_id, rw, msr, error); 622 } 623 624 /* 625 * Determine the number of nodes in an Opteron / Greyhound family system. 626 */ 627 static uint_t 628 opteron_get_nnodes(void) 629 { 630 static uint_t nnodes = 0; 631 632 #ifdef DEBUG 633 uint_t family; 634 635 family = cpuid_getfamily(CPU); 636 ASSERT(family == 0xf || family == 0x10); 637 #endif /* DEBUG */ 638 639 if (nnodes == 0) { 640 /* 641 * Obtain the number of nodes in the system from 642 * bits [6:4] of the Node ID register on node 0. 643 * 644 * The actual node count is NodeID[6:4] + 1 645 * 646 * The Node ID register is accessed via function 0, 647 * offset 0x60. Node 0 is device 24. 648 */ 649 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 650 } 651 return (nnodes); 652 } 653 654 #if defined(__xpv) 655 656 /* 657 * On dom0, we can determine the number of physical cpus on the machine. 658 * This number is important when figuring out what workarounds are 659 * appropriate, so compute it now. 660 */ 661 uint_t 662 xen_get_nphyscpus(void) 663 { 664 static uint_t nphyscpus = 0; 665 666 ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 667 668 if (nphyscpus == 0) { 669 xen_sysctl_t op; 670 xen_sysctl_physinfo_t *pi = &op.u.physinfo; 671 672 op.cmd = XEN_SYSCTL_physinfo; 673 op.interface_version = XEN_SYSCTL_INTERFACE_VERSION; 674 if (HYPERVISOR_sysctl(&op) == 0) 675 nphyscpus = pi->threads_per_core * 676 pi->cores_per_socket * pi->sockets_per_node * 677 pi->nr_nodes; 678 } 679 return (nphyscpus); 680 } 681 #endif 682 683 uint_t 684 do_erratum_298(struct cpu *cpu) 685 { 686 static int osvwrc = -3; 687 extern int osvw_opteron_erratum(cpu_t *, uint_t); 688 689 /* 690 * L2 Eviction May Occur During Processor Operation To Set 691 * Accessed or Dirty Bit. 692 */ 693 if (osvwrc == -3) { 694 osvwrc = osvw_opteron_erratum(cpu, 298); 695 } else { 696 /* osvw return codes should be consistent for all cpus */ 697 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 698 } 699 700 switch (osvwrc) { 701 case 0: /* erratum is not present: do nothing */ 702 break; 703 case 1: /* erratum is present: BIOS workaround applied */ 704 /* 705 * check if workaround is actually in place and issue warning 706 * if not. 707 */ 708 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 709 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 710 #if defined(OPTERON_ERRATUM_298) 711 opteron_erratum_298++; 712 #else 713 workaround_warning(cpu, 298); 714 return (1); 715 #endif 716 } 717 break; 718 case -1: /* cannot determine via osvw: check cpuid */ 719 if ((cpuid_opteron_erratum(cpu, 298) > 0) && 720 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 721 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 722 #if defined(OPTERON_ERRATUM_298) 723 opteron_erratum_298++; 724 #else 725 workaround_warning(cpu, 298); 726 return (1); 727 #endif 728 } 729 break; 730 } 731 return (0); 732 } 733 734 uint_t 735 workaround_errata(struct cpu *cpu) 736 { 737 uint_t missing = 0; 738 739 ASSERT(cpu == CPU); 740 741 /*LINTED*/ 742 if (cpuid_opteron_erratum(cpu, 88) > 0) { 743 /* 744 * SWAPGS May Fail To Read Correct GS Base 745 */ 746 #if defined(OPTERON_ERRATUM_88) 747 /* 748 * The workaround is an mfence in the relevant assembler code 749 */ 750 opteron_erratum_88++; 751 #else 752 workaround_warning(cpu, 88); 753 missing++; 754 #endif 755 } 756 757 if (cpuid_opteron_erratum(cpu, 91) > 0) { 758 /* 759 * Software Prefetches May Report A Page Fault 760 */ 761 #if defined(OPTERON_ERRATUM_91) 762 /* 763 * fix is in trap.c 764 */ 765 opteron_erratum_91++; 766 #else 767 workaround_warning(cpu, 91); 768 missing++; 769 #endif 770 } 771 772 if (cpuid_opteron_erratum(cpu, 93) > 0) { 773 /* 774 * RSM Auto-Halt Restart Returns to Incorrect RIP 775 */ 776 #if defined(OPTERON_ERRATUM_93) 777 /* 778 * fix is in trap.c 779 */ 780 opteron_erratum_93++; 781 #else 782 workaround_warning(cpu, 93); 783 missing++; 784 #endif 785 } 786 787 /*LINTED*/ 788 if (cpuid_opteron_erratum(cpu, 95) > 0) { 789 /* 790 * RET Instruction May Return to Incorrect EIP 791 */ 792 #if defined(OPTERON_ERRATUM_95) 793 #if defined(_LP64) 794 /* 795 * Workaround this by ensuring that 32-bit user code and 796 * 64-bit kernel code never occupy the same address 797 * range mod 4G. 798 */ 799 if (_userlimit32 > 0xc0000000ul) 800 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 801 802 /*LINTED*/ 803 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 804 opteron_erratum_95++; 805 #endif /* _LP64 */ 806 #else 807 workaround_warning(cpu, 95); 808 missing++; 809 #endif 810 } 811 812 if (cpuid_opteron_erratum(cpu, 100) > 0) { 813 /* 814 * Compatibility Mode Branches Transfer to Illegal Address 815 */ 816 #if defined(OPTERON_ERRATUM_100) 817 /* 818 * fix is in trap.c 819 */ 820 opteron_erratum_100++; 821 #else 822 workaround_warning(cpu, 100); 823 missing++; 824 #endif 825 } 826 827 /*LINTED*/ 828 if (cpuid_opteron_erratum(cpu, 108) > 0) { 829 /* 830 * CPUID Instruction May Return Incorrect Model Number In 831 * Some Processors 832 */ 833 #if defined(OPTERON_ERRATUM_108) 834 /* 835 * (Our cpuid-handling code corrects the model number on 836 * those processors) 837 */ 838 #else 839 workaround_warning(cpu, 108); 840 missing++; 841 #endif 842 } 843 844 /*LINTED*/ 845 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 846 /* 847 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 848 */ 849 #if defined(OPTERON_ERRATUM_109) 850 /* 851 * The "workaround" is to print a warning to upgrade the BIOS 852 */ 853 uint64_t value; 854 const uint_t msr = MSR_AMD_PATCHLEVEL; 855 int err; 856 857 if ((err = checked_rdmsr(msr, &value)) != 0) { 858 msr_warning(cpu, "rd", msr, err); 859 workaround_warning(cpu, 109); 860 missing++; 861 } 862 if (value == 0) 863 opteron_erratum_109++; 864 #else 865 workaround_warning(cpu, 109); 866 missing++; 867 #endif 868 /*CONSTANTCONDITION*/ 869 } while (0); 870 871 /*LINTED*/ 872 if (cpuid_opteron_erratum(cpu, 121) > 0) { 873 /* 874 * Sequential Execution Across Non_Canonical Boundary Caused 875 * Processor Hang 876 */ 877 #if defined(OPTERON_ERRATUM_121) 878 #if defined(_LP64) 879 /* 880 * Erratum 121 is only present in long (64 bit) mode. 881 * Workaround is to include the page immediately before the 882 * va hole to eliminate the possibility of system hangs due to 883 * sequential execution across the va hole boundary. 884 */ 885 if (opteron_erratum_121) 886 opteron_erratum_121++; 887 else { 888 if (hole_start) { 889 hole_start -= PAGESIZE; 890 } else { 891 /* 892 * hole_start not yet initialized by 893 * mmu_init. Initialize hole_start 894 * with value to be subtracted. 895 */ 896 hole_start = PAGESIZE; 897 } 898 opteron_erratum_121++; 899 } 900 #endif /* _LP64 */ 901 #else 902 workaround_warning(cpu, 121); 903 missing++; 904 #endif 905 } 906 907 /*LINTED*/ 908 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 909 /* 910 * TLB Flush Filter May Cause Coherency Problem in 911 * Multiprocessor Systems 912 */ 913 #if defined(OPTERON_ERRATUM_122) 914 uint64_t value; 915 const uint_t msr = MSR_AMD_HWCR; 916 int error; 917 918 /* 919 * Erratum 122 is only present in MP configurations (multi-core 920 * or multi-processor). 921 */ 922 #if defined(__xpv) 923 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 924 break; 925 if (!opteron_erratum_122 && xen_get_nphyscpus() == 1) 926 break; 927 #else 928 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 929 cpuid_get_ncpu_per_chip(cpu) == 1) 930 break; 931 #endif 932 /* disable TLB Flush Filter */ 933 934 if ((error = checked_rdmsr(msr, &value)) != 0) { 935 msr_warning(cpu, "rd", msr, error); 936 workaround_warning(cpu, 122); 937 missing++; 938 } else { 939 value |= (uint64_t)AMD_HWCR_FFDIS; 940 if ((error = checked_wrmsr(msr, value)) != 0) { 941 msr_warning(cpu, "wr", msr, error); 942 workaround_warning(cpu, 122); 943 missing++; 944 } 945 } 946 opteron_erratum_122++; 947 #else 948 workaround_warning(cpu, 122); 949 missing++; 950 #endif 951 /*CONSTANTCONDITION*/ 952 } while (0); 953 954 /*LINTED*/ 955 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 956 /* 957 * Bypassed Reads May Cause Data Corruption of System Hang in 958 * Dual Core Processors 959 */ 960 #if defined(OPTERON_ERRATUM_123) 961 uint64_t value; 962 const uint_t msr = MSR_AMD_PATCHLEVEL; 963 int err; 964 965 /* 966 * Erratum 123 applies only to multi-core cpus. 967 */ 968 if (cpuid_get_ncpu_per_chip(cpu) < 2) 969 break; 970 #if defined(__xpv) 971 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 972 break; 973 #endif 974 /* 975 * The "workaround" is to print a warning to upgrade the BIOS 976 */ 977 if ((err = checked_rdmsr(msr, &value)) != 0) { 978 msr_warning(cpu, "rd", msr, err); 979 workaround_warning(cpu, 123); 980 missing++; 981 } 982 if (value == 0) 983 opteron_erratum_123++; 984 #else 985 workaround_warning(cpu, 123); 986 missing++; 987 988 #endif 989 /*CONSTANTCONDITION*/ 990 } while (0); 991 992 /*LINTED*/ 993 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 994 /* 995 * Multiprocessor Systems with Four or More Cores May Deadlock 996 * Waiting for a Probe Response 997 */ 998 #if defined(OPTERON_ERRATUM_131) 999 uint64_t nbcfg; 1000 const uint_t msr = MSR_AMD_NB_CFG; 1001 const uint64_t wabits = 1002 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1003 int error; 1004 1005 /* 1006 * Erratum 131 applies to any system with four or more cores. 1007 */ 1008 if (opteron_erratum_131) 1009 break; 1010 #if defined(__xpv) 1011 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1012 break; 1013 if (xen_get_nphyscpus() < 4) 1014 break; 1015 #else 1016 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1017 break; 1018 #endif 1019 /* 1020 * Print a warning if neither of the workarounds for 1021 * erratum 131 is present. 1022 */ 1023 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1024 msr_warning(cpu, "rd", msr, error); 1025 workaround_warning(cpu, 131); 1026 missing++; 1027 } else if ((nbcfg & wabits) == 0) { 1028 opteron_erratum_131++; 1029 } else { 1030 /* cannot have both workarounds set */ 1031 ASSERT((nbcfg & wabits) != wabits); 1032 } 1033 #else 1034 workaround_warning(cpu, 131); 1035 missing++; 1036 #endif 1037 /*CONSTANTCONDITION*/ 1038 } while (0); 1039 1040 /* 1041 * This isn't really an erratum, but for convenience the 1042 * detection/workaround code lives here and in cpuid_opteron_erratum. 1043 */ 1044 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1045 #if defined(OPTERON_WORKAROUND_6336786) 1046 /* 1047 * Disable C1-Clock ramping on multi-core/multi-processor 1048 * K8 platforms to guard against TSC drift. 1049 */ 1050 if (opteron_workaround_6336786) { 1051 opteron_workaround_6336786++; 1052 #if defined(__xpv) 1053 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1054 xen_get_nphyscpus() > 1) || 1055 opteron_workaround_6336786_UP) { 1056 /* 1057 * XXPV Hmm. We can't walk the Northbridges on 1058 * the hypervisor; so just complain and drive 1059 * on. This probably needs to be fixed in 1060 * the hypervisor itself. 1061 */ 1062 opteron_workaround_6336786++; 1063 workaround_warning(cpu, 6336786); 1064 #else /* __xpv */ 1065 } else if ((opteron_get_nnodes() * 1066 cpuid_get_ncpu_per_chip(cpu) > 1) || 1067 opteron_workaround_6336786_UP) { 1068 1069 uint_t node, nnodes; 1070 uint8_t data; 1071 1072 nnodes = opteron_get_nnodes(); 1073 for (node = 0; node < nnodes; node++) { 1074 /* 1075 * Clear PMM7[1:0] (function 3, offset 0x87) 1076 * Northbridge device is the node id + 24. 1077 */ 1078 data = pci_getb_func(0, node + 24, 3, 0x87); 1079 data &= 0xFC; 1080 pci_putb_func(0, node + 24, 3, 0x87, data); 1081 } 1082 opteron_workaround_6336786++; 1083 #endif /* __xpv */ 1084 } 1085 #else 1086 workaround_warning(cpu, 6336786); 1087 missing++; 1088 #endif 1089 } 1090 1091 /*LINTED*/ 1092 /* 1093 * Mutex primitives don't work as expected. 1094 */ 1095 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1096 #if defined(OPTERON_WORKAROUND_6323525) 1097 /* 1098 * This problem only occurs with 2 or more cores. If bit in 1099 * MSR_AMD_BU_CFG set, then not applicable. The workaround 1100 * is to patch the semaphone routines with the lfence 1101 * instruction to provide necessary load memory barrier with 1102 * possible subsequent read-modify-write ops. 1103 * 1104 * It is too early in boot to call the patch routine so 1105 * set erratum variable to be done in startup_end(). 1106 */ 1107 if (opteron_workaround_6323525) { 1108 opteron_workaround_6323525++; 1109 #if defined(__xpv) 1110 } else if (x86_feature & X86_SSE2) { 1111 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1112 /* 1113 * XXPV Use dom0_msr here when extended 1114 * operations are supported? 1115 */ 1116 if (xen_get_nphyscpus() > 1) 1117 opteron_workaround_6323525++; 1118 } else { 1119 /* 1120 * We have no way to tell how many physical 1121 * cpus there are, or even if this processor 1122 * has the problem, so enable the workaround 1123 * unconditionally (at some performance cost). 1124 */ 1125 opteron_workaround_6323525++; 1126 } 1127 #else /* __xpv */ 1128 } else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * 1129 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1130 if ((xrdmsr(MSR_AMD_BU_CFG) & 0x02) == 0) 1131 opteron_workaround_6323525++; 1132 #endif /* __xpv */ 1133 } 1134 #else 1135 workaround_warning(cpu, 6323525); 1136 missing++; 1137 #endif 1138 } 1139 1140 missing += do_erratum_298(cpu); 1141 1142 #ifdef __xpv 1143 return (0); 1144 #else 1145 return (missing); 1146 #endif 1147 } 1148 1149 void 1150 workaround_errata_end() 1151 { 1152 #if defined(OPTERON_ERRATUM_88) 1153 if (opteron_erratum_88) 1154 workaround_applied(88); 1155 #endif 1156 #if defined(OPTERON_ERRATUM_91) 1157 if (opteron_erratum_91) 1158 workaround_applied(91); 1159 #endif 1160 #if defined(OPTERON_ERRATUM_93) 1161 if (opteron_erratum_93) 1162 workaround_applied(93); 1163 #endif 1164 #if defined(OPTERON_ERRATUM_95) 1165 if (opteron_erratum_95) 1166 workaround_applied(95); 1167 #endif 1168 #if defined(OPTERON_ERRATUM_100) 1169 if (opteron_erratum_100) 1170 workaround_applied(100); 1171 #endif 1172 #if defined(OPTERON_ERRATUM_108) 1173 if (opteron_erratum_108) 1174 workaround_applied(108); 1175 #endif 1176 #if defined(OPTERON_ERRATUM_109) 1177 if (opteron_erratum_109) { 1178 cmn_err(CE_WARN, 1179 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1180 " processor\nerratum 109 was not detected; updating your" 1181 " system's BIOS to a version\ncontaining this" 1182 " microcode patch is HIGHLY recommended or erroneous" 1183 " system\noperation may occur.\n"); 1184 } 1185 #endif 1186 #if defined(OPTERON_ERRATUM_121) 1187 if (opteron_erratum_121) 1188 workaround_applied(121); 1189 #endif 1190 #if defined(OPTERON_ERRATUM_122) 1191 if (opteron_erratum_122) 1192 workaround_applied(122); 1193 #endif 1194 #if defined(OPTERON_ERRATUM_123) 1195 if (opteron_erratum_123) { 1196 cmn_err(CE_WARN, 1197 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1198 " processor\nerratum 123 was not detected; updating your" 1199 " system's BIOS to a version\ncontaining this" 1200 " microcode patch is HIGHLY recommended or erroneous" 1201 " system\noperation may occur.\n"); 1202 } 1203 #endif 1204 #if defined(OPTERON_ERRATUM_131) 1205 if (opteron_erratum_131) { 1206 cmn_err(CE_WARN, 1207 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1208 " processor\nerratum 131 was not detected; updating your" 1209 " system's BIOS to a version\ncontaining this" 1210 " microcode patch is HIGHLY recommended or erroneous" 1211 " system\noperation may occur.\n"); 1212 } 1213 #endif 1214 #if defined(OPTERON_WORKAROUND_6336786) 1215 if (opteron_workaround_6336786) 1216 workaround_applied(6336786); 1217 #endif 1218 #if defined(OPTERON_WORKAROUND_6323525) 1219 if (opteron_workaround_6323525) 1220 workaround_applied(6323525); 1221 #endif 1222 #if defined(OPTERON_ERRATUM_298) 1223 if (opteron_erratum_298) { 1224 cmn_err(CE_WARN, 1225 "BIOS microcode patch for AMD 64/Opteron(tm)" 1226 " processor\nerratum 298 was not detected; updating your" 1227 " system's BIOS to a version\ncontaining this" 1228 " microcode patch is HIGHLY recommended or erroneous" 1229 " system\noperation may occur.\n"); 1230 } 1231 #endif 1232 } 1233 1234 static cpuset_t procset; 1235 1236 /* 1237 * Start a single cpu, assuming that the kernel context is available 1238 * to successfully start another cpu. 1239 * 1240 * (For example, real mode code is mapped into the right place 1241 * in memory and is ready to be run.) 1242 */ 1243 int 1244 start_cpu(processorid_t who) 1245 { 1246 void *ctx; 1247 cpu_t *cp; 1248 int delays; 1249 int error = 0; 1250 1251 ASSERT(who != 0); 1252 1253 /* 1254 * Check if there's at least a Mbyte of kmem available 1255 * before attempting to start the cpu. 1256 */ 1257 if (kmem_avail() < 1024 * 1024) { 1258 /* 1259 * Kick off a reap in case that helps us with 1260 * later attempts .. 1261 */ 1262 kmem_reap(); 1263 return (ENOMEM); 1264 } 1265 1266 cp = mp_startup_init(who); 1267 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1268 (error = mach_cpu_start(cp, ctx)) != 0) { 1269 1270 /* 1271 * Something went wrong before we even started it 1272 */ 1273 if (ctx) 1274 cmn_err(CE_WARN, 1275 "cpu%d: failed to start error %d", 1276 cp->cpu_id, error); 1277 else 1278 cmn_err(CE_WARN, 1279 "cpu%d: failed to allocate context", cp->cpu_id); 1280 1281 if (ctx) 1282 mach_cpucontext_free(cp, ctx, error); 1283 else 1284 error = EAGAIN; /* hmm. */ 1285 mp_startup_fini(cp, error); 1286 return (error); 1287 } 1288 1289 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1290 if (delays == 500) { 1291 /* 1292 * After five seconds, things are probably looking 1293 * a bit bleak - explain the hang. 1294 */ 1295 cmn_err(CE_NOTE, "cpu%d: started, " 1296 "but not running in the kernel yet", who); 1297 } else if (delays > 2000) { 1298 /* 1299 * We waited at least 20 seconds, bail .. 1300 */ 1301 error = ETIMEDOUT; 1302 cmn_err(CE_WARN, "cpu%d: timed out", who); 1303 mach_cpucontext_free(cp, ctx, error); 1304 mp_startup_fini(cp, error); 1305 return (error); 1306 } 1307 1308 /* 1309 * wait at least 10ms, then check again.. 1310 */ 1311 delay(USEC_TO_TICK_ROUNDUP(10000)); 1312 } 1313 1314 mach_cpucontext_free(cp, ctx, 0); 1315 1316 #ifndef __xpv 1317 if (tsc_gethrtime_enable) 1318 tsc_sync_master(who); 1319 #endif 1320 1321 if (dtrace_cpu_init != NULL) { 1322 /* 1323 * DTrace CPU initialization expects cpu_lock to be held. 1324 */ 1325 mutex_enter(&cpu_lock); 1326 (*dtrace_cpu_init)(who); 1327 mutex_exit(&cpu_lock); 1328 } 1329 1330 while (!CPU_IN_SET(cpu_ready_set, who)) 1331 delay(1); 1332 1333 return (0); 1334 } 1335 1336 1337 /*ARGSUSED*/ 1338 void 1339 start_other_cpus(int cprboot) 1340 { 1341 uint_t who; 1342 uint_t skipped = 0; 1343 uint_t bootcpuid = 0; 1344 1345 /* 1346 * Initialize our own cpu_info. 1347 */ 1348 init_cpu_info(CPU); 1349 1350 /* 1351 * Initialize our syscall handlers 1352 */ 1353 init_cpu_syscall(CPU); 1354 1355 /* 1356 * Take the boot cpu out of the mp_cpus set because we know 1357 * it's already running. Add it to the cpu_ready_set for 1358 * precisely the same reason. 1359 */ 1360 CPUSET_DEL(mp_cpus, bootcpuid); 1361 CPUSET_ADD(cpu_ready_set, bootcpuid); 1362 1363 /* 1364 * if only 1 cpu or not using MP, skip the rest of this 1365 */ 1366 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1367 if (use_mp == 0) 1368 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1369 goto done; 1370 } 1371 1372 /* 1373 * perform such initialization as is needed 1374 * to be able to take CPUs on- and off-line. 1375 */ 1376 cpu_pause_init(); 1377 1378 xc_init(); /* initialize processor crosscalls */ 1379 1380 if (mach_cpucontext_init() != 0) 1381 goto done; 1382 1383 flushes_require_xcalls = 1; 1384 1385 /* 1386 * We lock our affinity to the master CPU to ensure that all slave CPUs 1387 * do their TSC syncs with the same CPU. 1388 */ 1389 affinity_set(CPU_CURRENT); 1390 1391 for (who = 0; who < NCPU; who++) { 1392 1393 if (!CPU_IN_SET(mp_cpus, who)) 1394 continue; 1395 ASSERT(who != bootcpuid); 1396 if (ncpus >= max_ncpus) { 1397 skipped = who; 1398 continue; 1399 } 1400 if (start_cpu(who) != 0) 1401 CPUSET_DEL(mp_cpus, who); 1402 } 1403 1404 #if !defined(__xpv) 1405 /* Free the space allocated to hold the microcode file */ 1406 ucode_free(); 1407 #endif 1408 1409 affinity_clear(); 1410 1411 if (skipped) { 1412 cmn_err(CE_NOTE, 1413 "System detected %d cpus, but " 1414 "only %d cpu(s) were enabled during boot.", 1415 skipped + 1, ncpus); 1416 cmn_err(CE_NOTE, 1417 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1418 "See eeprom(1M)."); 1419 } 1420 1421 done: 1422 workaround_errata_end(); 1423 mach_cpucontext_fini(); 1424 1425 cmi_post_mpstartup(); 1426 } 1427 1428 /* 1429 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1430 */ 1431 /*ARGSUSED*/ 1432 int 1433 mp_cpu_configure(int cpuid) 1434 { 1435 return (ENOTSUP); /* not supported */ 1436 } 1437 1438 /*ARGSUSED*/ 1439 int 1440 mp_cpu_unconfigure(int cpuid) 1441 { 1442 return (ENOTSUP); /* not supported */ 1443 } 1444 1445 /* 1446 * Startup function for 'other' CPUs (besides boot cpu). 1447 * Called from real_mode_start. 1448 * 1449 * WARNING: until CPU_READY is set, mp_startup and routines called by 1450 * mp_startup should not call routines (e.g. kmem_free) that could call 1451 * hat_unload which requires CPU_READY to be set. 1452 */ 1453 void 1454 mp_startup(void) 1455 { 1456 struct cpu *cp = CPU; 1457 uint_t new_x86_feature; 1458 1459 /* 1460 * We need to get TSC on this proc synced (i.e., any delta 1461 * from cpu0 accounted for) as soon as we can, because many 1462 * many things use gethrtime/pc_gethrestime, including 1463 * interrupts, cmn_err, etc. 1464 */ 1465 1466 /* Let cpu0 continue into tsc_sync_master() */ 1467 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1468 1469 #ifndef __xpv 1470 if (tsc_gethrtime_enable) 1471 tsc_sync_slave(); 1472 #endif 1473 1474 /* 1475 * Once this was done from assembly, but it's safer here; if 1476 * it blocks, we need to be able to swtch() to and from, and 1477 * since we get here by calling t_pc, we need to do that call 1478 * before swtch() overwrites it. 1479 */ 1480 (void) (*ap_mlsetup)(); 1481 1482 new_x86_feature = cpuid_pass1(cp); 1483 1484 #ifndef __xpv 1485 /* 1486 * Program this cpu's PAT 1487 */ 1488 if (x86_feature & X86_PAT) 1489 pat_sync(); 1490 #endif 1491 1492 /* 1493 * Set up TSC_AUX to contain the cpuid for this processor 1494 * for the rdtscp instruction. 1495 */ 1496 if (x86_feature & X86_TSCP) 1497 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1498 1499 /* 1500 * Initialize this CPU's syscall handlers 1501 */ 1502 init_cpu_syscall(cp); 1503 1504 /* 1505 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1506 * highest level at which a routine is permitted to block on 1507 * an adaptive mutex (allows for cpu poke interrupt in case 1508 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1509 * device interrupts that may end up in the hat layer issuing cross 1510 * calls before CPU_READY is set. 1511 */ 1512 splx(ipltospl(LOCK_LEVEL)); 1513 sti(); 1514 1515 /* 1516 * Do a sanity check to make sure this new CPU is a sane thing 1517 * to add to the collection of processors running this system. 1518 * 1519 * XXX Clearly this needs to get more sophisticated, if x86 1520 * systems start to get built out of heterogenous CPUs; as is 1521 * likely to happen once the number of processors in a configuration 1522 * gets large enough. 1523 */ 1524 if ((x86_feature & new_x86_feature) != x86_feature) { 1525 cmn_err(CE_CONT, "?cpu%d: %b\n", 1526 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1527 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1528 } 1529 1530 /* 1531 * We do not support cpus with mixed monitor/mwait support if the 1532 * boot cpu supports monitor/mwait. 1533 */ 1534 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1535 panic("unsupported mixed cpu monitor/mwait support detected"); 1536 1537 /* 1538 * We could be more sophisticated here, and just mark the CPU 1539 * as "faulted" but at this point we'll opt for the easier 1540 * answer of dieing horribly. Provided the boot cpu is ok, 1541 * the system can be recovered by booting with use_mp set to zero. 1542 */ 1543 if (workaround_errata(cp) != 0) 1544 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1545 1546 cpuid_pass2(cp); 1547 cpuid_pass3(cp); 1548 (void) cpuid_pass4(cp); 1549 1550 init_cpu_info(cp); 1551 1552 mutex_enter(&cpu_lock); 1553 /* 1554 * Processor group initialization for this CPU is dependent on the 1555 * cpuid probing, which must be done in the context of the current 1556 * CPU. 1557 */ 1558 pghw_physid_create(cp); 1559 pg_cpu_init(cp); 1560 pg_cmt_cpu_startup(cp); 1561 1562 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 1563 1564 if (dtrace_cpu_init != NULL) { 1565 (*dtrace_cpu_init)(cp->cpu_id); 1566 } 1567 1568 #if !defined(__xpv) 1569 /* 1570 * Fill out cpu_ucode_info. Update microcode if necessary. 1571 */ 1572 ucode_check(cp); 1573 #endif 1574 1575 mutex_exit(&cpu_lock); 1576 1577 /* 1578 * Enable preemption here so that contention for any locks acquired 1579 * later in mp_startup may be preempted if the thread owning those 1580 * locks is continously executing on other CPUs (for example, this 1581 * CPU must be preemptible to allow other CPUs to pause it during their 1582 * startup phases). It's safe to enable preemption here because the 1583 * CPU state is pretty-much fully constructed. 1584 */ 1585 curthread->t_preempt = 0; 1586 1587 /* The base spl should still be at LOCK LEVEL here */ 1588 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1589 set_base_spl(); /* Restore the spl to its proper value */ 1590 1591 /* Enable interrupts */ 1592 (void) spl0(); 1593 mutex_enter(&cpu_lock); 1594 cpu_enable_intr(cp); 1595 cpu_add_active(cp); 1596 mutex_exit(&cpu_lock); 1597 1598 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1599 1600 #ifndef __xpv 1601 { 1602 /* 1603 * Set up the CPU module for this CPU. This can't be done 1604 * before this CPU is made CPU_READY, because we may (in 1605 * heterogeneous systems) need to go load another CPU module. 1606 * The act of attempting to load a module may trigger a 1607 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1608 */ 1609 cmi_hdl_t hdl; 1610 1611 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1612 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1613 if (x86_feature & X86_MCA) 1614 cmi_mca_init(hdl); 1615 } 1616 } 1617 #endif /* __xpv */ 1618 1619 if (boothowto & RB_DEBUG) 1620 kdi_cpu_init(); 1621 1622 /* 1623 * Setting the bit in cpu_ready_set must be the last operation in 1624 * processor initialization; the boot CPU will continue to boot once 1625 * it sees this bit set for all active CPUs. 1626 */ 1627 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1628 1629 /* 1630 * Because mp_startup() gets fired off after init() starts, we 1631 * can't use the '?' trick to do 'boot -v' printing - so we 1632 * always direct the 'cpu .. online' messages to the log. 1633 */ 1634 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1635 cp->cpu_id); 1636 1637 /* 1638 * Now we are done with the startup thread, so free it up. 1639 */ 1640 thread_exit(); 1641 panic("mp_startup: cannot return"); 1642 /*NOTREACHED*/ 1643 } 1644 1645 1646 /* 1647 * Start CPU on user request. 1648 */ 1649 /* ARGSUSED */ 1650 int 1651 mp_cpu_start(struct cpu *cp) 1652 { 1653 ASSERT(MUTEX_HELD(&cpu_lock)); 1654 return (0); 1655 } 1656 1657 /* 1658 * Stop CPU on user request. 1659 */ 1660 /* ARGSUSED */ 1661 int 1662 mp_cpu_stop(struct cpu *cp) 1663 { 1664 extern int cbe_psm_timer_mode; 1665 ASSERT(MUTEX_HELD(&cpu_lock)); 1666 1667 #ifdef __xpv 1668 /* 1669 * We can't offline vcpu0. 1670 */ 1671 if (cp->cpu_id == 0) 1672 return (EBUSY); 1673 #endif 1674 1675 /* 1676 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1677 * can't stop it. (This is true only for machines with no TSC.) 1678 */ 1679 1680 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1681 return (EBUSY); 1682 1683 return (0); 1684 } 1685 1686 /* 1687 * Take the specified CPU out of participation in interrupts. 1688 */ 1689 int 1690 cpu_disable_intr(struct cpu *cp) 1691 { 1692 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1693 return (EBUSY); 1694 1695 cp->cpu_flags &= ~CPU_ENABLE; 1696 return (0); 1697 } 1698 1699 /* 1700 * Allow the specified CPU to participate in interrupts. 1701 */ 1702 void 1703 cpu_enable_intr(struct cpu *cp) 1704 { 1705 ASSERT(MUTEX_HELD(&cpu_lock)); 1706 cp->cpu_flags |= CPU_ENABLE; 1707 psm_enable_intr(cp->cpu_id); 1708 } 1709 1710 1711 /*ARGSUSED*/ 1712 void 1713 mp_cpu_faulted_enter(struct cpu *cp) 1714 { 1715 #ifndef __xpv 1716 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1717 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1718 1719 if (hdl != NULL) { 1720 cmi_faulted_enter(hdl); 1721 cmi_hdl_rele(hdl); 1722 } 1723 #endif 1724 } 1725 1726 /*ARGSUSED*/ 1727 void 1728 mp_cpu_faulted_exit(struct cpu *cp) 1729 { 1730 #ifndef __xpv 1731 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1732 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1733 1734 if (hdl != NULL) { 1735 cmi_faulted_exit(hdl); 1736 cmi_hdl_rele(hdl); 1737 } 1738 #endif 1739 } 1740 1741 /* 1742 * The following two routines are used as context operators on threads belonging 1743 * to processes with a private LDT (see sysi86). Due to the rarity of such 1744 * processes, these routines are currently written for best code readability and 1745 * organization rather than speed. We could avoid checking x86_feature at every 1746 * context switch by installing different context ops, depending on the 1747 * x86_feature flags, at LDT creation time -- one for each combination of fast 1748 * syscall feature flags. 1749 */ 1750 1751 /*ARGSUSED*/ 1752 void 1753 cpu_fast_syscall_disable(void *arg) 1754 { 1755 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1756 cpu_sep_disable(); 1757 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1758 cpu_asysc_disable(); 1759 } 1760 1761 /*ARGSUSED*/ 1762 void 1763 cpu_fast_syscall_enable(void *arg) 1764 { 1765 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1766 cpu_sep_enable(); 1767 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1768 cpu_asysc_enable(); 1769 } 1770 1771 static void 1772 cpu_sep_enable(void) 1773 { 1774 ASSERT(x86_feature & X86_SEP); 1775 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1776 1777 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1778 } 1779 1780 static void 1781 cpu_sep_disable(void) 1782 { 1783 ASSERT(x86_feature & X86_SEP); 1784 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1785 1786 /* 1787 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1788 * the sysenter or sysexit instruction to trigger a #gp fault. 1789 */ 1790 wrmsr(MSR_INTC_SEP_CS, 0); 1791 } 1792 1793 static void 1794 cpu_asysc_enable(void) 1795 { 1796 ASSERT(x86_feature & X86_ASYSC); 1797 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1798 1799 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1800 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1801 } 1802 1803 static void 1804 cpu_asysc_disable(void) 1805 { 1806 ASSERT(x86_feature & X86_ASYSC); 1807 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1808 1809 /* 1810 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1811 * executing syscall or sysret with this bit off will incur a #ud trap. 1812 */ 1813 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1814 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1815 } 1816