1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Welcome to the world of the "real mode platter". 30 * See also startup.c, mpcore.s and apic.c for related routines. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/cpuvar.h> 36 #include <sys/kmem.h> 37 #include <sys/archsystm.h> 38 #include <sys/machsystm.h> 39 #include <sys/controlregs.h> 40 #include <sys/x86_archext.h> 41 #include <sys/smp_impldefs.h> 42 #include <sys/sysmacros.h> 43 #include <sys/mach_mmu.h> 44 #include <sys/promif.h> 45 #include <sys/cpu.h> 46 47 extern void real_mode_start(void); 48 extern void real_mode_end(void); 49 50 /* 51 * Fill up the real mode platter to make it easy for real mode code to 52 * kick it off. This area should really be one passed by boot to kernel 53 * and guaranteed to be below 1MB and aligned to 16 bytes. Should also 54 * have identical physical and virtual address in paged mode. 55 */ 56 static ushort_t *warm_reset_vector = NULL; 57 58 int 59 mach_cpucontext_init(void) 60 { 61 ushort_t *vec; 62 63 if (!(vec = (ushort_t *)psm_map_phys(WARM_RESET_VECTOR, 64 sizeof (vec), PROT_READ | PROT_WRITE))) 65 return (-1); 66 /* 67 * setup secondary cpu bios boot up vector 68 */ 69 *vec = (ushort_t)((caddr_t) 70 ((struct rm_platter *)rm_platter_va)->rm_code - rm_platter_va 71 + ((ulong_t)rm_platter_va & 0xf)); 72 vec[1] = (ushort_t)(rm_platter_pa >> 4); 73 warm_reset_vector = vec; 74 75 bcopy((caddr_t)real_mode_start, 76 (caddr_t)((rm_platter_t *)rm_platter_va)->rm_code, 77 (size_t)real_mode_end - (size_t)real_mode_start); 78 79 return (0); 80 } 81 82 void 83 mach_cpucontext_fini(void) 84 { 85 if (warm_reset_vector) 86 psm_unmap_phys((caddr_t)warm_reset_vector, 87 sizeof (warm_reset_vector)); 88 hat_unload(kas.a_hat, (caddr_t)(uintptr_t)rm_platter_pa, MMU_PAGESIZE, 89 HAT_UNLOAD); 90 } 91 92 #if defined(__amd64) 93 extern void *long_mode_64(void); 94 #endif /* __amd64 */ 95 96 void * 97 mach_cpucontext_alloc(struct cpu *cp) 98 { 99 rm_platter_t *rm = (rm_platter_t *)rm_platter_va; 100 struct cpu_tables *ct; 101 struct tss *ntss; 102 103 /* 104 * Allocate space for page directory, stack, tss, gdt and idt. 105 * The page directory has to be page aligned 106 */ 107 ct = kmem_zalloc(sizeof (*ct), KM_SLEEP); 108 if ((uintptr_t)ct & ~MMU_STD_PAGEMASK) 109 panic("mp_startup_init: cpu%d misaligned tables", cp->cpu_id); 110 111 ntss = cp->cpu_tss = &ct->ct_tss; 112 113 #if defined(__amd64) 114 115 /* 116 * #DF (double fault). 117 */ 118 ntss->tss_ist1 = (uint64_t)&ct->ct_stack[sizeof (ct->ct_stack)]; 119 120 #elif defined(__i386) 121 122 ntss->tss_esp0 = ntss->tss_esp1 = ntss->tss_esp2 = ntss->tss_esp = 123 (uint32_t)&ct->ct_stack[sizeof (ct->ct_stack)]; 124 125 ntss->tss_ss0 = ntss->tss_ss1 = ntss->tss_ss2 = ntss->tss_ss = KDS_SEL; 126 127 ntss->tss_eip = (uint32_t)cp->cpu_thread->t_pc; 128 129 ntss->tss_cs = KCS_SEL; 130 ntss->tss_ds = ntss->tss_es = KDS_SEL; 131 ntss->tss_fs = KFS_SEL; 132 ntss->tss_gs = KGS_SEL; 133 134 #endif /* __i386 */ 135 136 /* 137 * Set I/O bit map offset equal to size of TSS segment limit 138 * for no I/O permission map. This will cause all user I/O 139 * instructions to generate #gp fault. 140 */ 141 ntss->tss_bitmapbase = sizeof (*ntss); 142 143 /* 144 * Setup kernel tss. 145 */ 146 set_syssegd((system_desc_t *)&cp->cpu_gdt[GDT_KTSS], cp->cpu_tss, 147 sizeof (*cp->cpu_tss) -1, SDT_SYSTSS, SEL_KPL); 148 149 /* 150 * Now copy all that we've set up onto the real mode platter 151 * for the real mode code to digest as part of starting the cpu. 152 */ 153 154 rm->rm_idt_base = cp->cpu_idt; 155 rm->rm_idt_lim = sizeof (idt0) - 1; 156 rm->rm_gdt_base = cp->cpu_gdt; 157 rm->rm_gdt_lim = ((sizeof (*cp->cpu_gdt) * NGDT)) -1; 158 159 rm->rm_pdbr = getcr3(); 160 rm->rm_cpu = cp->cpu_id; 161 rm->rm_x86feature = x86_feature; 162 rm->rm_cr4 = getcr4(); 163 164 #if defined(__amd64) 165 166 if (getcr3() > 0xffffffffUL) 167 panic("Cannot initialize CPUs; kernel's 64-bit page tables\n" 168 "located above 4G in physical memory (@ 0x%lx)", getcr3()); 169 170 /* 171 * Setup pseudo-descriptors for temporary GDT and IDT for use ONLY 172 * by code in real_mode_start(): 173 * 174 * GDT[0]: NULL selector 175 * GDT[1]: 64-bit CS: Long = 1, Present = 1, bits 12, 11 = 1 176 * 177 * Clear the IDT as interrupts will be off and a limit of 0 will cause 178 * the CPU to triple fault and reset on an NMI, seemingly as reasonable 179 * a course of action as any other, though it may cause the entire 180 * platform to reset in some cases... 181 */ 182 rm->rm_temp_gdt[0] = 0; 183 rm->rm_temp_gdt[TEMPGDT_KCODE64] = 0x20980000000000ULL; 184 185 rm->rm_temp_gdt_lim = (ushort_t)(sizeof (rm->rm_temp_gdt) - 1); 186 rm->rm_temp_gdt_base = rm_platter_pa + 187 (uint32_t)offsetof(rm_platter_t, rm_temp_gdt); 188 rm->rm_temp_idt_lim = 0; 189 rm->rm_temp_idt_base = 0; 190 191 /* 192 * Since the CPU needs to jump to protected mode using an identity 193 * mapped address, we need to calculate it here. 194 */ 195 rm->rm_longmode64_addr = rm_platter_pa + 196 ((uint32_t)long_mode_64 - (uint32_t)real_mode_start); 197 #endif /* __amd64 */ 198 199 return (ct); 200 } 201 202 /*ARGSUSED*/ 203 void 204 mach_cpucontext_free(struct cpu *cp, void *arg, int err) 205 { 206 struct cpu_tables *ct = arg; 207 208 ASSERT(&ct->ct_tss == cp->cpu_tss); 209 210 switch (err) { 211 case 0: 212 break; 213 case ETIMEDOUT: 214 /* 215 * The processor was poked, but failed to start before 216 * we gave up waiting for it. In case it starts later, 217 * don't free anything. 218 */ 219 break; 220 default: 221 /* 222 * Some other, passive, error occurred. 223 */ 224 kmem_free(ct, sizeof (*ct)); 225 cp->cpu_tss = NULL; 226 break; 227 } 228 } 229 230 /* 231 * "Enter monitor." Called via cross-call from stop_other_cpus(). 232 */ 233 void 234 mach_cpu_halt(char *msg) 235 { 236 if (msg) 237 prom_printf("%s\n", msg); 238 239 /*CONSTANTCONDITION*/ 240 while (1) 241 ; 242 } 243 244 void 245 mach_cpu_idle(void) 246 { 247 i86_halt(); 248 } 249 250 void 251 mach_cpu_pause(volatile char *safe) 252 { 253 /* 254 * This cpu is now safe. 255 */ 256 *safe = PAUSE_WAIT; 257 membar_enter(); /* make sure stores are flushed */ 258 259 /* 260 * Now we wait. When we are allowed to continue, safe 261 * will be set to PAUSE_IDLE. 262 */ 263 while (*safe != PAUSE_IDLE) 264 SMT_PAUSE(); 265 } 266 267 /* 268 * Power on CPU. 269 */ 270 /*ARGSUSED*/ 271 int 272 mp_cpu_poweron(struct cpu *cp) 273 { 274 ASSERT(MUTEX_HELD(&cpu_lock)); 275 return (ENOTSUP); /* not supported */ 276 } 277 278 /* 279 * Power off CPU. 280 */ 281 /*ARGSUSED*/ 282 int 283 mp_cpu_poweroff(struct cpu *cp) 284 { 285 ASSERT(MUTEX_HELD(&cpu_lock)); 286 return (ENOTSUP); /* not supported */ 287 } 288