1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Welcome to the world of the "real mode platter". 30 * See also startup.c, mpcore.s and apic.c for related routines. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/cpuvar.h> 36 #include <sys/kmem.h> 37 #include <sys/archsystm.h> 38 #include <sys/machsystm.h> 39 #include <sys/controlregs.h> 40 #include <sys/x86_archext.h> 41 #include <sys/smp_impldefs.h> 42 #include <sys/sysmacros.h> 43 #include <sys/mach_mmu.h> 44 #include <sys/promif.h> 45 #include <sys/cpu.h> 46 #include <vm/hat_i86.h> 47 48 extern void real_mode_start(void); 49 extern void real_mode_end(void); 50 51 /* 52 * Fill up the real mode platter to make it easy for real mode code to 53 * kick it off. This area should really be one passed by boot to kernel 54 * and guaranteed to be below 1MB and aligned to 16 bytes. Should also 55 * have identical physical and virtual address in paged mode. 56 */ 57 static ushort_t *warm_reset_vector = NULL; 58 59 int 60 mach_cpucontext_init(void) 61 { 62 ushort_t *vec; 63 64 if (!(vec = (ushort_t *)psm_map_phys(WARM_RESET_VECTOR, 65 sizeof (vec), PROT_READ | PROT_WRITE))) 66 return (-1); 67 /* 68 * setup secondary cpu bios boot up vector 69 */ 70 *vec = (ushort_t)((caddr_t) 71 ((struct rm_platter *)rm_platter_va)->rm_code - rm_platter_va 72 + ((ulong_t)rm_platter_va & 0xf)); 73 vec[1] = (ushort_t)(rm_platter_pa >> 4); 74 warm_reset_vector = vec; 75 76 bcopy((caddr_t)real_mode_start, 77 (caddr_t)((rm_platter_t *)rm_platter_va)->rm_code, 78 (size_t)real_mode_end - (size_t)real_mode_start); 79 80 return (0); 81 } 82 83 void 84 mach_cpucontext_fini(void) 85 { 86 if (warm_reset_vector) 87 psm_unmap_phys((caddr_t)warm_reset_vector, 88 sizeof (warm_reset_vector)); 89 hat_unload(kas.a_hat, (caddr_t)(uintptr_t)rm_platter_pa, MMU_PAGESIZE, 90 HAT_UNLOAD); 91 } 92 93 #if defined(__amd64) 94 extern void *long_mode_64(void); 95 #endif /* __amd64 */ 96 97 void * 98 mach_cpucontext_alloc(struct cpu *cp) 99 { 100 rm_platter_t *rm = (rm_platter_t *)rm_platter_va; 101 struct cpu_tables *ct; 102 struct tss *ntss; 103 104 /* 105 * Allocate space for page directory, stack, tss, gdt and idt. 106 * The page directory has to be page aligned 107 */ 108 ct = kmem_zalloc(sizeof (*ct), KM_SLEEP); 109 if ((uintptr_t)ct & ~MMU_STD_PAGEMASK) 110 panic("mp_startup_init: cpu%d misaligned tables", cp->cpu_id); 111 112 ntss = cp->cpu_tss = &ct->ct_tss; 113 114 #if defined(__amd64) 115 116 /* 117 * #DF (double fault). 118 */ 119 ntss->tss_ist1 = (uint64_t)&ct->ct_stack[sizeof (ct->ct_stack)]; 120 121 #elif defined(__i386) 122 123 ntss->tss_esp0 = ntss->tss_esp1 = ntss->tss_esp2 = ntss->tss_esp = 124 (uint32_t)&ct->ct_stack[sizeof (ct->ct_stack)]; 125 126 ntss->tss_ss0 = ntss->tss_ss1 = ntss->tss_ss2 = ntss->tss_ss = KDS_SEL; 127 128 ntss->tss_eip = (uint32_t)cp->cpu_thread->t_pc; 129 130 ntss->tss_cs = KCS_SEL; 131 ntss->tss_ds = ntss->tss_es = KDS_SEL; 132 ntss->tss_fs = KFS_SEL; 133 ntss->tss_gs = KGS_SEL; 134 135 #endif /* __i386 */ 136 137 /* 138 * Set I/O bit map offset equal to size of TSS segment limit 139 * for no I/O permission map. This will cause all user I/O 140 * instructions to generate #gp fault. 141 */ 142 ntss->tss_bitmapbase = sizeof (*ntss); 143 144 /* 145 * Setup kernel tss. 146 */ 147 set_syssegd((system_desc_t *)&cp->cpu_gdt[GDT_KTSS], cp->cpu_tss, 148 sizeof (*cp->cpu_tss) -1, SDT_SYSTSS, SEL_KPL); 149 150 /* 151 * Now copy all that we've set up onto the real mode platter 152 * for the real mode code to digest as part of starting the cpu. 153 */ 154 155 rm->rm_idt_base = cp->cpu_idt; 156 rm->rm_idt_lim = sizeof (idt0) - 1; 157 rm->rm_gdt_base = cp->cpu_gdt; 158 rm->rm_gdt_lim = ((sizeof (*cp->cpu_gdt) * NGDT)) -1; 159 160 rm->rm_pdbr = getcr3(); 161 rm->rm_cpu = cp->cpu_id; 162 rm->rm_x86feature = x86_feature; 163 rm->rm_cr4 = getcr4(); 164 165 #if defined(__amd64) 166 167 if (getcr3() > 0xffffffffUL) 168 panic("Cannot initialize CPUs; kernel's 64-bit page tables\n" 169 "located above 4G in physical memory (@ 0x%lx)", getcr3()); 170 171 /* 172 * Setup pseudo-descriptors for temporary GDT and IDT for use ONLY 173 * by code in real_mode_start(): 174 * 175 * GDT[0]: NULL selector 176 * GDT[1]: 64-bit CS: Long = 1, Present = 1, bits 12, 11 = 1 177 * 178 * Clear the IDT as interrupts will be off and a limit of 0 will cause 179 * the CPU to triple fault and reset on an NMI, seemingly as reasonable 180 * a course of action as any other, though it may cause the entire 181 * platform to reset in some cases... 182 */ 183 rm->rm_temp_gdt[0] = 0; 184 rm->rm_temp_gdt[TEMPGDT_KCODE64] = 0x20980000000000ULL; 185 186 rm->rm_temp_gdt_lim = (ushort_t)(sizeof (rm->rm_temp_gdt) - 1); 187 rm->rm_temp_gdt_base = rm_platter_pa + 188 (uint32_t)offsetof(rm_platter_t, rm_temp_gdt); 189 rm->rm_temp_idt_lim = 0; 190 rm->rm_temp_idt_base = 0; 191 192 /* 193 * Since the CPU needs to jump to protected mode using an identity 194 * mapped address, we need to calculate it here. 195 */ 196 rm->rm_longmode64_addr = rm_platter_pa + 197 ((uint32_t)long_mode_64 - (uint32_t)real_mode_start); 198 #endif /* __amd64 */ 199 200 return (ct); 201 } 202 203 /*ARGSUSED*/ 204 void 205 mach_cpucontext_free(struct cpu *cp, void *arg, int err) 206 { 207 struct cpu_tables *ct = arg; 208 209 ASSERT(&ct->ct_tss == cp->cpu_tss); 210 211 switch (err) { 212 case 0: 213 break; 214 case ETIMEDOUT: 215 /* 216 * The processor was poked, but failed to start before 217 * we gave up waiting for it. In case it starts later, 218 * don't free anything. 219 */ 220 break; 221 default: 222 /* 223 * Some other, passive, error occurred. 224 */ 225 kmem_free(ct, sizeof (*ct)); 226 cp->cpu_tss = NULL; 227 break; 228 } 229 } 230 231 /* 232 * "Enter monitor." Called via cross-call from stop_other_cpus(). 233 */ 234 void 235 mach_cpu_halt(char *msg) 236 { 237 if (msg) 238 prom_printf("%s\n", msg); 239 240 /*CONSTANTCONDITION*/ 241 while (1) 242 ; 243 } 244 245 void 246 mach_cpu_idle(void) 247 { 248 tlb_going_idle(); 249 i86_halt(); 250 tlb_service(); 251 } 252 253 void 254 mach_cpu_pause(volatile char *safe) 255 { 256 /* 257 * This cpu is now safe. 258 */ 259 *safe = PAUSE_WAIT; 260 membar_enter(); /* make sure stores are flushed */ 261 262 /* 263 * Now we wait. When we are allowed to continue, safe 264 * will be set to PAUSE_IDLE. 265 */ 266 while (*safe != PAUSE_IDLE) 267 SMT_PAUSE(); 268 } 269 270 /* 271 * Power on CPU. 272 */ 273 /*ARGSUSED*/ 274 int 275 mp_cpu_poweron(struct cpu *cp) 276 { 277 ASSERT(MUTEX_HELD(&cpu_lock)); 278 return (ENOTSUP); /* not supported */ 279 } 280 281 /* 282 * Power off CPU. 283 */ 284 /*ARGSUSED*/ 285 int 286 mp_cpu_poweroff(struct cpu *cp) 287 { 288 ASSERT(MUTEX_HELD(&cpu_lock)); 289 return (ENOTSUP); /* not supported */ 290 } 291