1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #define PSMI_1_6 29 #include <sys/smp_impldefs.h> 30 #include <sys/psm.h> 31 #include <sys/psm_modctl.h> 32 #include <sys/pit.h> 33 #include <sys/cmn_err.h> 34 #include <sys/strlog.h> 35 #include <sys/clock.h> 36 #include <sys/debug.h> 37 #include <sys/rtc.h> 38 #include <sys/x86_archext.h> 39 #include <sys/cpupart.h> 40 #include <sys/cpuvar.h> 41 #include <sys/cmt.h> 42 #include <sys/cpu.h> 43 #include <sys/disp.h> 44 #include <sys/archsystm.h> 45 #include <sys/machsystm.h> 46 #include <sys/sysmacros.h> 47 #include <sys/memlist.h> 48 #include <sys/param.h> 49 #include <sys/promif.h> 50 #if defined(__xpv) 51 #include <sys/hypervisor.h> 52 #endif 53 #include <sys/mach_intr.h> 54 #include <vm/hat_i86.h> 55 #include <sys/kdi_machimpl.h> 56 57 #define OFFSETOF(s, m) (size_t)(&(((s *)0)->m)) 58 59 /* 60 * Local function prototypes 61 */ 62 static int mp_disable_intr(processorid_t cpun); 63 static void mp_enable_intr(processorid_t cpun); 64 static void mach_init(); 65 static void mach_picinit(); 66 static int machhztomhz(uint64_t cpu_freq_hz); 67 static uint64_t mach_getcpufreq(void); 68 static void mach_fixcpufreq(void); 69 static int mach_clkinit(int, int *); 70 static void mach_smpinit(void); 71 static int mach_softlvl_to_vect(int ipl); 72 static void mach_get_platform(int owner); 73 static void mach_construct_info(); 74 static int mach_translate_irq(dev_info_t *dip, int irqno); 75 static int mach_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *, 76 psm_intr_op_t, int *); 77 static void mach_notify_error(int level, char *errmsg); 78 static hrtime_t dummy_hrtime(void); 79 static void dummy_scalehrtime(hrtime_t *); 80 static void cpu_idle(void); 81 static void cpu_wakeup(cpu_t *, int); 82 #ifndef __xpv 83 static void cpu_idle_mwait(void); 84 static void cpu_wakeup_mwait(cpu_t *, int); 85 #endif 86 /* 87 * External reference functions 88 */ 89 extern void return_instr(); 90 extern uint64_t freq_tsc(uint32_t *); 91 #if defined(__i386) 92 extern uint64_t freq_notsc(uint32_t *); 93 #endif 94 extern void pc_gethrestime(timestruc_t *); 95 extern int cpuid_get_coreid(cpu_t *); 96 extern int cpuid_get_chipid(cpu_t *); 97 98 /* 99 * PSM functions initialization 100 */ 101 void (*psm_shutdownf)(int, int) = (void (*)(int, int))return_instr; 102 void (*psm_preshutdownf)(int, int) = (void (*)(int, int))return_instr; 103 void (*psm_notifyf)(int) = (void (*)(int))return_instr; 104 void (*psm_set_idle_cpuf)(int) = (void (*)(int))return_instr; 105 void (*psm_unset_idle_cpuf)(int) = (void (*)(int))return_instr; 106 void (*psminitf)() = mach_init; 107 void (*picinitf)() = return_instr; 108 int (*clkinitf)(int, int *) = (int (*)(int, int *))return_instr; 109 int (*ap_mlsetup)() = (int (*)(void))return_instr; 110 void (*send_dirintf)() = return_instr; 111 void (*setspl)(int) = (void (*)(int))return_instr; 112 int (*addspl)(int, int, int, int) = (int (*)(int, int, int, int))return_instr; 113 int (*delspl)(int, int, int, int) = (int (*)(int, int, int, int))return_instr; 114 void (*kdisetsoftint)(int, struct av_softinfo *)= 115 (void (*)(int, struct av_softinfo *))return_instr; 116 void (*setsoftint)(int, struct av_softinfo *)= 117 (void (*)(int, struct av_softinfo *))return_instr; 118 int (*slvltovect)(int) = (int (*)(int))return_instr; 119 int (*setlvl)(int, int *) = (int (*)(int, int *))return_instr; 120 void (*setlvlx)(int, int) = (void (*)(int, int))return_instr; 121 int (*psm_disable_intr)(int) = mp_disable_intr; 122 void (*psm_enable_intr)(int) = mp_enable_intr; 123 hrtime_t (*gethrtimef)(void) = dummy_hrtime; 124 hrtime_t (*gethrtimeunscaledf)(void) = dummy_hrtime; 125 void (*scalehrtimef)(hrtime_t *) = dummy_scalehrtime; 126 int (*psm_translate_irq)(dev_info_t *, int) = mach_translate_irq; 127 void (*gethrestimef)(timestruc_t *) = pc_gethrestime; 128 void (*psm_notify_error)(int, char *) = (void (*)(int, char *))NULL; 129 int (*psm_get_clockirq)(int) = NULL; 130 int (*psm_get_ipivect)(int, int) = NULL; 131 132 int (*psm_clkinit)(int) = NULL; 133 void (*psm_timer_reprogram)(hrtime_t) = NULL; 134 void (*psm_timer_enable)(void) = NULL; 135 void (*psm_timer_disable)(void) = NULL; 136 void (*psm_post_cyclic_setup)(void *arg) = NULL; 137 int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, psm_intr_op_t, 138 int *) = mach_intr_ops; 139 int (*psm_state)(psm_state_request_t *) = (int (*)(psm_state_request_t *)) 140 return_instr; 141 142 void (*notify_error)(int, char *) = (void (*)(int, char *))return_instr; 143 void (*hrtime_tick)(void) = return_instr; 144 145 /* 146 * True if the generic TSC code is our source of hrtime, rather than whatever 147 * the PSM can provide. 148 */ 149 #ifdef __xpv 150 int tsc_gethrtime_enable = 0; 151 #else 152 int tsc_gethrtime_enable = 1; 153 #endif 154 int tsc_gethrtime_initted = 0; 155 156 /* 157 * True if the hrtime implementation is "hires"; namely, better than microdata. 158 */ 159 int gethrtime_hires = 0; 160 161 /* 162 * Local Static Data 163 */ 164 static struct psm_ops mach_ops; 165 static struct psm_ops *mach_set[4] = {&mach_ops, NULL, NULL, NULL}; 166 static ushort_t mach_ver[4] = {0, 0, 0, 0}; 167 168 /* 169 * If non-zero, idle cpus will become "halted" when there's 170 * no work to do. 171 */ 172 int idle_cpu_use_hlt = 1; 173 174 #ifndef __xpv 175 /* 176 * If non-zero, idle cpus will use mwait if available to halt instead of hlt. 177 */ 178 int idle_cpu_prefer_mwait = 1; 179 #endif 180 181 /*ARGSUSED*/ 182 int 183 pg_plat_hw_shared(cpu_t *cp, pghw_type_t hw) 184 { 185 switch (hw) { 186 case PGHW_IPIPE: 187 if (x86_feature & (X86_HTT)) { 188 /* 189 * Hyper-threading is SMT 190 */ 191 return (1); 192 } else { 193 return (0); 194 } 195 case PGHW_CHIP: 196 if (x86_feature & (X86_CMP|X86_HTT)) 197 return (1); 198 else 199 return (0); 200 case PGHW_CACHE: 201 if (cpuid_get_ncpu_sharing_last_cache(cp) > 1) 202 return (1); 203 else 204 return (0); 205 default: 206 return (0); 207 } 208 } 209 210 /* 211 * Compare two CPUs and see if they have a pghw_type_t sharing relationship 212 * If pghw_type_t is an unsupported hardware type, then return -1 213 */ 214 int 215 pg_plat_cpus_share(cpu_t *cpu_a, cpu_t *cpu_b, pghw_type_t hw) 216 { 217 id_t pgp_a, pgp_b; 218 219 pgp_a = pg_plat_hw_instance_id(cpu_a, hw); 220 pgp_b = pg_plat_hw_instance_id(cpu_b, hw); 221 222 if (pgp_a == -1 || pgp_b == -1) 223 return (-1); 224 225 return (pgp_a == pgp_b); 226 } 227 228 /* 229 * Return a physical instance identifier for known hardware sharing 230 * relationships 231 */ 232 id_t 233 pg_plat_hw_instance_id(cpu_t *cpu, pghw_type_t hw) 234 { 235 switch (hw) { 236 case PGHW_IPIPE: 237 return (cpuid_get_coreid(cpu)); 238 case PGHW_CACHE: 239 return (cpuid_get_last_lvl_cacheid(cpu)); 240 case PGHW_CHIP: 241 return (cpuid_get_chipid(cpu)); 242 default: 243 return (-1); 244 } 245 } 246 247 int 248 pg_plat_hw_level(pghw_type_t hw) 249 { 250 int i; 251 static pghw_type_t hw_hier[] = { 252 PGHW_IPIPE, 253 PGHW_CACHE, 254 PGHW_CHIP, 255 PGHW_NUM_COMPONENTS 256 }; 257 258 for (i = 0; hw_hier[i] != PGHW_NUM_COMPONENTS; i++) { 259 if (hw_hier[i] == hw) 260 return (i); 261 } 262 return (-1); 263 } 264 265 /* 266 * Return 1 if CMT load balancing policies should be 267 * implemented across instances of the specified hardware 268 * sharing relationship. 269 */ 270 int 271 pg_plat_cmt_load_bal_hw(pghw_type_t hw) 272 { 273 if (hw == PGHW_IPIPE || 274 hw == PGHW_FPU || 275 hw == PGHW_CHIP || 276 hw == PGHW_CACHE) 277 return (1); 278 else 279 return (0); 280 } 281 282 283 /* 284 * Return 1 if thread affinity polices should be implemented 285 * for instances of the specifed hardware sharing relationship. 286 */ 287 int 288 pg_plat_cmt_affinity_hw(pghw_type_t hw) 289 { 290 if (hw == PGHW_CACHE) 291 return (1); 292 else 293 return (0); 294 } 295 296 id_t 297 pg_plat_get_core_id(cpu_t *cpu) 298 { 299 return ((id_t)cpuid_get_coreid(cpu)); 300 } 301 302 void 303 cmp_set_nosteal_interval(void) 304 { 305 /* Set the nosteal interval (used by disp_getbest()) to 100us */ 306 nosteal_nsec = 100000UL; 307 } 308 309 /* 310 * Routine to ensure initial callers to hrtime gets 0 as return 311 */ 312 static hrtime_t 313 dummy_hrtime(void) 314 { 315 return (0); 316 } 317 318 /* ARGSUSED */ 319 static void 320 dummy_scalehrtime(hrtime_t *ticks) 321 {} 322 323 /* 324 * Idle the present CPU until awoken via an interrupt 325 */ 326 static void 327 cpu_idle(void) 328 { 329 cpu_t *cpup = CPU; 330 processorid_t cpun = cpup->cpu_id; 331 cpupart_t *cp = cpup->cpu_part; 332 int hset_update = 1; 333 334 /* 335 * If this CPU is online, and there's multiple CPUs 336 * in the system, then we should notate our halting 337 * by adding ourselves to the partition's halted CPU 338 * bitmap. This allows other CPUs to find/awaken us when 339 * work becomes available. 340 */ 341 if (cpup->cpu_flags & CPU_OFFLINE || ncpus == 1) 342 hset_update = 0; 343 344 /* 345 * Add ourselves to the partition's halted CPUs bitmask 346 * and set our HALTED flag, if necessary. 347 * 348 * When a thread becomes runnable, it is placed on the queue 349 * and then the halted cpuset is checked to determine who 350 * (if anyone) should be awoken. We therefore need to first 351 * add ourselves to the halted cpuset, and and then check if there 352 * is any work available. 353 * 354 * Note that memory barriers after updating the HALTED flag 355 * are not necessary since an atomic operation (updating the bitmap) 356 * immediately follows. On x86 the atomic operation acts as a 357 * memory barrier for the update of cpu_disp_flags. 358 */ 359 if (hset_update) { 360 cpup->cpu_disp_flags |= CPU_DISP_HALTED; 361 CPUSET_ATOMIC_ADD(cp->cp_mach->mc_haltset, cpun); 362 } 363 364 /* 365 * Check to make sure there's really nothing to do. 366 * Work destined for this CPU may become available after 367 * this check. We'll be notified through the clearing of our 368 * bit in the halted CPU bitmask, and a poke. 369 */ 370 if (disp_anywork()) { 371 if (hset_update) { 372 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 373 CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun); 374 } 375 return; 376 } 377 378 /* 379 * We're on our way to being halted. 380 * 381 * Disable interrupts now, so that we'll awaken immediately 382 * after halting if someone tries to poke us between now and 383 * the time we actually halt. 384 * 385 * We check for the presence of our bit after disabling interrupts. 386 * If it's cleared, we'll return. If the bit is cleared after 387 * we check then the poke will pop us out of the halted state. 388 * 389 * This means that the ordering of the poke and the clearing 390 * of the bit by cpu_wakeup is important. 391 * cpu_wakeup() must clear, then poke. 392 * cpu_idle() must disable interrupts, then check for the bit. 393 */ 394 cli(); 395 396 if (hset_update && !CPU_IN_SET(cp->cp_mach->mc_haltset, cpun)) { 397 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 398 sti(); 399 return; 400 } 401 402 /* 403 * The check for anything locally runnable is here for performance 404 * and isn't needed for correctness. disp_nrunnable ought to be 405 * in our cache still, so it's inexpensive to check, and if there 406 * is anything runnable we won't have to wait for the poke. 407 */ 408 if (cpup->cpu_disp->disp_nrunnable != 0) { 409 if (hset_update) { 410 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 411 CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun); 412 } 413 sti(); 414 return; 415 } 416 417 mach_cpu_idle(); 418 419 /* 420 * We're no longer halted 421 */ 422 if (hset_update) { 423 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 424 CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun); 425 } 426 } 427 428 429 /* 430 * If "cpu" is halted, then wake it up clearing its halted bit in advance. 431 * Otherwise, see if other CPUs in the cpu partition are halted and need to 432 * be woken up so that they can steal the thread we placed on this CPU. 433 * This function is only used on MP systems. 434 */ 435 static void 436 cpu_wakeup(cpu_t *cpu, int bound) 437 { 438 uint_t cpu_found; 439 int result; 440 cpupart_t *cp; 441 442 cp = cpu->cpu_part; 443 if (CPU_IN_SET(cp->cp_mach->mc_haltset, cpu->cpu_id)) { 444 /* 445 * Clear the halted bit for that CPU since it will be 446 * poked in a moment. 447 */ 448 CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpu->cpu_id); 449 /* 450 * We may find the current CPU present in the halted cpuset 451 * if we're in the context of an interrupt that occurred 452 * before we had a chance to clear our bit in cpu_idle(). 453 * Poking ourself is obviously unnecessary, since if 454 * we're here, we're not halted. 455 */ 456 if (cpu != CPU) 457 poke_cpu(cpu->cpu_id); 458 return; 459 } else { 460 /* 461 * This cpu isn't halted, but it's idle or undergoing a 462 * context switch. No need to awaken anyone else. 463 */ 464 if (cpu->cpu_thread == cpu->cpu_idle_thread || 465 cpu->cpu_disp_flags & CPU_DISP_DONTSTEAL) 466 return; 467 } 468 469 /* 470 * No need to wake up other CPUs if the thread we just enqueued 471 * is bound. 472 */ 473 if (bound) 474 return; 475 476 477 /* 478 * See if there's any other halted CPUs. If there are, then 479 * select one, and awaken it. 480 * It's possible that after we find a CPU, somebody else 481 * will awaken it before we get the chance. 482 * In that case, look again. 483 */ 484 do { 485 CPUSET_FIND(cp->cp_mach->mc_haltset, cpu_found); 486 if (cpu_found == CPUSET_NOTINSET) 487 return; 488 489 ASSERT(cpu_found >= 0 && cpu_found < NCPU); 490 CPUSET_ATOMIC_XDEL(cp->cp_mach->mc_haltset, cpu_found, result); 491 } while (result < 0); 492 493 if (cpu_found != CPU->cpu_id) 494 poke_cpu(cpu_found); 495 } 496 497 #ifndef __xpv 498 /* 499 * Idle the present CPU until awoken via touching its monitored line 500 */ 501 static void 502 cpu_idle_mwait(void) 503 { 504 volatile uint32_t *mcpu_mwait = CPU->cpu_m.mcpu_mwait; 505 cpu_t *cpup = CPU; 506 processorid_t cpun = cpup->cpu_id; 507 cpupart_t *cp = cpup->cpu_part; 508 int hset_update = 1; 509 510 /* 511 * Set our mcpu_mwait here, so we can tell if anyone trys to 512 * wake us between now and when we call mwait. No other cpu will 513 * attempt to set our mcpu_mwait until we add ourself to the haltset. 514 */ 515 *mcpu_mwait = MWAIT_HALTED; 516 517 /* 518 * If this CPU is online, and there's multiple CPUs 519 * in the system, then we should notate our halting 520 * by adding ourselves to the partition's halted CPU 521 * bitmap. This allows other CPUs to find/awaken us when 522 * work becomes available. 523 */ 524 if (cpup->cpu_flags & CPU_OFFLINE || ncpus == 1) 525 hset_update = 0; 526 527 /* 528 * Add ourselves to the partition's halted CPUs bitmask 529 * and set our HALTED flag, if necessary. 530 * 531 * When a thread becomes runnable, it is placed on the queue 532 * and then the halted cpuset is checked to determine who 533 * (if anyone) should be awoken. We therefore need to first 534 * add ourselves to the halted cpuset, and and then check if there 535 * is any work available. 536 * 537 * Note that memory barriers after updating the HALTED flag 538 * are not necessary since an atomic operation (updating the bitmap) 539 * immediately follows. On x86 the atomic operation acts as a 540 * memory barrier for the update of cpu_disp_flags. 541 */ 542 if (hset_update) { 543 cpup->cpu_disp_flags |= CPU_DISP_HALTED; 544 CPUSET_ATOMIC_ADD(cp->cp_mach->mc_haltset, cpun); 545 } 546 547 /* 548 * Check to make sure there's really nothing to do. 549 * Work destined for this CPU may become available after 550 * this check. We'll be notified through the clearing of our 551 * bit in the halted CPU bitmask, and a write to our mcpu_mwait. 552 * 553 * disp_anywork() checks disp_nrunnable, so we do not have to later. 554 */ 555 if (disp_anywork()) { 556 if (hset_update) { 557 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 558 CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun); 559 } 560 return; 561 } 562 563 /* 564 * We're on our way to being halted. 565 * To avoid a lost wakeup, arm the monitor before checking if another 566 * cpu wrote to mcpu_mwait to wake us up. 567 */ 568 i86_monitor(mcpu_mwait, 0, 0); 569 if (*mcpu_mwait == MWAIT_HALTED) { 570 tlb_going_idle(); 571 i86_mwait(0, 0); 572 tlb_service(); 573 } 574 575 /* 576 * We're no longer halted 577 */ 578 if (hset_update) { 579 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 580 CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun); 581 } 582 } 583 584 /* 585 * If "cpu" is halted in mwait, then wake it up clearing its halted bit in 586 * advance. Otherwise, see if other CPUs in the cpu partition are halted and 587 * need to be woken up so that they can steal the thread we placed on this CPU. 588 * This function is only used on MP systems. 589 */ 590 static void 591 cpu_wakeup_mwait(cpu_t *cp, int bound) 592 { 593 cpupart_t *cpu_part; 594 uint_t cpu_found; 595 int result; 596 597 cpu_part = cp->cpu_part; 598 599 /* 600 * Clear the halted bit for that CPU since it will be woken up 601 * in a moment. 602 */ 603 if (CPU_IN_SET(cpu_part->cp_mach->mc_haltset, cp->cpu_id)) { 604 /* 605 * Clear the halted bit for that CPU since it will be 606 * poked in a moment. 607 */ 608 CPUSET_ATOMIC_DEL(cpu_part->cp_mach->mc_haltset, cp->cpu_id); 609 /* 610 * We may find the current CPU present in the halted cpuset 611 * if we're in the context of an interrupt that occurred 612 * before we had a chance to clear our bit in cpu_idle(). 613 * Waking ourself is obviously unnecessary, since if 614 * we're here, we're not halted. 615 * 616 * monitor/mwait wakeup via writing to our cache line is 617 * harmless and less expensive than always checking if we 618 * are waking ourself which is an uncommon case. 619 */ 620 MWAIT_WAKEUP(cp); /* write to monitored line */ 621 return; 622 } else { 623 /* 624 * This cpu isn't halted, but it's idle or undergoing a 625 * context switch. No need to awaken anyone else. 626 */ 627 if (cp->cpu_thread == cp->cpu_idle_thread || 628 cp->cpu_disp_flags & CPU_DISP_DONTSTEAL) 629 return; 630 } 631 632 /* 633 * No need to wake up other CPUs if the thread we just enqueued 634 * is bound. 635 */ 636 if (bound) 637 return; 638 639 640 /* 641 * See if there's any other halted CPUs. If there are, then 642 * select one, and awaken it. 643 * It's possible that after we find a CPU, somebody else 644 * will awaken it before we get the chance. 645 * In that case, look again. 646 */ 647 do { 648 CPUSET_FIND(cpu_part->cp_mach->mc_haltset, cpu_found); 649 if (cpu_found == CPUSET_NOTINSET) 650 return; 651 652 ASSERT(cpu_found >= 0 && cpu_found < NCPU); 653 CPUSET_ATOMIC_XDEL(cpu_part->cp_mach->mc_haltset, cpu_found, 654 result); 655 } while (result < 0); 656 657 /* 658 * Do not check if cpu_found is ourself as monitor/mwait wakeup is 659 * cheap. 660 */ 661 MWAIT_WAKEUP(cpu[cpu_found]); /* write to monitored line */ 662 } 663 #endif 664 665 void (*cpu_pause_handler)(volatile char *) = NULL; 666 667 static int 668 mp_disable_intr(int cpun) 669 { 670 /* 671 * switch to the offline cpu 672 */ 673 affinity_set(cpun); 674 /* 675 * raise ipl to just below cross call 676 */ 677 splx(XC_MED_PIL-1); 678 /* 679 * set base spl to prevent the next swtch to idle from 680 * lowering back to ipl 0 681 */ 682 CPU->cpu_intr_actv |= (1 << (XC_MED_PIL-1)); 683 set_base_spl(); 684 affinity_clear(); 685 return (DDI_SUCCESS); 686 } 687 688 static void 689 mp_enable_intr(int cpun) 690 { 691 /* 692 * switch to the online cpu 693 */ 694 affinity_set(cpun); 695 /* 696 * clear the interrupt active mask 697 */ 698 CPU->cpu_intr_actv &= ~(1 << (XC_MED_PIL-1)); 699 set_base_spl(); 700 (void) spl0(); 701 affinity_clear(); 702 } 703 704 static void 705 mach_get_platform(int owner) 706 { 707 void **srv_opsp; 708 void **clt_opsp; 709 int i; 710 int total_ops; 711 712 /* fix up psm ops */ 713 srv_opsp = (void **)mach_set[0]; 714 clt_opsp = (void **)mach_set[owner]; 715 if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01) 716 total_ops = sizeof (struct psm_ops_ver01) / 717 sizeof (void (*)(void)); 718 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_1) 719 /* no psm_notify_func */ 720 total_ops = OFFSETOF(struct psm_ops, psm_notify_func) / 721 sizeof (void (*)(void)); 722 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_2) 723 /* no psm_timer funcs */ 724 total_ops = OFFSETOF(struct psm_ops, psm_timer_reprogram) / 725 sizeof (void (*)(void)); 726 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_3) 727 /* no psm_preshutdown function */ 728 total_ops = OFFSETOF(struct psm_ops, psm_preshutdown) / 729 sizeof (void (*)(void)); 730 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_4) 731 /* no psm_preshutdown function */ 732 total_ops = OFFSETOF(struct psm_ops, psm_intr_ops) / 733 sizeof (void (*)(void)); 734 else 735 total_ops = sizeof (struct psm_ops) / sizeof (void (*)(void)); 736 737 /* 738 * Save the version of the PSM module, in case we need to 739 * bahave differently based on version. 740 */ 741 mach_ver[0] = mach_ver[owner]; 742 743 for (i = 0; i < total_ops; i++) 744 if (clt_opsp[i] != NULL) 745 srv_opsp[i] = clt_opsp[i]; 746 } 747 748 static void 749 mach_construct_info() 750 { 751 struct psm_sw *swp; 752 int mach_cnt[PSM_OWN_OVERRIDE+1] = {0}; 753 int conflict_owner = 0; 754 755 if (psmsw->psw_forw == psmsw) 756 panic("No valid PSM modules found"); 757 mutex_enter(&psmsw_lock); 758 for (swp = psmsw->psw_forw; swp != psmsw; swp = swp->psw_forw) { 759 if (!(swp->psw_flag & PSM_MOD_IDENTIFY)) 760 continue; 761 mach_set[swp->psw_infop->p_owner] = swp->psw_infop->p_ops; 762 mach_ver[swp->psw_infop->p_owner] = swp->psw_infop->p_version; 763 mach_cnt[swp->psw_infop->p_owner]++; 764 } 765 mutex_exit(&psmsw_lock); 766 767 mach_get_platform(PSM_OWN_SYS_DEFAULT); 768 769 /* check to see are there any conflicts */ 770 if (mach_cnt[PSM_OWN_EXCLUSIVE] > 1) 771 conflict_owner = PSM_OWN_EXCLUSIVE; 772 if (mach_cnt[PSM_OWN_OVERRIDE] > 1) 773 conflict_owner = PSM_OWN_OVERRIDE; 774 if (conflict_owner) { 775 /* remove all psm modules except uppc */ 776 cmn_err(CE_WARN, 777 "Conflicts detected on the following PSM modules:"); 778 mutex_enter(&psmsw_lock); 779 for (swp = psmsw->psw_forw; swp != psmsw; swp = swp->psw_forw) { 780 if (swp->psw_infop->p_owner == conflict_owner) 781 cmn_err(CE_WARN, "%s ", 782 swp->psw_infop->p_mach_idstring); 783 } 784 mutex_exit(&psmsw_lock); 785 cmn_err(CE_WARN, 786 "Setting the system back to SINGLE processor mode!"); 787 cmn_err(CE_WARN, 788 "Please edit /etc/mach to remove the invalid PSM module."); 789 return; 790 } 791 792 if (mach_set[PSM_OWN_EXCLUSIVE]) 793 mach_get_platform(PSM_OWN_EXCLUSIVE); 794 795 if (mach_set[PSM_OWN_OVERRIDE]) 796 mach_get_platform(PSM_OWN_OVERRIDE); 797 } 798 799 static void 800 mach_init() 801 { 802 struct psm_ops *pops; 803 804 mach_construct_info(); 805 806 pops = mach_set[0]; 807 808 /* register the interrupt and clock initialization rotuines */ 809 picinitf = mach_picinit; 810 clkinitf = mach_clkinit; 811 psm_get_clockirq = pops->psm_get_clockirq; 812 813 /* register the interrupt setup code */ 814 slvltovect = mach_softlvl_to_vect; 815 addspl = pops->psm_addspl; 816 delspl = pops->psm_delspl; 817 818 if (pops->psm_translate_irq) 819 psm_translate_irq = pops->psm_translate_irq; 820 if (pops->psm_intr_ops) 821 psm_intr_ops = pops->psm_intr_ops; 822 823 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) 824 /* 825 * Time-of-day functionality now handled in TOD modules. 826 * (Warn about PSM modules that think that we're going to use 827 * their ops vectors.) 828 */ 829 if (pops->psm_tod_get) 830 cmn_err(CE_WARN, "obsolete psm_tod_get op %p", 831 (void *)pops->psm_tod_get); 832 833 if (pops->psm_tod_set) 834 cmn_err(CE_WARN, "obsolete psm_tod_set op %p", 835 (void *)pops->psm_tod_set); 836 #endif 837 838 if (pops->psm_notify_error) { 839 psm_notify_error = mach_notify_error; 840 notify_error = pops->psm_notify_error; 841 } 842 843 (*pops->psm_softinit)(); 844 845 /* 846 * Initialize the dispatcher's function hooks 847 * to enable CPU halting when idle. 848 * Do not use monitor/mwait if idle_cpu_use_hlt is not set(spin idle) 849 * or idle_cpu_prefer_mwait is not set. 850 * Allocate monitor/mwait buffer for cpu0. 851 */ 852 if (idle_cpu_use_hlt) { 853 idle_cpu = cpu_idle; 854 #ifndef __xpv 855 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) { 856 CPU->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 857 /* 858 * Protect ourself from insane mwait size. 859 */ 860 if (CPU->cpu_m.mcpu_mwait == NULL) { 861 #ifdef DEBUG 862 cmn_err(CE_NOTE, "Using hlt idle. Cannot " 863 "handle cpu 0 mwait size."); 864 #endif 865 idle_cpu_prefer_mwait = 0; 866 idle_cpu = cpu_idle; 867 } else { 868 idle_cpu = cpu_idle_mwait; 869 } 870 } else { 871 idle_cpu = cpu_idle; 872 } 873 #endif 874 } 875 876 mach_smpinit(); 877 } 878 879 static void 880 mach_smpinit(void) 881 { 882 struct psm_ops *pops; 883 processorid_t cpu_id; 884 int cnt; 885 cpuset_t cpumask; 886 887 pops = mach_set[0]; 888 889 cpu_id = -1; 890 cpu_id = (*pops->psm_get_next_processorid)(cpu_id); 891 for (cnt = 0, CPUSET_ZERO(cpumask); cpu_id != -1; cnt++) { 892 CPUSET_ADD(cpumask, cpu_id); 893 cpu_id = (*pops->psm_get_next_processorid)(cpu_id); 894 } 895 896 mp_cpus = cpumask; 897 898 /* MP related routines */ 899 ap_mlsetup = pops->psm_post_cpu_start; 900 send_dirintf = pops->psm_send_ipi; 901 902 /* optional MP related routines */ 903 if (pops->psm_shutdown) 904 psm_shutdownf = pops->psm_shutdown; 905 if (pops->psm_preshutdown) 906 psm_preshutdownf = pops->psm_preshutdown; 907 if (pops->psm_notify_func) 908 psm_notifyf = pops->psm_notify_func; 909 if (pops->psm_set_idlecpu) 910 psm_set_idle_cpuf = pops->psm_set_idlecpu; 911 if (pops->psm_unset_idlecpu) 912 psm_unset_idle_cpuf = pops->psm_unset_idlecpu; 913 914 psm_clkinit = pops->psm_clkinit; 915 916 if (pops->psm_timer_reprogram) 917 psm_timer_reprogram = pops->psm_timer_reprogram; 918 919 if (pops->psm_timer_enable) 920 psm_timer_enable = pops->psm_timer_enable; 921 922 if (pops->psm_timer_disable) 923 psm_timer_disable = pops->psm_timer_disable; 924 925 if (pops->psm_post_cyclic_setup) 926 psm_post_cyclic_setup = pops->psm_post_cyclic_setup; 927 928 if (pops->psm_state) 929 psm_state = pops->psm_state; 930 931 /* check for multiple cpu's */ 932 if (cnt < 2) 933 return; 934 935 /* check for MP platforms */ 936 if (pops->psm_cpu_start == NULL) 937 return; 938 939 /* 940 * Set the dispatcher hook to enable cpu "wake up" 941 * when a thread becomes runnable. 942 */ 943 if (idle_cpu_use_hlt) { 944 disp_enq_thread = cpu_wakeup; 945 #ifndef __xpv 946 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) 947 disp_enq_thread = cpu_wakeup_mwait; 948 #endif 949 } 950 951 if (pops->psm_disable_intr) 952 psm_disable_intr = pops->psm_disable_intr; 953 if (pops->psm_enable_intr) 954 psm_enable_intr = pops->psm_enable_intr; 955 956 psm_get_ipivect = pops->psm_get_ipivect; 957 958 (void) add_avintr((void *)NULL, XC_HI_PIL, xc_serv, "xc_hi_intr", 959 (*pops->psm_get_ipivect)(XC_HI_PIL, PSM_INTR_IPI_HI), 960 (caddr_t)X_CALL_HIPRI, NULL, NULL, NULL); 961 (void) add_avintr((void *)NULL, XC_MED_PIL, xc_serv, "xc_med_intr", 962 (*pops->psm_get_ipivect)(XC_MED_PIL, PSM_INTR_IPI_LO), 963 (caddr_t)X_CALL_MEDPRI, NULL, NULL, NULL); 964 965 (void) (*pops->psm_get_ipivect)(XC_CPUPOKE_PIL, PSM_INTR_POKE); 966 } 967 968 static void 969 mach_picinit() 970 { 971 struct psm_ops *pops; 972 973 pops = mach_set[0]; 974 975 /* register the interrupt handlers */ 976 setlvl = pops->psm_intr_enter; 977 setlvlx = pops->psm_intr_exit; 978 979 /* initialize the interrupt hardware */ 980 (*pops->psm_picinit)(); 981 982 /* set interrupt mask for current ipl */ 983 setspl = pops->psm_setspl; 984 cli(); 985 setspl(CPU->cpu_pri); 986 } 987 988 uint_t cpu_freq; /* MHz */ 989 uint64_t cpu_freq_hz; /* measured (in hertz) */ 990 991 #define MEGA_HZ 1000000 992 993 #ifdef __xpv 994 995 int xpv_cpufreq_workaround = 1; 996 int xpv_cpufreq_verbose = 0; 997 998 #else /* __xpv */ 999 1000 static uint64_t 1001 mach_calchz(uint32_t pit_counter, uint64_t *processor_clks) 1002 { 1003 uint64_t cpu_hz; 1004 1005 if ((pit_counter == 0) || (*processor_clks == 0) || 1006 (*processor_clks > (((uint64_t)-1) / PIT_HZ))) 1007 return (0); 1008 1009 cpu_hz = ((uint64_t)PIT_HZ * *processor_clks) / pit_counter; 1010 1011 return (cpu_hz); 1012 } 1013 1014 #endif /* __xpv */ 1015 1016 static uint64_t 1017 mach_getcpufreq(void) 1018 { 1019 #if defined(__xpv) 1020 vcpu_time_info_t *vti = &CPU->cpu_m.mcpu_vcpu_info->time; 1021 uint64_t cpu_hz; 1022 1023 /* 1024 * During dom0 bringup, it was noted that on at least one older 1025 * Intel HT machine, the hypervisor initially gives a tsc_to_system_mul 1026 * value that is quite wrong (the 3.06GHz clock was reported 1027 * as 4.77GHz) 1028 * 1029 * The curious thing is, that if you stop the kernel at entry, 1030 * breakpoint here and inspect the value with kmdb, the value 1031 * is correct - but if you don't stop and simply enable the 1032 * printf statement (below), you can see the bad value printed 1033 * here. Almost as if something kmdb did caused the hypervisor to 1034 * figure it out correctly. And, note that the hypervisor 1035 * eventually -does- figure it out correctly ... if you look at 1036 * the field later in the life of dom0, it is correct. 1037 * 1038 * For now, on dom0, we employ a slightly cheesy workaround of 1039 * using the DOM0_PHYSINFO hypercall. 1040 */ 1041 if (DOMAIN_IS_INITDOMAIN(xen_info) && xpv_cpufreq_workaround) { 1042 xen_sysctl_t op0, *op = &op0; 1043 1044 op->cmd = XEN_SYSCTL_physinfo; 1045 op->interface_version = XEN_SYSCTL_INTERFACE_VERSION; 1046 if (HYPERVISOR_sysctl(op) != 0) 1047 panic("physinfo op refused"); 1048 1049 cpu_hz = 1000 * (uint64_t)op->u.physinfo.cpu_khz; 1050 } else { 1051 cpu_hz = (UINT64_C(1000000000) << 32) / vti->tsc_to_system_mul; 1052 1053 if (vti->tsc_shift < 0) 1054 cpu_hz <<= -vti->tsc_shift; 1055 else 1056 cpu_hz >>= vti->tsc_shift; 1057 } 1058 1059 if (xpv_cpufreq_verbose) 1060 printf("mach_getcpufreq: system_mul 0x%x, shift %d, " 1061 "cpu_hz %" PRId64 "Hz\n", 1062 vti->tsc_to_system_mul, vti->tsc_shift, cpu_hz); 1063 1064 return (cpu_hz); 1065 #else /* __xpv */ 1066 uint32_t pit_counter; 1067 uint64_t processor_clks; 1068 1069 if (x86_feature & X86_TSC) { 1070 /* 1071 * We have a TSC. freq_tsc() knows how to measure the number 1072 * of clock cycles sampled against the PIT. 1073 */ 1074 ulong_t flags = clear_int_flag(); 1075 processor_clks = freq_tsc(&pit_counter); 1076 restore_int_flag(flags); 1077 return (mach_calchz(pit_counter, &processor_clks)); 1078 } else if (x86_vendor == X86_VENDOR_Cyrix || x86_type == X86_TYPE_P5) { 1079 #if defined(__amd64) 1080 panic("mach_getcpufreq: no TSC!"); 1081 #elif defined(__i386) 1082 /* 1083 * We are a Cyrix based on a 6x86 core or an Intel Pentium 1084 * for which freq_notsc() knows how to measure the number of 1085 * elapsed clock cycles sampled against the PIT 1086 */ 1087 ulong_t flags = clear_int_flag(); 1088 processor_clks = freq_notsc(&pit_counter); 1089 restore_int_flag(flags); 1090 return (mach_calchz(pit_counter, &processor_clks)); 1091 #endif /* __i386 */ 1092 } 1093 1094 /* We do not know how to calculate cpu frequency for this cpu. */ 1095 return (0); 1096 #endif /* __xpv */ 1097 } 1098 1099 /* 1100 * If the clock speed of a cpu is found to be reported incorrectly, do not add 1101 * to this array, instead improve the accuracy of the algorithm that determines 1102 * the clock speed of the processor or extend the implementation to support the 1103 * vendor as appropriate. This is here only to support adjusting the speed on 1104 * older slower processors that mach_fixcpufreq() would not be able to account 1105 * for otherwise. 1106 */ 1107 static int x86_cpu_freq[] = { 60, 75, 80, 90, 120, 160, 166, 175, 180, 233 }; 1108 1109 /* 1110 * On fast processors the clock frequency that is measured may be off by 1111 * a few MHz from the value printed on the part. This is a combination of 1112 * the factors that for such fast parts being off by this much is within 1113 * the tolerances for manufacture and because of the difficulties in the 1114 * measurement that can lead to small error. This function uses some 1115 * heuristics in order to tweak the value that was measured to match what 1116 * is most likely printed on the part. 1117 * 1118 * Some examples: 1119 * AMD Athlon 1000 mhz measured as 998 mhz 1120 * Intel Pentium III Xeon 733 mhz measured as 731 mhz 1121 * Intel Pentium IV 1500 mhz measured as 1495mhz 1122 * 1123 * If in the future this function is no longer sufficient to correct 1124 * for the error in the measurement, then the algorithm used to perform 1125 * the measurement will have to be improved in order to increase accuracy 1126 * rather than adding horrible and questionable kludges here. 1127 * 1128 * This is called after the cyclics subsystem because of the potential 1129 * that the heuristics within may give a worse estimate of the clock 1130 * frequency than the value that was measured. 1131 */ 1132 static void 1133 mach_fixcpufreq(void) 1134 { 1135 uint32_t freq, mul, near66, delta66, near50, delta50, fixed, delta, i; 1136 1137 freq = (uint32_t)cpu_freq; 1138 1139 /* 1140 * Find the nearest integer multiple of 200/3 (about 66) MHz to the 1141 * measured speed taking into account that the 667 MHz parts were 1142 * the first to round-up. 1143 */ 1144 mul = (uint32_t)((3 * (uint64_t)freq + 100) / 200); 1145 near66 = (uint32_t)((200 * (uint64_t)mul + ((mul >= 10) ? 1 : 0)) / 3); 1146 delta66 = (near66 > freq) ? (near66 - freq) : (freq - near66); 1147 1148 /* Find the nearest integer multiple of 50 MHz to the measured speed */ 1149 mul = (freq + 25) / 50; 1150 near50 = mul * 50; 1151 delta50 = (near50 > freq) ? (near50 - freq) : (freq - near50); 1152 1153 /* Find the closer of the two */ 1154 if (delta66 < delta50) { 1155 fixed = near66; 1156 delta = delta66; 1157 } else { 1158 fixed = near50; 1159 delta = delta50; 1160 } 1161 1162 if (fixed > INT_MAX) 1163 return; 1164 1165 /* 1166 * Some older parts have a core clock frequency that is not an 1167 * integral multiple of 50 or 66 MHz. Check if one of the old 1168 * clock frequencies is closer to the measured value than any 1169 * of the integral multiples of 50 an 66, and if so set fixed 1170 * and delta appropriately to represent the closest value. 1171 */ 1172 i = sizeof (x86_cpu_freq) / sizeof (int); 1173 while (i > 0) { 1174 i--; 1175 1176 if (x86_cpu_freq[i] <= freq) { 1177 mul = freq - x86_cpu_freq[i]; 1178 1179 if (mul < delta) { 1180 fixed = x86_cpu_freq[i]; 1181 delta = mul; 1182 } 1183 1184 break; 1185 } 1186 1187 mul = x86_cpu_freq[i] - freq; 1188 1189 if (mul < delta) { 1190 fixed = x86_cpu_freq[i]; 1191 delta = mul; 1192 } 1193 } 1194 1195 /* 1196 * Set a reasonable maximum for how much to correct the measured 1197 * result by. This check is here to prevent the adjustment made 1198 * by this function from being more harm than good. It is entirely 1199 * possible that in the future parts will be made that are not 1200 * integral multiples of 66 or 50 in clock frequency or that 1201 * someone may overclock a part to some odd frequency. If the 1202 * measured value is farther from the corrected value than 1203 * allowed, then assume the corrected value is in error and use 1204 * the measured value. 1205 */ 1206 if (6 < delta) 1207 return; 1208 1209 cpu_freq = (int)fixed; 1210 } 1211 1212 1213 static int 1214 machhztomhz(uint64_t cpu_freq_hz) 1215 { 1216 uint64_t cpu_mhz; 1217 1218 /* Round to nearest MHZ */ 1219 cpu_mhz = (cpu_freq_hz + (MEGA_HZ / 2)) / MEGA_HZ; 1220 1221 if (cpu_mhz > INT_MAX) 1222 return (0); 1223 1224 return ((int)cpu_mhz); 1225 1226 } 1227 1228 1229 static int 1230 mach_clkinit(int preferred_mode, int *set_mode) 1231 { 1232 struct psm_ops *pops; 1233 int resolution; 1234 1235 pops = mach_set[0]; 1236 1237 cpu_freq_hz = mach_getcpufreq(); 1238 1239 cpu_freq = machhztomhz(cpu_freq_hz); 1240 1241 if (!(x86_feature & X86_TSC) || (cpu_freq == 0)) 1242 tsc_gethrtime_enable = 0; 1243 1244 #ifndef __xpv 1245 if (tsc_gethrtime_enable) { 1246 tsc_hrtimeinit(cpu_freq_hz); 1247 } else 1248 #endif 1249 { 1250 if (pops->psm_hrtimeinit) 1251 (*pops->psm_hrtimeinit)(); 1252 gethrtimef = pops->psm_gethrtime; 1253 gethrtimeunscaledf = gethrtimef; 1254 /* scalehrtimef will remain dummy */ 1255 } 1256 1257 mach_fixcpufreq(); 1258 1259 if (mach_ver[0] >= PSM_INFO_VER01_3) { 1260 if (preferred_mode == TIMER_ONESHOT) { 1261 1262 resolution = (*pops->psm_clkinit)(0); 1263 if (resolution != 0) { 1264 *set_mode = TIMER_ONESHOT; 1265 return (resolution); 1266 } 1267 } 1268 1269 /* 1270 * either periodic mode was requested or could not set to 1271 * one-shot mode 1272 */ 1273 resolution = (*pops->psm_clkinit)(hz); 1274 /* 1275 * psm should be able to do periodic, so we do not check 1276 * for return value of psm_clkinit here. 1277 */ 1278 *set_mode = TIMER_PERIODIC; 1279 return (resolution); 1280 } else { 1281 /* 1282 * PSMI interface prior to PSMI_3 does not define a return 1283 * value for psm_clkinit, so the return value is ignored. 1284 */ 1285 (void) (*pops->psm_clkinit)(hz); 1286 *set_mode = TIMER_PERIODIC; 1287 return (nsec_per_tick); 1288 } 1289 } 1290 1291 1292 /*ARGSUSED*/ 1293 static int 1294 mach_softlvl_to_vect(int ipl) 1295 { 1296 setsoftint = av_set_softint_pending; 1297 kdisetsoftint = kdi_av_set_softint_pending; 1298 1299 return (PSM_SV_SOFTWARE); 1300 } 1301 1302 #ifdef DEBUG 1303 /* 1304 * This is here to allow us to simulate cpus that refuse to start. 1305 */ 1306 cpuset_t cpufailset; 1307 #endif 1308 1309 int 1310 mach_cpu_start(struct cpu *cp, void *ctx) 1311 { 1312 struct psm_ops *pops = mach_set[0]; 1313 processorid_t id = cp->cpu_id; 1314 1315 #ifdef DEBUG 1316 if (CPU_IN_SET(cpufailset, id)) 1317 return (0); 1318 #endif 1319 return ((*pops->psm_cpu_start)(id, ctx)); 1320 } 1321 1322 int 1323 mach_cpuid_start(processorid_t id, void *ctx) 1324 { 1325 struct psm_ops *pops = mach_set[0]; 1326 1327 #ifdef DEBUG 1328 if (CPU_IN_SET(cpufailset, id)) 1329 return (0); 1330 #endif 1331 return ((*pops->psm_cpu_start)(id, ctx)); 1332 } 1333 1334 /*ARGSUSED*/ 1335 static int 1336 mach_translate_irq(dev_info_t *dip, int irqno) 1337 { 1338 return (irqno); /* default to NO translation */ 1339 } 1340 1341 static void 1342 mach_notify_error(int level, char *errmsg) 1343 { 1344 /* 1345 * SL_FATAL is pass in once panicstr is set, deliver it 1346 * as CE_PANIC. Also, translate SL_ codes back to CE_ 1347 * codes for the psmi handler 1348 */ 1349 if (level & SL_FATAL) 1350 (*notify_error)(CE_PANIC, errmsg); 1351 else if (level & SL_WARN) 1352 (*notify_error)(CE_WARN, errmsg); 1353 else if (level & SL_NOTE) 1354 (*notify_error)(CE_NOTE, errmsg); 1355 else if (level & SL_CONSOLE) 1356 (*notify_error)(CE_CONT, errmsg); 1357 } 1358 1359 /* 1360 * It provides the default basic intr_ops interface for the new DDI 1361 * interrupt framework if the PSM doesn't have one. 1362 * 1363 * Input: 1364 * dip - pointer to the dev_info structure of the requested device 1365 * hdlp - pointer to the internal interrupt handle structure for the 1366 * requested interrupt 1367 * intr_op - opcode for this call 1368 * result - pointer to the integer that will hold the result to be 1369 * passed back if return value is PSM_SUCCESS 1370 * 1371 * Output: 1372 * return value is either PSM_SUCCESS or PSM_FAILURE 1373 */ 1374 static int 1375 mach_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 1376 psm_intr_op_t intr_op, int *result) 1377 { 1378 struct intrspec *ispec; 1379 1380 switch (intr_op) { 1381 case PSM_INTR_OP_CHECK_MSI: 1382 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI | 1383 DDI_INTR_TYPE_MSIX); 1384 break; 1385 case PSM_INTR_OP_ALLOC_VECTORS: 1386 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 1387 *result = 1; 1388 else 1389 *result = 0; 1390 break; 1391 case PSM_INTR_OP_FREE_VECTORS: 1392 break; 1393 case PSM_INTR_OP_NAVAIL_VECTORS: 1394 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 1395 *result = 1; 1396 else 1397 *result = 0; 1398 break; 1399 case PSM_INTR_OP_XLATE_VECTOR: 1400 ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp; 1401 *result = psm_translate_irq(dip, ispec->intrspec_vec); 1402 break; 1403 case PSM_INTR_OP_GET_CAP: 1404 *result = 0; 1405 break; 1406 case PSM_INTR_OP_GET_PENDING: 1407 case PSM_INTR_OP_CLEAR_MASK: 1408 case PSM_INTR_OP_SET_MASK: 1409 case PSM_INTR_OP_GET_SHARED: 1410 case PSM_INTR_OP_SET_PRI: 1411 case PSM_INTR_OP_SET_CAP: 1412 case PSM_INTR_OP_SET_CPU: 1413 case PSM_INTR_OP_GET_INTR: 1414 default: 1415 return (PSM_FAILURE); 1416 } 1417 return (PSM_SUCCESS); 1418 } 1419 /* 1420 * Return 1 if CMT load balancing policies should be 1421 * implemented across instances of the specified hardware 1422 * sharing relationship. 1423 */ 1424 int 1425 pg_cmt_load_bal_hw(pghw_type_t hw) 1426 { 1427 if (hw == PGHW_IPIPE || 1428 hw == PGHW_FPU || 1429 hw == PGHW_CHIP) 1430 return (1); 1431 else 1432 return (0); 1433 } 1434 /* 1435 * Return 1 if thread affinity polices should be implemented 1436 * for instances of the specifed hardware sharing relationship. 1437 */ 1438 int 1439 pg_cmt_affinity_hw(pghw_type_t hw) 1440 { 1441 if (hw == PGHW_CACHE) 1442 return (1); 1443 else 1444 return (0); 1445 } 1446