1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/sysmacros.h> 28 #include <sys/disp.h> 29 #include <sys/promif.h> 30 #include <sys/clock.h> 31 #include <sys/cpuvar.h> 32 #include <sys/stack.h> 33 #include <vm/as.h> 34 #include <vm/hat.h> 35 #include <sys/reboot.h> 36 #include <sys/avintr.h> 37 #include <sys/vtrace.h> 38 #include <sys/proc.h> 39 #include <sys/thread.h> 40 #include <sys/cpupart.h> 41 #include <sys/pset.h> 42 #include <sys/copyops.h> 43 #include <sys/pg.h> 44 #include <sys/disp.h> 45 #include <sys/debug.h> 46 #include <sys/sunddi.h> 47 #include <sys/x86_archext.h> 48 #include <sys/privregs.h> 49 #include <sys/machsystm.h> 50 #include <sys/ontrap.h> 51 #include <sys/bootconf.h> 52 #include <sys/kdi_machimpl.h> 53 #include <sys/archsystm.h> 54 #include <sys/promif.h> 55 #include <sys/bootconf.h> 56 #include <sys/pci_cfgspace.h> 57 #ifdef __xpv 58 #include <sys/hypervisor.h> 59 #endif 60 61 /* 62 * some globals for patching the result of cpuid 63 * to solve problems w/ creative cpu vendors 64 */ 65 66 extern uint32_t cpuid_feature_ecx_include; 67 extern uint32_t cpuid_feature_ecx_exclude; 68 extern uint32_t cpuid_feature_edx_include; 69 extern uint32_t cpuid_feature_edx_exclude; 70 71 /* 72 * Dummy spl priority masks 73 */ 74 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 75 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 76 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 77 }; 78 79 80 /* 81 * Setup routine called right before main(). Interposing this function 82 * before main() allows us to call it in a machine-independent fashion. 83 */ 84 void 85 mlsetup(struct regs *rp) 86 { 87 u_longlong_t prop_value; 88 extern struct classfuncs sys_classfuncs; 89 extern disp_t cpu0_disp; 90 extern char t0stack[]; 91 92 ASSERT_STACK_ALIGNED(); 93 94 /* 95 * initialize cpu_self 96 */ 97 cpu[0]->cpu_self = cpu[0]; 98 99 #if defined(__xpv) 100 /* 101 * Point at the hypervisor's virtual cpu structure 102 */ 103 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 104 #endif 105 106 /* 107 * Set up dummy cpu_pri_data values till psm spl code is 108 * installed. This allows splx() to work on amd64. 109 */ 110 111 cpu[0]->cpu_pri_data = dummy_cpu_pri; 112 113 /* 114 * check if we've got special bits to clear or set 115 * when checking cpu features 116 */ 117 118 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 119 cpuid_feature_ecx_include = 0; 120 else 121 cpuid_feature_ecx_include = (uint32_t)prop_value; 122 123 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 124 cpuid_feature_ecx_exclude = 0; 125 else 126 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 127 128 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 129 cpuid_feature_edx_include = 0; 130 else 131 cpuid_feature_edx_include = (uint32_t)prop_value; 132 133 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 134 cpuid_feature_edx_exclude = 0; 135 else 136 cpuid_feature_edx_exclude = (uint32_t)prop_value; 137 138 /* 139 * The first lightweight pass (pass0) through the cpuid data 140 * was done in locore before mlsetup was called. Do the next 141 * pass in C code. 142 * 143 * The x86_feature bits are set here on the basis of the capabilities 144 * of the boot CPU. Note that if we choose to support CPUs that have 145 * different feature sets (at which point we would almost certainly 146 * want to set the feature bits to correspond to the feature 147 * minimum) this value may be altered. 148 */ 149 x86_feature = cpuid_pass1(cpu[0]); 150 151 /* 152 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 153 */ 154 init_desctbls(); 155 156 #if !defined(__xpv) 157 158 /* 159 * Patch the tsc_read routine with appropriate set of instructions, 160 * depending on the processor family and architecure, to read the 161 * time-stamp counter while ensuring no out-of-order execution. 162 * Patch it while the kernel text is still writable. 163 * 164 * Note: tsc_read is not patched for intel processors whose family 165 * is >6 and for amd whose family >f (in case they don't support rdtscp 166 * instruction, unlikely). By default tsc_read will use cpuid for 167 * serialization in such cases. The following code needs to be 168 * revisited if intel processors of family >= f retains the 169 * instruction serialization nature of mfence instruction. 170 * Note: tsc_read is not patched for x86 processors which do 171 * not support "mfence". By default tsc_read will use cpuid for 172 * serialization in such cases. 173 * 174 * The Xen hypervisor does not correctly report whether rdtscp is 175 * supported or not, so we must assume that it is not. 176 */ 177 if (get_hwenv() != HW_XEN_HVM && (x86_feature & X86_TSCP)) 178 patch_tsc_read(X86_HAVE_TSCP); 179 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 180 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 181 patch_tsc_read(X86_TSC_MFENCE); 182 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 183 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 184 patch_tsc_read(X86_TSC_LFENCE); 185 186 #endif /* !__xpv */ 187 188 #if defined(__i386) && !defined(__xpv) 189 /* 190 * Some i386 processors do not implement the rdtsc instruction, 191 * or at least they do not implement it correctly. Patch them to 192 * return 0. 193 */ 194 if ((x86_feature & X86_TSC) == 0) 195 patch_tsc_read(X86_NO_TSC); 196 #endif /* __i386 && !__xpv */ 197 198 #if defined(__amd64) && !defined(__xpv) 199 patch_memops(cpuid_getvendor(CPU)); 200 #endif /* __amd64 && !__xpv */ 201 202 #if !defined(__xpv) 203 /* XXPV what, if anything, should be dorked with here under xen? */ 204 205 /* 206 * While we're thinking about the TSC, let's set up %cr4 so that 207 * userland can issue rdtsc, and initialize the TSC_AUX value 208 * (the cpuid) for the rdtscp instruction on appropriately 209 * capable hardware. 210 */ 211 if (x86_feature & X86_TSC) 212 setcr4(getcr4() & ~CR4_TSD); 213 214 if (x86_feature & X86_TSCP) 215 (void) wrmsr(MSR_AMD_TSCAUX, 0); 216 217 if (x86_feature & X86_DE) 218 setcr4(getcr4() | CR4_DE); 219 #endif /* __xpv */ 220 221 /* 222 * initialize t0 223 */ 224 t0.t_stk = (caddr_t)rp - MINFRAME; 225 t0.t_stkbase = t0stack; 226 t0.t_pri = maxclsyspri - 3; 227 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 228 t0.t_procp = &p0; 229 t0.t_plockp = &p0lock.pl_lock; 230 t0.t_lwp = &lwp0; 231 t0.t_forw = &t0; 232 t0.t_back = &t0; 233 t0.t_next = &t0; 234 t0.t_prev = &t0; 235 t0.t_cpu = cpu[0]; 236 t0.t_disp_queue = &cpu0_disp; 237 t0.t_bind_cpu = PBIND_NONE; 238 t0.t_bind_pset = PS_NONE; 239 t0.t_bindflag = (uchar_t)default_binding_mode; 240 t0.t_cpupart = &cp_default; 241 t0.t_clfuncs = &sys_classfuncs.thread; 242 t0.t_copyops = NULL; 243 THREAD_ONPROC(&t0, CPU); 244 245 lwp0.lwp_thread = &t0; 246 lwp0.lwp_regs = (void *)rp; 247 lwp0.lwp_procp = &p0; 248 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 249 250 p0.p_exec = NULL; 251 p0.p_stat = SRUN; 252 p0.p_flag = SSYS; 253 p0.p_tlist = &t0; 254 p0.p_stksize = 2*PAGESIZE; 255 p0.p_stkpageszc = 0; 256 p0.p_as = &kas; 257 p0.p_lockp = &p0lock; 258 p0.p_brkpageszc = 0; 259 p0.p_t1_lgrpid = LGRP_NONE; 260 p0.p_tr_lgrpid = LGRP_NONE; 261 sigorset(&p0.p_ignore, &ignoredefault); 262 263 CPU->cpu_thread = &t0; 264 bzero(&cpu0_disp, sizeof (disp_t)); 265 CPU->cpu_disp = &cpu0_disp; 266 CPU->cpu_disp->disp_cpu = CPU; 267 CPU->cpu_dispthread = &t0; 268 CPU->cpu_idle_thread = &t0; 269 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 270 CPU->cpu_dispatch_pri = t0.t_pri; 271 272 CPU->cpu_id = 0; 273 274 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 275 276 /* 277 * The kernel doesn't use LDTs unless a process explicitly requests one. 278 */ 279 p0.p_ldt_desc = null_sdesc; 280 281 /* 282 * Initialize thread/cpu microstate accounting 283 */ 284 init_mstate(&t0, LMS_SYSTEM); 285 init_cpu_mstate(CPU, CMS_SYSTEM); 286 287 /* 288 * Initialize lists of available and active CPUs. 289 */ 290 cpu_list_init(CPU); 291 292 pg_cpu_bootstrap(CPU); 293 294 /* 295 * Now that we have taken over the GDT, IDT and have initialized 296 * active CPU list it's time to inform kmdb if present. 297 */ 298 if (boothowto & RB_DEBUG) 299 kdi_idt_sync(); 300 301 /* 302 * If requested (boot -d) drop into kmdb. 303 * 304 * This must be done after cpu_list_init() on the 64-bit kernel 305 * since taking a trap requires that we re-compute gsbase based 306 * on the cpu list. 307 */ 308 if (boothowto & RB_DEBUGENTER) 309 kmdb_enter(); 310 311 cpu_vm_data_init(CPU); 312 313 /* lgrp_init() needs PCI config space access */ 314 #if defined(__xpv) 315 if (DOMAIN_IS_INITDOMAIN(xen_info)) 316 pci_cfgspace_init(); 317 #else 318 pci_cfgspace_init(); 319 #endif 320 321 rp->r_fp = 0; /* terminate kernel stack traces! */ 322 323 prom_init("kernel", (void *)NULL); 324 325 if (bootprop_getval("boot-ncpus", &prop_value) != 0) 326 boot_ncpus = NCPU; 327 else { 328 boot_ncpus = (int)prop_value; 329 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 330 boot_ncpus = NCPU; 331 } 332 333 max_ncpus = boot_max_ncpus = boot_ncpus; 334 335 /* 336 * Initialize the lgrp framework 337 */ 338 lgrp_init(); 339 340 if (boothowto & RB_HALT) { 341 prom_printf("unix: kernel halted by -h flag\n"); 342 prom_enter_mon(); 343 } 344 345 ASSERT_STACK_ALIGNED(); 346 347 /* 348 * Fill out cpu_ucode_info. Update microcode if necessary. 349 */ 350 ucode_check(CPU); 351 352 if (workaround_errata(CPU) != 0) 353 panic("critical workaround(s) missing for boot cpu"); 354 } 355 356 357 void 358 mach_modpath(char *path, const char *filename) 359 { 360 /* 361 * Construct the directory path from the filename. 362 */ 363 364 int len; 365 char *p; 366 const char isastr[] = "/amd64"; 367 size_t isalen = strlen(isastr); 368 369 if ((p = strrchr(filename, '/')) == NULL) 370 return; 371 372 while (p > filename && *(p - 1) == '/') 373 p--; /* remove trailing '/' characters */ 374 if (p == filename) 375 p++; /* so "/" -is- the modpath in this case */ 376 377 /* 378 * Remove optional isa-dependent directory name - the module 379 * subsystem will put this back again (!) 380 */ 381 len = p - filename; 382 if (len > isalen && 383 strncmp(&filename[len - isalen], isastr, isalen) == 0) 384 p -= isalen; 385 386 /* 387 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 388 */ 389 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 390 (void) strncpy(path, filename, p - filename); 391 } 392