1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2012 Gary Mills 23 * 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 25 * Copyright (c) 2011 by Delphix. All rights reserved. 26 */ 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/sysmacros.h> 34 #include <sys/disp.h> 35 #include <sys/promif.h> 36 #include <sys/clock.h> 37 #include <sys/cpuvar.h> 38 #include <sys/stack.h> 39 #include <vm/as.h> 40 #include <vm/hat.h> 41 #include <sys/reboot.h> 42 #include <sys/avintr.h> 43 #include <sys/vtrace.h> 44 #include <sys/proc.h> 45 #include <sys/thread.h> 46 #include <sys/cpupart.h> 47 #include <sys/pset.h> 48 #include <sys/copyops.h> 49 #include <sys/pg.h> 50 #include <sys/disp.h> 51 #include <sys/debug.h> 52 #include <sys/sunddi.h> 53 #include <sys/x86_archext.h> 54 #include <sys/privregs.h> 55 #include <sys/machsystm.h> 56 #include <sys/ontrap.h> 57 #include <sys/bootconf.h> 58 #include <sys/boot_console.h> 59 #include <sys/kdi_machimpl.h> 60 #include <sys/archsystm.h> 61 #include <sys/promif.h> 62 #include <sys/pci_cfgspace.h> 63 #ifdef __xpv 64 #include <sys/hypervisor.h> 65 #else 66 #include <sys/xpv_support.h> 67 #endif 68 69 /* 70 * some globals for patching the result of cpuid 71 * to solve problems w/ creative cpu vendors 72 */ 73 74 extern uint32_t cpuid_feature_ecx_include; 75 extern uint32_t cpuid_feature_ecx_exclude; 76 extern uint32_t cpuid_feature_edx_include; 77 extern uint32_t cpuid_feature_edx_exclude; 78 79 /* 80 * Dummy spl priority masks 81 */ 82 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 83 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 84 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 85 }; 86 87 /* 88 * Set console mode 89 */ 90 static void 91 set_console_mode(uint8_t val) 92 { 93 struct bop_regs rp = {0}; 94 95 rp.eax.byte.ah = 0x0; 96 rp.eax.byte.al = val; 97 rp.ebx.word.bx = 0x0; 98 99 BOP_DOINT(bootops, 0x10, &rp); 100 } 101 102 103 /* 104 * Setup routine called right before main(). Interposing this function 105 * before main() allows us to call it in a machine-independent fashion. 106 */ 107 void 108 mlsetup(struct regs *rp) 109 { 110 u_longlong_t prop_value; 111 extern struct classfuncs sys_classfuncs; 112 extern disp_t cpu0_disp; 113 extern char t0stack[]; 114 extern int post_fastreboot; 115 extern uint64_t plat_dr_options; 116 117 ASSERT_STACK_ALIGNED(); 118 119 /* 120 * initialize cpu_self 121 */ 122 cpu[0]->cpu_self = cpu[0]; 123 124 #if defined(__xpv) 125 /* 126 * Point at the hypervisor's virtual cpu structure 127 */ 128 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 129 #endif 130 131 /* 132 * Set up dummy cpu_pri_data values till psm spl code is 133 * installed. This allows splx() to work on amd64. 134 */ 135 136 cpu[0]->cpu_pri_data = dummy_cpu_pri; 137 138 /* 139 * check if we've got special bits to clear or set 140 * when checking cpu features 141 */ 142 143 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 144 cpuid_feature_ecx_include = 0; 145 else 146 cpuid_feature_ecx_include = (uint32_t)prop_value; 147 148 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 149 cpuid_feature_ecx_exclude = 0; 150 else 151 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 152 153 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 154 cpuid_feature_edx_include = 0; 155 else 156 cpuid_feature_edx_include = (uint32_t)prop_value; 157 158 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 159 cpuid_feature_edx_exclude = 0; 160 else 161 cpuid_feature_edx_exclude = (uint32_t)prop_value; 162 163 /* 164 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 165 */ 166 init_desctbls(); 167 168 /* 169 * lgrp_init() and possibly cpuid_pass1() need PCI config 170 * space access 171 */ 172 #if defined(__xpv) 173 if (DOMAIN_IS_INITDOMAIN(xen_info)) 174 pci_cfgspace_init(); 175 #else 176 pci_cfgspace_init(); 177 /* 178 * Initialize the platform type from CPU 0 to ensure that 179 * determine_platform() is only ever called once. 180 */ 181 determine_platform(); 182 #endif 183 184 /* 185 * The first lightweight pass (pass0) through the cpuid data 186 * was done in locore before mlsetup was called. Do the next 187 * pass in C code. 188 * 189 * The x86_featureset is initialized here based on the capabilities 190 * of the boot CPU. Note that if we choose to support CPUs that have 191 * different feature sets (at which point we would almost certainly 192 * want to set the feature bits to correspond to the feature 193 * minimum) this value may be altered. 194 */ 195 cpuid_pass1(cpu[0], x86_featureset); 196 197 #if !defined(__xpv) 198 199 if (get_hwenv() == HW_XEN_HVM) 200 xen_hvm_init(); 201 202 /* 203 * Patch the tsc_read routine with appropriate set of instructions, 204 * depending on the processor family and architecure, to read the 205 * time-stamp counter while ensuring no out-of-order execution. 206 * Patch it while the kernel text is still writable. 207 * 208 * Note: tsc_read is not patched for intel processors whose family 209 * is >6 and for amd whose family >f (in case they don't support rdtscp 210 * instruction, unlikely). By default tsc_read will use cpuid for 211 * serialization in such cases. The following code needs to be 212 * revisited if intel processors of family >= f retains the 213 * instruction serialization nature of mfence instruction. 214 * Note: tsc_read is not patched for x86 processors which do 215 * not support "mfence". By default tsc_read will use cpuid for 216 * serialization in such cases. 217 * 218 * The Xen hypervisor does not correctly report whether rdtscp is 219 * supported or not, so we must assume that it is not. 220 */ 221 if (get_hwenv() != HW_XEN_HVM && 222 is_x86_feature(x86_featureset, X86FSET_TSCP)) 223 patch_tsc_read(X86_HAVE_TSCP); 224 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 225 cpuid_getfamily(CPU) <= 0xf && 226 is_x86_feature(x86_featureset, X86FSET_SSE2)) 227 patch_tsc_read(X86_TSC_MFENCE); 228 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 229 cpuid_getfamily(CPU) <= 6 && 230 is_x86_feature(x86_featureset, X86FSET_SSE2)) 231 patch_tsc_read(X86_TSC_LFENCE); 232 233 #endif /* !__xpv */ 234 235 #if defined(__i386) && !defined(__xpv) 236 /* 237 * Some i386 processors do not implement the rdtsc instruction, 238 * or at least they do not implement it correctly. Patch them to 239 * return 0. 240 */ 241 if (!is_x86_feature(x86_featureset, X86FSET_TSC)) 242 patch_tsc_read(X86_NO_TSC); 243 #endif /* __i386 && !__xpv */ 244 245 #if defined(__amd64) && !defined(__xpv) 246 patch_memops(cpuid_getvendor(CPU)); 247 #endif /* __amd64 && !__xpv */ 248 249 #if !defined(__xpv) 250 /* XXPV what, if anything, should be dorked with here under xen? */ 251 252 /* 253 * While we're thinking about the TSC, let's set up %cr4 so that 254 * userland can issue rdtsc, and initialize the TSC_AUX value 255 * (the cpuid) for the rdtscp instruction on appropriately 256 * capable hardware. 257 */ 258 if (is_x86_feature(x86_featureset, X86FSET_TSC)) 259 setcr4(getcr4() & ~CR4_TSD); 260 261 if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 262 (void) wrmsr(MSR_AMD_TSCAUX, 0); 263 264 if (is_x86_feature(x86_featureset, X86FSET_DE)) 265 setcr4(getcr4() | CR4_DE); 266 #endif /* __xpv */ 267 268 /* 269 * initialize t0 270 */ 271 t0.t_stk = (caddr_t)rp - MINFRAME; 272 t0.t_stkbase = t0stack; 273 t0.t_pri = maxclsyspri - 3; 274 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 275 t0.t_procp = &p0; 276 t0.t_plockp = &p0lock.pl_lock; 277 t0.t_lwp = &lwp0; 278 t0.t_forw = &t0; 279 t0.t_back = &t0; 280 t0.t_next = &t0; 281 t0.t_prev = &t0; 282 t0.t_cpu = cpu[0]; 283 t0.t_disp_queue = &cpu0_disp; 284 t0.t_bind_cpu = PBIND_NONE; 285 t0.t_bind_pset = PS_NONE; 286 t0.t_bindflag = (uchar_t)default_binding_mode; 287 t0.t_cpupart = &cp_default; 288 t0.t_clfuncs = &sys_classfuncs.thread; 289 t0.t_copyops = NULL; 290 THREAD_ONPROC(&t0, CPU); 291 292 lwp0.lwp_thread = &t0; 293 lwp0.lwp_regs = (void *)rp; 294 lwp0.lwp_procp = &p0; 295 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 296 297 p0.p_exec = NULL; 298 p0.p_stat = SRUN; 299 p0.p_flag = SSYS; 300 p0.p_tlist = &t0; 301 p0.p_stksize = 2*PAGESIZE; 302 p0.p_stkpageszc = 0; 303 p0.p_as = &kas; 304 p0.p_lockp = &p0lock; 305 p0.p_brkpageszc = 0; 306 p0.p_t1_lgrpid = LGRP_NONE; 307 p0.p_tr_lgrpid = LGRP_NONE; 308 sigorset(&p0.p_ignore, &ignoredefault); 309 310 CPU->cpu_thread = &t0; 311 bzero(&cpu0_disp, sizeof (disp_t)); 312 CPU->cpu_disp = &cpu0_disp; 313 CPU->cpu_disp->disp_cpu = CPU; 314 CPU->cpu_dispthread = &t0; 315 CPU->cpu_idle_thread = &t0; 316 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 317 CPU->cpu_dispatch_pri = t0.t_pri; 318 319 CPU->cpu_id = 0; 320 321 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 322 323 /* 324 * The kernel doesn't use LDTs unless a process explicitly requests one. 325 */ 326 p0.p_ldt_desc = null_sdesc; 327 328 /* 329 * Initialize thread/cpu microstate accounting 330 */ 331 init_mstate(&t0, LMS_SYSTEM); 332 init_cpu_mstate(CPU, CMS_SYSTEM); 333 334 /* 335 * Initialize lists of available and active CPUs. 336 */ 337 cpu_list_init(CPU); 338 339 pg_cpu_bootstrap(CPU); 340 341 /* 342 * Now that we have taken over the GDT, IDT and have initialized 343 * active CPU list it's time to inform kmdb if present. 344 */ 345 if (boothowto & RB_DEBUG) 346 kdi_idt_sync(); 347 348 /* 349 * Explicitly set console to text mode (0x3) if this is a boot 350 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT. 351 */ 352 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT) 353 set_console_mode(0x3); 354 355 /* 356 * If requested (boot -d) drop into kmdb. 357 * 358 * This must be done after cpu_list_init() on the 64-bit kernel 359 * since taking a trap requires that we re-compute gsbase based 360 * on the cpu list. 361 */ 362 if (boothowto & RB_DEBUGENTER) 363 kmdb_enter(); 364 365 cpu_vm_data_init(CPU); 366 367 rp->r_fp = 0; /* terminate kernel stack traces! */ 368 369 prom_init("kernel", (void *)NULL); 370 371 /* User-set option overrides firmware value. */ 372 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 373 plat_dr_options = (uint64_t)prop_value; 374 } 375 #if defined(__xpv) 376 /* No support of DR operations on xpv */ 377 plat_dr_options = 0; 378 #else /* __xpv */ 379 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 380 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 381 #ifndef __amd64 382 /* Only enable CPU/memory DR on 64 bits kernel. */ 383 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY; 384 plat_dr_options &= ~PLAT_DR_FEATURE_CPU; 385 #endif /* __amd64 */ 386 #endif /* __xpv */ 387 388 /* 389 * Get value of "plat_dr_physmax" boot option. 390 * It overrides values calculated from MSCT or SRAT table. 391 */ 392 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 393 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 394 } 395 396 /* Get value of boot_ncpus. */ 397 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 398 boot_ncpus = NCPU; 399 } else { 400 boot_ncpus = (int)prop_value; 401 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 402 boot_ncpus = NCPU; 403 } 404 405 /* 406 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 407 * support CPU DR operations. 408 */ 409 if (plat_dr_support_cpu() == 0) { 410 max_ncpus = boot_max_ncpus = boot_ncpus; 411 } else { 412 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 413 max_ncpus = NCPU; 414 } else { 415 max_ncpus = (int)prop_value; 416 if (max_ncpus <= 0 || max_ncpus > NCPU) { 417 max_ncpus = NCPU; 418 } 419 if (boot_ncpus > max_ncpus) { 420 boot_ncpus = max_ncpus; 421 } 422 } 423 424 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 425 boot_max_ncpus = boot_ncpus; 426 } else { 427 boot_max_ncpus = (int)prop_value; 428 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 429 boot_max_ncpus = boot_ncpus; 430 } else if (boot_max_ncpus > max_ncpus) { 431 boot_max_ncpus = max_ncpus; 432 } 433 } 434 } 435 436 /* 437 * Initialize the lgrp framework 438 */ 439 lgrp_init(LGRP_INIT_STAGE1); 440 441 if (boothowto & RB_HALT) { 442 prom_printf("unix: kernel halted by -h flag\n"); 443 prom_enter_mon(); 444 } 445 446 ASSERT_STACK_ALIGNED(); 447 448 /* 449 * Fill out cpu_ucode_info. Update microcode if necessary. 450 */ 451 ucode_check(CPU); 452 453 if (workaround_errata(CPU) != 0) 454 panic("critical workaround(s) missing for boot cpu"); 455 } 456 457 458 void 459 mach_modpath(char *path, const char *filename) 460 { 461 /* 462 * Construct the directory path from the filename. 463 */ 464 465 int len; 466 char *p; 467 const char isastr[] = "/amd64"; 468 size_t isalen = strlen(isastr); 469 470 if ((p = strrchr(filename, '/')) == NULL) 471 return; 472 473 while (p > filename && *(p - 1) == '/') 474 p--; /* remove trailing '/' characters */ 475 if (p == filename) 476 p++; /* so "/" -is- the modpath in this case */ 477 478 /* 479 * Remove optional isa-dependent directory name - the module 480 * subsystem will put this back again (!) 481 */ 482 len = p - filename; 483 if (len > isalen && 484 strncmp(&filename[len - isalen], isastr, isalen) == 0) 485 p -= isalen; 486 487 /* 488 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 489 */ 490 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 491 (void) strncpy(path, filename, p - filename); 492 } 493