1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/chip.h> 44 #include <sys/fp.h> 45 #include <sys/controlregs.h> 46 #include <sys/auxv_386.h> 47 #include <sys/bitmap.h> 48 #include <sys/controlregs.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 ulong_t cr4_value; 108 uint_t pentiumpro_bug4046376; 109 uint_t pentiumpro_bug4064495; 110 111 uint_t enable486; 112 113 /* 114 * This set of strings are for processors rumored to support the cpuid 115 * instruction, and is used by locore.s to figure out how to set x86_vendor 116 */ 117 const char CyrixInstead[] = "CyrixInstead"; 118 119 /* 120 * These constants determine how many of the elements of the 121 * cpuid we cache in the cpuid_info data structure; the 122 * remaining elements are accessible via the cpuid instruction. 123 */ 124 125 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 126 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 127 128 struct cpuid_info { 129 uint_t cpi_pass; /* last pass completed */ 130 /* 131 * standard function information 132 */ 133 uint_t cpi_maxeax; /* fn 0: %eax */ 134 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 135 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 136 137 uint_t cpi_family; /* fn 1: extended family */ 138 uint_t cpi_model; /* fn 1: extended model */ 139 uint_t cpi_step; /* fn 1: stepping */ 140 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 141 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 142 int cpi_clogid; /* fn 1: %ebx: thread # */ 143 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 144 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 145 uint_t cpi_ncache; /* fn 2: number of elements */ 146 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 147 /* 148 * extended function information 149 */ 150 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 151 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 152 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 153 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 154 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 155 id_t cpi_coreid; 156 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 157 /* Intel: fn 4: %eax[31-26] */ 158 /* 159 * supported feature information 160 */ 161 uint32_t cpi_support[4]; 162 #define STD_EDX_FEATURES 0 163 #define AMD_EDX_FEATURES 1 164 #define TM_EDX_FEATURES 2 165 #define STD_ECX_FEATURES 3 166 167 }; 168 169 170 static struct cpuid_info cpuid_info0; 171 172 /* 173 * These bit fields are defined by the Intel Application Note AP-485 174 * "Intel Processor Identification and the CPUID Instruction" 175 */ 176 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 177 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 178 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 179 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 180 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 181 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 182 183 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 184 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 185 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 186 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 187 188 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 189 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 190 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 191 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 192 193 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 194 #define CPI_XMAXEAX_MAX 0x80000100 195 196 /* 197 * Some undocumented ways of patching the results of the cpuid 198 * instruction to permit running Solaris 10 on future cpus that 199 * we don't currently support. Could be set to non-zero values 200 * via settings in eeprom. 201 */ 202 203 uint32_t cpuid_feature_ecx_include; 204 uint32_t cpuid_feature_ecx_exclude; 205 uint32_t cpuid_feature_edx_include; 206 uint32_t cpuid_feature_edx_exclude; 207 208 uint_t 209 cpuid_pass1(cpu_t *cpu) 210 { 211 uint32_t mask_ecx, mask_edx; 212 uint_t feature = X86_CPUID; 213 struct cpuid_info *cpi; 214 struct cpuid_regs *cp; 215 int xcpuid; 216 217 /* 218 * By convention, cpu0 is the boot cpu, which is called 219 * before memory allocation is available. Other cpus are 220 * initialized when memory becomes available. 221 */ 222 if (cpu->cpu_id == 0) 223 cpu->cpu_m.mcpu_cpi = cpi = &cpuid_info0; 224 else 225 cpu->cpu_m.mcpu_cpi = cpi = 226 kmem_zalloc(sizeof (*cpi), KM_SLEEP); 227 228 cp = &cpi->cpi_std[0]; 229 cp->cp_eax = 0; 230 cpi->cpi_maxeax = __cpuid_insn(cp); 231 { 232 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 233 *iptr++ = cp->cp_ebx; 234 *iptr++ = cp->cp_edx; 235 *iptr++ = cp->cp_ecx; 236 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 237 } 238 239 /* 240 * Map the vendor string to a type code 241 */ 242 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 243 cpi->cpi_vendor = X86_VENDOR_Intel; 244 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 245 cpi->cpi_vendor = X86_VENDOR_AMD; 246 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 247 cpi->cpi_vendor = X86_VENDOR_TM; 248 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 249 /* 250 * CyrixInstead is a variable used by the Cyrix detection code 251 * in locore. 252 */ 253 cpi->cpi_vendor = X86_VENDOR_Cyrix; 254 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 255 cpi->cpi_vendor = X86_VENDOR_UMC; 256 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 257 cpi->cpi_vendor = X86_VENDOR_NexGen; 258 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 259 cpi->cpi_vendor = X86_VENDOR_Centaur; 260 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 261 cpi->cpi_vendor = X86_VENDOR_Rise; 262 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 263 cpi->cpi_vendor = X86_VENDOR_SiS; 264 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 265 cpi->cpi_vendor = X86_VENDOR_NSC; 266 else 267 cpi->cpi_vendor = X86_VENDOR_IntelClone; 268 269 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 270 271 /* 272 * Limit the range in case of weird hardware 273 */ 274 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 275 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 276 if (cpi->cpi_maxeax < 1) 277 goto pass1_done; 278 279 cp = &cpi->cpi_std[1]; 280 cp->cp_eax = 1; 281 (void) __cpuid_insn(cp); 282 283 /* 284 * Extract identifying constants for easy access. 285 */ 286 cpi->cpi_model = CPI_MODEL(cpi); 287 cpi->cpi_family = CPI_FAMILY(cpi); 288 289 if (cpi->cpi_family == 0xf) { 290 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 291 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 292 } 293 294 cpi->cpi_step = CPI_STEP(cpi); 295 cpi->cpi_brandid = CPI_BRANDID(cpi); 296 297 /* 298 * *default* assumptions: 299 * - believe %edx feature word 300 * - ignore %ecx feature word 301 * - 32-bit virtual and physical addressing 302 */ 303 mask_edx = 0xffffffff; 304 mask_ecx = 0; 305 306 cpi->cpi_pabits = cpi->cpi_vabits = 32; 307 308 switch (cpi->cpi_vendor) { 309 case X86_VENDOR_Intel: 310 if (cpi->cpi_family == 5) 311 x86_type = X86_TYPE_P5; 312 else if (cpi->cpi_family == 6) { 313 x86_type = X86_TYPE_P6; 314 pentiumpro_bug4046376 = 1; 315 pentiumpro_bug4064495 = 1; 316 /* 317 * Clear the SEP bit when it was set erroneously 318 */ 319 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 320 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 321 } else if (cpi->cpi_family == 0xf) { 322 x86_type = X86_TYPE_P4; 323 /* 324 * We don't currently depend on any of the %ecx 325 * features until Prescott, so we'll only check 326 * this from P4 onwards. We might want to revisit 327 * that idea later. 328 */ 329 mask_ecx = 0xffffffff; 330 } else if (cpi->cpi_family > 0xf) 331 mask_ecx = 0xffffffff; 332 break; 333 case X86_VENDOR_IntelClone: 334 default: 335 break; 336 case X86_VENDOR_AMD: 337 #if defined(OPTERON_ERRATUM_108) 338 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 339 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 340 cpi->cpi_model = 0xc; 341 } else 342 #endif 343 if (cpi->cpi_family == 5) { 344 /* 345 * AMD K5 and K6 346 * 347 * These CPUs have an incomplete implementation 348 * of MCA/MCE which we mask away. 349 */ 350 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 351 352 /* 353 * Model 0 uses the wrong (APIC) bit 354 * to indicate PGE. Fix it here. 355 */ 356 if (cpi->cpi_model == 0) { 357 if (cp->cp_edx & 0x200) { 358 cp->cp_edx &= ~0x200; 359 cp->cp_edx |= CPUID_INTC_EDX_PGE; 360 } 361 } 362 363 /* 364 * Early models had problems w/ MMX; disable. 365 */ 366 if (cpi->cpi_model < 6) 367 mask_edx &= ~CPUID_INTC_EDX_MMX; 368 } 369 370 /* 371 * For newer families, SSE3 and CX16, at least, are valid; 372 * enable all 373 */ 374 if (cpi->cpi_family >= 0xf) 375 mask_ecx = 0xffffffff; 376 break; 377 case X86_VENDOR_TM: 378 /* 379 * workaround the NT workaround in CMS 4.1 380 */ 381 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 382 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 383 cp->cp_edx |= CPUID_INTC_EDX_CX8; 384 break; 385 case X86_VENDOR_Centaur: 386 /* 387 * workaround the NT workarounds again 388 */ 389 if (cpi->cpi_family == 6) 390 cp->cp_edx |= CPUID_INTC_EDX_CX8; 391 break; 392 case X86_VENDOR_Cyrix: 393 /* 394 * We rely heavily on the probing in locore 395 * to actually figure out what parts, if any, 396 * of the Cyrix cpuid instruction to believe. 397 */ 398 switch (x86_type) { 399 case X86_TYPE_CYRIX_486: 400 mask_edx = 0; 401 break; 402 case X86_TYPE_CYRIX_6x86: 403 mask_edx = 0; 404 break; 405 case X86_TYPE_CYRIX_6x86L: 406 mask_edx = 407 CPUID_INTC_EDX_DE | 408 CPUID_INTC_EDX_CX8; 409 break; 410 case X86_TYPE_CYRIX_6x86MX: 411 mask_edx = 412 CPUID_INTC_EDX_DE | 413 CPUID_INTC_EDX_MSR | 414 CPUID_INTC_EDX_CX8 | 415 CPUID_INTC_EDX_PGE | 416 CPUID_INTC_EDX_CMOV | 417 CPUID_INTC_EDX_MMX; 418 break; 419 case X86_TYPE_CYRIX_GXm: 420 mask_edx = 421 CPUID_INTC_EDX_MSR | 422 CPUID_INTC_EDX_CX8 | 423 CPUID_INTC_EDX_CMOV | 424 CPUID_INTC_EDX_MMX; 425 break; 426 case X86_TYPE_CYRIX_MediaGX: 427 break; 428 case X86_TYPE_CYRIX_MII: 429 case X86_TYPE_VIA_CYRIX_III: 430 mask_edx = 431 CPUID_INTC_EDX_DE | 432 CPUID_INTC_EDX_TSC | 433 CPUID_INTC_EDX_MSR | 434 CPUID_INTC_EDX_CX8 | 435 CPUID_INTC_EDX_PGE | 436 CPUID_INTC_EDX_CMOV | 437 CPUID_INTC_EDX_MMX; 438 break; 439 default: 440 break; 441 } 442 break; 443 } 444 445 /* 446 * Now we've figured out the masks that determine 447 * which bits we choose to believe, apply the masks 448 * to the feature words, then map the kernel's view 449 * of these feature words into its feature word. 450 */ 451 cp->cp_edx &= mask_edx; 452 cp->cp_ecx &= mask_ecx; 453 454 /* 455 * fold in fix ups 456 */ 457 458 cp->cp_edx |= cpuid_feature_edx_include; 459 cp->cp_edx &= ~cpuid_feature_edx_exclude; 460 461 462 cp->cp_ecx |= cpuid_feature_ecx_include; 463 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 464 465 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 466 feature |= X86_LARGEPAGE; 467 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 468 feature |= X86_TSC; 469 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 470 feature |= X86_MSR; 471 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 472 feature |= X86_MTRR; 473 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 474 feature |= X86_PGE; 475 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 476 feature |= X86_CMOV; 477 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 478 feature |= X86_MMX; 479 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 480 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 481 feature |= X86_MCA; 482 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 483 feature |= X86_PAE; 484 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 485 feature |= X86_CX8; 486 /* 487 * Once this bit was thought questionable, but it looks like it's 488 * back, as of Application Note 485 March 2005 (24161829.pdf) 489 */ 490 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 491 feature |= X86_CX16; 492 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 493 feature |= X86_PAT; 494 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 495 feature |= X86_SEP; 496 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 497 /* 498 * In our implementation, fxsave/fxrstor 499 * are prerequisites before we'll even 500 * try and do SSE things. 501 */ 502 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 503 feature |= X86_SSE; 504 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 505 feature |= X86_SSE2; 506 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 507 feature |= X86_SSE3; 508 } 509 if (cp->cp_edx & CPUID_INTC_EDX_DE) 510 cr4_value |= CR4_DE; 511 512 if (feature & X86_PAE) 513 cpi->cpi_pabits = 36; 514 515 /* 516 * Hyperthreading configuration is slightly tricky on Intel 517 * and pure clones, and even trickier on AMD. 518 * 519 * (AMD chose to set the HTT bit on their CMP processors, 520 * even though they're not actually hyperthreaded. Thus it 521 * takes a bit more work to figure out what's really going 522 * on ... see the handling of the CMP_LEGACY bit below) 523 */ 524 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 525 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 526 if (cpi->cpi_ncpu_per_chip > 1) 527 feature |= X86_HTT; 528 } else { 529 cpi->cpi_ncpu_per_chip = 1; 530 } 531 532 /* 533 * Work on the "extended" feature information, doing 534 * some basic initialization for cpuid_pass2() 535 */ 536 xcpuid = 0; 537 switch (cpi->cpi_vendor) { 538 case X86_VENDOR_Intel: 539 if (cpi->cpi_family >= 0xf) 540 xcpuid++; 541 break; 542 case X86_VENDOR_AMD: 543 if (cpi->cpi_family > 5 || 544 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 545 xcpuid++; 546 break; 547 case X86_VENDOR_Cyrix: 548 /* 549 * Only these Cyrix CPUs are -known- to support 550 * extended cpuid operations. 551 */ 552 if (x86_type == X86_TYPE_VIA_CYRIX_III || 553 x86_type == X86_TYPE_CYRIX_GXm) 554 xcpuid++; 555 break; 556 case X86_VENDOR_Centaur: 557 case X86_VENDOR_TM: 558 default: 559 xcpuid++; 560 break; 561 } 562 563 if (xcpuid) { 564 cp = &cpi->cpi_extd[0]; 565 cp->cp_eax = 0x80000000; 566 cpi->cpi_xmaxeax = __cpuid_insn(cp); 567 } 568 569 if (cpi->cpi_xmaxeax & 0x80000000) { 570 571 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 572 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 573 574 switch (cpi->cpi_vendor) { 575 case X86_VENDOR_Intel: 576 case X86_VENDOR_AMD: 577 if (cpi->cpi_xmaxeax < 0x80000001) 578 break; 579 cp = &cpi->cpi_extd[1]; 580 cp->cp_eax = 0x80000001; 581 (void) __cpuid_insn(cp); 582 if (cpi->cpi_vendor == X86_VENDOR_AMD && 583 cpi->cpi_family == 5 && 584 cpi->cpi_model == 6 && 585 cpi->cpi_step == 6) { 586 /* 587 * K6 model 6 uses bit 10 to indicate SYSC 588 * Later models use bit 11. Fix it here. 589 */ 590 if (cp->cp_edx & 0x400) { 591 cp->cp_edx &= ~0x400; 592 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 593 } 594 } 595 596 /* 597 * Compute the additions to the kernel's feature word. 598 */ 599 if (cp->cp_edx & CPUID_AMD_EDX_NX) 600 feature |= X86_NX; 601 602 /* 603 * If both the HTT and CMP_LEGACY bits are set, 604 * then we're not actually HyperThreaded. Read 605 * "AMD CPUID Specification" for more details. 606 */ 607 if (cpi->cpi_vendor == X86_VENDOR_AMD && 608 (feature & X86_HTT) && 609 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LEGACY)) { 610 feature &= ~X86_HTT; 611 feature |= X86_CMP; 612 } 613 #if defined(_LP64) 614 /* 615 * It's really tricky to support syscall/sysret in 616 * the i386 kernel; we rely on sysenter/sysexit 617 * instead. In the amd64 kernel, things are -way- 618 * better. 619 */ 620 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 621 feature |= X86_ASYSC; 622 623 /* 624 * While we're thinking about system calls, note 625 * that AMD processors don't support sysenter 626 * in long mode at all, so don't try to program them. 627 */ 628 if (x86_vendor == X86_VENDOR_AMD) 629 feature &= ~X86_SEP; 630 #endif 631 break; 632 default: 633 break; 634 } 635 636 /* 637 * Get CPUID data about processor cores and hyperthreads. 638 */ 639 switch (cpi->cpi_vendor) { 640 case X86_VENDOR_Intel: 641 if (cpi->cpi_maxeax >= 4) { 642 cp = &cpi->cpi_std[4]; 643 cp->cp_eax = 4; 644 cp->cp_ecx = 0; 645 (void) __cpuid_insn(cp); 646 } 647 /*FALLTHROUGH*/ 648 case X86_VENDOR_AMD: 649 if (cpi->cpi_xmaxeax < 0x80000008) 650 break; 651 cp = &cpi->cpi_extd[8]; 652 cp->cp_eax = 0x80000008; 653 (void) __cpuid_insn(cp); 654 /* 655 * Virtual and physical address limits from 656 * cpuid override previously guessed values. 657 */ 658 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 659 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 660 break; 661 default: 662 break; 663 } 664 665 switch (cpi->cpi_vendor) { 666 case X86_VENDOR_Intel: 667 if (cpi->cpi_maxeax < 4) { 668 cpi->cpi_ncore_per_chip = 1; 669 break; 670 } else { 671 cpi->cpi_ncore_per_chip = 672 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 673 } 674 break; 675 case X86_VENDOR_AMD: 676 if (cpi->cpi_xmaxeax < 0x80000008) { 677 cpi->cpi_ncore_per_chip = 1; 678 break; 679 } else { 680 cpi->cpi_ncore_per_chip = 681 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 682 } 683 break; 684 default: 685 cpi->cpi_ncore_per_chip = 1; 686 break; 687 } 688 689 } 690 691 /* 692 * If more than one core, then this processor is CMP. 693 */ 694 if (cpi->cpi_ncore_per_chip > 1) 695 feature |= X86_CMP; 696 /* 697 * If the number of cores is the same as the number 698 * of CPUs, then we cannot have HyperThreading. 699 */ 700 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 701 feature &= ~X86_HTT; 702 703 if ((feature & (X86_HTT | X86_CMP)) == 0) { 704 /* 705 * Single-core single-threaded processors. 706 */ 707 cpi->cpi_chipid = -1; 708 cpi->cpi_clogid = 0; 709 cpi->cpi_coreid = cpu->cpu_id; 710 } else if (cpi->cpi_ncpu_per_chip > 1) { 711 uint_t i; 712 uint_t chipid_shift = 0; 713 uint_t coreid_shift = 0; 714 uint_t apic_id = CPI_APIC_ID(cpi); 715 716 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 717 chipid_shift++; 718 cpi->cpi_chipid = apic_id >> chipid_shift; 719 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 720 721 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 722 if (feature & X86_CMP) { 723 /* 724 * Multi-core (and possibly multi-threaded) 725 * processors. 726 */ 727 uint_t ncpu_per_core; 728 if (cpi->cpi_ncore_per_chip == 1) 729 ncpu_per_core = cpi->cpi_ncpu_per_chip; 730 else if (cpi->cpi_ncore_per_chip > 1) 731 ncpu_per_core = cpi->cpi_ncpu_per_chip / 732 cpi->cpi_ncore_per_chip; 733 /* 734 * 8bit APIC IDs on dual core Pentiums 735 * look like this: 736 * 737 * +-----------------------+------+------+ 738 * | Physical Package ID | MC | HT | 739 * +-----------------------+------+------+ 740 * <------- chipid --------> 741 * <------- coreid ---------------> 742 * <--- clogid --> 743 * 744 * Where the number of bits necessary to 745 * represent MC and HT fields together equals 746 * to the minimum number of bits necessary to 747 * store the value of cpi->cpi_ncpu_per_chip. 748 * Of those bits, the MC part uses the number 749 * of bits necessary to store the value of 750 * cpi->cpi_ncore_per_chip. 751 */ 752 for (i = 1; i < ncpu_per_core; i <<= 1) 753 coreid_shift++; 754 cpi->cpi_coreid = apic_id >> coreid_shift; 755 } else if (feature & X86_HTT) { 756 /* 757 * Single-core multi-threaded processors. 758 */ 759 cpi->cpi_coreid = cpi->cpi_chipid; 760 } 761 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 762 /* 763 * AMD currently only has dual-core processors with 764 * single-threaded cores. If they ever release 765 * multi-threaded processors, then this code 766 * will have to be updated. 767 */ 768 cpi->cpi_coreid = cpu->cpu_id; 769 } else { 770 /* 771 * All other processors are currently 772 * assumed to have single cores. 773 */ 774 cpi->cpi_coreid = cpi->cpi_chipid; 775 } 776 } 777 778 pass1_done: 779 cpi->cpi_pass = 1; 780 return (feature); 781 } 782 783 /* 784 * Make copies of the cpuid table entries we depend on, in 785 * part for ease of parsing now, in part so that we have only 786 * one place to correct any of it, in part for ease of 787 * later export to userland, and in part so we can look at 788 * this stuff in a crash dump. 789 */ 790 791 /*ARGSUSED*/ 792 void 793 cpuid_pass2(cpu_t *cpu) 794 { 795 uint_t n, nmax; 796 int i; 797 struct cpuid_regs *cp; 798 uint8_t *dp; 799 uint32_t *iptr; 800 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 801 802 ASSERT(cpi->cpi_pass == 1); 803 804 if (cpi->cpi_maxeax < 1) 805 goto pass2_done; 806 807 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 808 nmax = NMAX_CPI_STD; 809 /* 810 * (We already handled n == 0 and n == 1 in pass 1) 811 */ 812 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 813 cp->cp_eax = n; 814 (void) __cpuid_insn(cp); 815 switch (n) { 816 case 2: 817 /* 818 * "the lower 8 bits of the %eax register 819 * contain a value that identifies the number 820 * of times the cpuid [instruction] has to be 821 * executed to obtain a complete image of the 822 * processor's caching systems." 823 * 824 * How *do* they make this stuff up? 825 */ 826 cpi->cpi_ncache = sizeof (*cp) * 827 BITX(cp->cp_eax, 7, 0); 828 if (cpi->cpi_ncache == 0) 829 break; 830 cpi->cpi_ncache--; /* skip count byte */ 831 832 /* 833 * Well, for now, rather than attempt to implement 834 * this slightly dubious algorithm, we just look 835 * at the first 15 .. 836 */ 837 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 838 cpi->cpi_ncache = sizeof (*cp) - 1; 839 840 dp = cpi->cpi_cacheinfo; 841 if (BITX(cp->cp_eax, 31, 31) == 0) { 842 uint8_t *p = (void *)&cp->cp_eax; 843 for (i = 1; i < 3; i++) 844 if (p[i] != 0) 845 *dp++ = p[i]; 846 } 847 if (BITX(cp->cp_ebx, 31, 31) == 0) { 848 uint8_t *p = (void *)&cp->cp_ebx; 849 for (i = 0; i < 4; i++) 850 if (p[i] != 0) 851 *dp++ = p[i]; 852 } 853 if (BITX(cp->cp_ecx, 31, 31) == 0) { 854 uint8_t *p = (void *)&cp->cp_ecx; 855 for (i = 0; i < 4; i++) 856 if (p[i] != 0) 857 *dp++ = p[i]; 858 } 859 if (BITX(cp->cp_edx, 31, 31) == 0) { 860 uint8_t *p = (void *)&cp->cp_edx; 861 for (i = 0; i < 4; i++) 862 if (p[i] != 0) 863 *dp++ = p[i]; 864 } 865 break; 866 case 3: /* Processor serial number, if PSN supported */ 867 case 4: /* Deterministic cache parameters */ 868 case 5: /* Monitor/Mwait parameters */ 869 default: 870 break; 871 } 872 } 873 874 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 875 goto pass2_done; 876 877 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 878 nmax = NMAX_CPI_EXTD; 879 /* 880 * Copy the extended properties, fixing them as we go. 881 * (We already handled n == 0 and n == 1 in pass 1) 882 */ 883 iptr = (void *)cpi->cpi_brandstr; 884 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 885 cp->cp_eax = 0x80000000 + n; 886 (void) __cpuid_insn(cp); 887 switch (n) { 888 case 2: 889 case 3: 890 case 4: 891 /* 892 * Extract the brand string 893 */ 894 *iptr++ = cp->cp_eax; 895 *iptr++ = cp->cp_ebx; 896 *iptr++ = cp->cp_ecx; 897 *iptr++ = cp->cp_edx; 898 break; 899 case 5: 900 switch (cpi->cpi_vendor) { 901 case X86_VENDOR_AMD: 902 /* 903 * The Athlon and Duron were the first 904 * parts to report the sizes of the 905 * TLB for large pages. Before then, 906 * we don't trust the data. 907 */ 908 if (cpi->cpi_family < 6 || 909 (cpi->cpi_family == 6 && 910 cpi->cpi_model < 1)) 911 cp->cp_eax = 0; 912 break; 913 default: 914 break; 915 } 916 break; 917 case 6: 918 switch (cpi->cpi_vendor) { 919 case X86_VENDOR_AMD: 920 /* 921 * The Athlon and Duron were the first 922 * AMD parts with L2 TLB's. 923 * Before then, don't trust the data. 924 */ 925 if (cpi->cpi_family < 6 || 926 cpi->cpi_family == 6 && 927 cpi->cpi_model < 1) 928 cp->cp_eax = cp->cp_ebx = 0; 929 /* 930 * AMD Duron rev A0 reports L2 931 * cache size incorrectly as 1K 932 * when it is really 64K 933 */ 934 if (cpi->cpi_family == 6 && 935 cpi->cpi_model == 3 && 936 cpi->cpi_step == 0) { 937 cp->cp_ecx &= 0xffff; 938 cp->cp_ecx |= 0x400000; 939 } 940 break; 941 case X86_VENDOR_Cyrix: /* VIA C3 */ 942 /* 943 * VIA C3 processors are a bit messed 944 * up w.r.t. encoding cache sizes in %ecx 945 */ 946 if (cpi->cpi_family != 6) 947 break; 948 /* 949 * model 7 and 8 were incorrectly encoded 950 * 951 * xxx is model 8 really broken? 952 */ 953 if (cpi->cpi_model == 7 || 954 cpi->cpi_model == 8) 955 cp->cp_ecx = 956 BITX(cp->cp_ecx, 31, 24) << 16 | 957 BITX(cp->cp_ecx, 23, 16) << 12 | 958 BITX(cp->cp_ecx, 15, 8) << 8 | 959 BITX(cp->cp_ecx, 7, 0); 960 /* 961 * model 9 stepping 1 has wrong associativity 962 */ 963 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 964 cp->cp_ecx |= 8 << 12; 965 break; 966 case X86_VENDOR_Intel: 967 /* 968 * Extended L2 Cache features function. 969 * First appeared on Prescott. 970 */ 971 default: 972 break; 973 } 974 break; 975 default: 976 break; 977 } 978 } 979 980 pass2_done: 981 cpi->cpi_pass = 2; 982 } 983 984 static const char * 985 intel_cpubrand(const struct cpuid_info *cpi) 986 { 987 int i; 988 989 if ((x86_feature & X86_CPUID) == 0 || 990 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 991 return ("i486"); 992 993 switch (cpi->cpi_family) { 994 case 5: 995 return ("Intel Pentium(r)"); 996 case 6: 997 switch (cpi->cpi_model) { 998 uint_t celeron, xeon; 999 const struct cpuid_regs *cp; 1000 case 0: 1001 case 1: 1002 case 2: 1003 return ("Intel Pentium(r) Pro"); 1004 case 3: 1005 case 4: 1006 return ("Intel Pentium(r) II"); 1007 case 6: 1008 return ("Intel Celeron(r)"); 1009 case 5: 1010 case 7: 1011 celeron = xeon = 0; 1012 cp = &cpi->cpi_std[2]; /* cache info */ 1013 1014 for (i = 1; i < 3; i++) { 1015 uint_t tmp; 1016 1017 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1018 if (tmp == 0x40) 1019 celeron++; 1020 if (tmp >= 0x44 && tmp <= 0x45) 1021 xeon++; 1022 } 1023 1024 for (i = 0; i < 2; i++) { 1025 uint_t tmp; 1026 1027 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1028 if (tmp == 0x40) 1029 celeron++; 1030 else if (tmp >= 0x44 && tmp <= 0x45) 1031 xeon++; 1032 } 1033 1034 for (i = 0; i < 4; i++) { 1035 uint_t tmp; 1036 1037 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1038 if (tmp == 0x40) 1039 celeron++; 1040 else if (tmp >= 0x44 && tmp <= 0x45) 1041 xeon++; 1042 } 1043 1044 for (i = 0; i < 4; i++) { 1045 uint_t tmp; 1046 1047 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1048 if (tmp == 0x40) 1049 celeron++; 1050 else if (tmp >= 0x44 && tmp <= 0x45) 1051 xeon++; 1052 } 1053 1054 if (celeron) 1055 return ("Intel Celeron(r)"); 1056 if (xeon) 1057 return (cpi->cpi_model == 5 ? 1058 "Intel Pentium(r) II Xeon(tm)" : 1059 "Intel Pentium(r) III Xeon(tm)"); 1060 return (cpi->cpi_model == 5 ? 1061 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1062 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1063 default: 1064 break; 1065 } 1066 default: 1067 break; 1068 } 1069 1070 if (cpi->cpi_family <= 0xf && cpi->cpi_model <= 0xf && 1071 cpi->cpi_brandid != 0) { 1072 static const struct { 1073 uint_t bt_bid; 1074 const char *bt_str; 1075 } brand_tbl[] = { 1076 { 0x1, "Intel(r) Celeron(r)" }, 1077 { 0x2, "Intel(r) Pentium(r) III" }, 1078 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1079 { 0x4, "Intel(r) Pentium(r) III" }, 1080 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1081 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1082 { 0x8, "Intel(r) Pentium(r) 4" }, 1083 { 0x9, "Intel(r) Pentium(r) 4" }, 1084 { 0xa, "Intel(r) Celeron(r)" }, 1085 { 0xb, "Intel(r) Xeon(tm)" }, 1086 { 0xc, "Intel(r) Xeon(tm) MP" }, 1087 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1088 { 0xf, "Mobile Intel(r) Celeron(r)" } 1089 }; 1090 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1091 uint_t sgn; 1092 1093 sgn = (cpi->cpi_family << 8) | 1094 (cpi->cpi_model << 4) | cpi->cpi_step; 1095 1096 for (i = 0; i < btblmax; i++) 1097 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1098 break; 1099 if (i < btblmax) { 1100 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1101 return ("Intel(r) Celeron(r)"); 1102 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1103 return ("Intel(r) Xeon(tm) MP"); 1104 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1105 return ("Intel(r) Xeon(tm)"); 1106 return (brand_tbl[i].bt_str); 1107 } 1108 } 1109 1110 return (NULL); 1111 } 1112 1113 static const char * 1114 amd_cpubrand(const struct cpuid_info *cpi) 1115 { 1116 if ((x86_feature & X86_CPUID) == 0 || 1117 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1118 return ("i486 compatible"); 1119 1120 switch (cpi->cpi_family) { 1121 case 5: 1122 switch (cpi->cpi_model) { 1123 case 0: 1124 case 1: 1125 case 2: 1126 case 3: 1127 case 4: 1128 case 5: 1129 return ("AMD-K5(r)"); 1130 case 6: 1131 case 7: 1132 return ("AMD-K6(r)"); 1133 case 8: 1134 return ("AMD-K6(r)-2"); 1135 case 9: 1136 return ("AMD-K6(r)-III"); 1137 default: 1138 return ("AMD (family 5)"); 1139 } 1140 case 6: 1141 switch (cpi->cpi_model) { 1142 case 1: 1143 return ("AMD-K7(tm)"); 1144 case 0: 1145 case 2: 1146 case 4: 1147 return ("AMD Athlon(tm)"); 1148 case 3: 1149 case 7: 1150 return ("AMD Duron(tm)"); 1151 case 6: 1152 case 8: 1153 case 10: 1154 /* 1155 * Use the L2 cache size to distinguish 1156 */ 1157 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1158 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1159 default: 1160 return ("AMD (family 6)"); 1161 } 1162 default: 1163 break; 1164 } 1165 1166 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1167 cpi->cpi_brandid != 0) { 1168 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1169 case 3: 1170 return ("AMD Opteron(tm) UP 1xx"); 1171 case 4: 1172 return ("AMD Opteron(tm) DP 2xx"); 1173 case 5: 1174 return ("AMD Opteron(tm) MP 8xx"); 1175 default: 1176 return ("AMD Opteron(tm)"); 1177 } 1178 } 1179 1180 return (NULL); 1181 } 1182 1183 static const char * 1184 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1185 { 1186 if ((x86_feature & X86_CPUID) == 0 || 1187 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1188 type == X86_TYPE_CYRIX_486) 1189 return ("i486 compatible"); 1190 1191 switch (type) { 1192 case X86_TYPE_CYRIX_6x86: 1193 return ("Cyrix 6x86"); 1194 case X86_TYPE_CYRIX_6x86L: 1195 return ("Cyrix 6x86L"); 1196 case X86_TYPE_CYRIX_6x86MX: 1197 return ("Cyrix 6x86MX"); 1198 case X86_TYPE_CYRIX_GXm: 1199 return ("Cyrix GXm"); 1200 case X86_TYPE_CYRIX_MediaGX: 1201 return ("Cyrix MediaGX"); 1202 case X86_TYPE_CYRIX_MII: 1203 return ("Cyrix M2"); 1204 case X86_TYPE_VIA_CYRIX_III: 1205 return ("VIA Cyrix M3"); 1206 default: 1207 /* 1208 * Have another wild guess .. 1209 */ 1210 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1211 return ("Cyrix 5x86"); 1212 else if (cpi->cpi_family == 5) { 1213 switch (cpi->cpi_model) { 1214 case 2: 1215 return ("Cyrix 6x86"); /* Cyrix M1 */ 1216 case 4: 1217 return ("Cyrix MediaGX"); 1218 default: 1219 break; 1220 } 1221 } else if (cpi->cpi_family == 6) { 1222 switch (cpi->cpi_model) { 1223 case 0: 1224 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1225 case 5: 1226 case 6: 1227 case 7: 1228 case 8: 1229 case 9: 1230 return ("VIA C3"); 1231 default: 1232 break; 1233 } 1234 } 1235 break; 1236 } 1237 return (NULL); 1238 } 1239 1240 /* 1241 * This only gets called in the case that the CPU extended 1242 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1243 * aren't available, or contain null bytes for some reason. 1244 */ 1245 static void 1246 fabricate_brandstr(struct cpuid_info *cpi) 1247 { 1248 const char *brand = NULL; 1249 1250 switch (cpi->cpi_vendor) { 1251 case X86_VENDOR_Intel: 1252 brand = intel_cpubrand(cpi); 1253 break; 1254 case X86_VENDOR_AMD: 1255 brand = amd_cpubrand(cpi); 1256 break; 1257 case X86_VENDOR_Cyrix: 1258 brand = cyrix_cpubrand(cpi, x86_type); 1259 break; 1260 case X86_VENDOR_NexGen: 1261 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1262 brand = "NexGen Nx586"; 1263 break; 1264 case X86_VENDOR_Centaur: 1265 if (cpi->cpi_family == 5) 1266 switch (cpi->cpi_model) { 1267 case 4: 1268 brand = "Centaur C6"; 1269 break; 1270 case 8: 1271 brand = "Centaur C2"; 1272 break; 1273 case 9: 1274 brand = "Centaur C3"; 1275 break; 1276 default: 1277 break; 1278 } 1279 break; 1280 case X86_VENDOR_Rise: 1281 if (cpi->cpi_family == 5 && 1282 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1283 brand = "Rise mP6"; 1284 break; 1285 case X86_VENDOR_SiS: 1286 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1287 brand = "SiS 55x"; 1288 break; 1289 case X86_VENDOR_TM: 1290 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1291 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1292 break; 1293 case X86_VENDOR_NSC: 1294 case X86_VENDOR_UMC: 1295 default: 1296 break; 1297 } 1298 if (brand) { 1299 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1300 return; 1301 } 1302 1303 /* 1304 * If all else fails ... 1305 */ 1306 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1307 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1308 cpi->cpi_model, cpi->cpi_step); 1309 } 1310 1311 /* 1312 * This routine is called just after kernel memory allocation 1313 * becomes available on cpu0, and as part of mp_startup() on 1314 * the other cpus. 1315 * 1316 * Fixup the brand string. 1317 */ 1318 /*ARGSUSED*/ 1319 void 1320 cpuid_pass3(cpu_t *cpu) 1321 { 1322 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1323 1324 ASSERT(cpi->cpi_pass == 2); 1325 1326 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1327 fabricate_brandstr(cpi); 1328 goto pass3_done; 1329 } 1330 1331 /* 1332 * If we successfully extracted a brand string from the cpuid 1333 * instruction, clean it up by removing leading spaces and 1334 * similar junk. 1335 */ 1336 if (cpi->cpi_brandstr[0]) { 1337 size_t maxlen = sizeof (cpi->cpi_brandstr); 1338 char *src, *dst; 1339 1340 dst = src = (char *)cpi->cpi_brandstr; 1341 src[maxlen - 1] = '\0'; 1342 /* 1343 * strip leading spaces 1344 */ 1345 while (*src == ' ') 1346 src++; 1347 /* 1348 * Remove any 'Genuine' or "Authentic" prefixes 1349 */ 1350 if (strncmp(src, "Genuine ", 8) == 0) 1351 src += 8; 1352 if (strncmp(src, "Authentic ", 10) == 0) 1353 src += 10; 1354 1355 /* 1356 * Now do an in-place copy. 1357 * Map (R) to (r) and (TM) to (tm). 1358 * The era of teletypes is long gone, and there's 1359 * -really- no need to shout. 1360 */ 1361 while (*src != '\0') { 1362 if (src[0] == '(') { 1363 if (strncmp(src + 1, "R)", 2) == 0) { 1364 (void) strncpy(dst, "(r)", 3); 1365 src += 3; 1366 dst += 3; 1367 continue; 1368 } 1369 if (strncmp(src + 1, "TM)", 3) == 0) { 1370 (void) strncpy(dst, "(tm)", 4); 1371 src += 4; 1372 dst += 4; 1373 continue; 1374 } 1375 } 1376 *dst++ = *src++; 1377 } 1378 *dst = '\0'; 1379 1380 /* 1381 * Finally, remove any trailing spaces 1382 */ 1383 while (--dst > cpi->cpi_brandstr) 1384 if (*dst == ' ') 1385 *dst = '\0'; 1386 else 1387 break; 1388 } else 1389 fabricate_brandstr(cpi); 1390 1391 pass3_done: 1392 cpi->cpi_pass = 3; 1393 } 1394 1395 /* 1396 * This routine is called out of bind_hwcap() much later in the life 1397 * of the kernel (post_startup()). The job of this routine is to resolve 1398 * the hardware feature support and kernel support for those features into 1399 * what we're actually going to tell applications via the aux vector. 1400 */ 1401 uint_t 1402 cpuid_pass4(cpu_t *cpu) 1403 { 1404 struct cpuid_info *cpi; 1405 uint_t hwcap_flags = 0; 1406 1407 if (cpu == NULL) 1408 cpu = CPU; 1409 cpi = cpu->cpu_m.mcpu_cpi; 1410 1411 ASSERT(cpi->cpi_pass == 3); 1412 1413 if (cpi->cpi_maxeax >= 1) { 1414 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1415 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1416 1417 *edx = CPI_FEATURES_EDX(cpi); 1418 *ecx = CPI_FEATURES_ECX(cpi); 1419 1420 /* 1421 * [these require explicit kernel support] 1422 */ 1423 if ((x86_feature & X86_SEP) == 0) 1424 *edx &= ~CPUID_INTC_EDX_SEP; 1425 1426 if ((x86_feature & X86_SSE) == 0) 1427 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1428 if ((x86_feature & X86_SSE2) == 0) 1429 *edx &= ~CPUID_INTC_EDX_SSE2; 1430 1431 if ((x86_feature & X86_HTT) == 0) 1432 *edx &= ~CPUID_INTC_EDX_HTT; 1433 1434 if ((x86_feature & X86_SSE3) == 0) 1435 *ecx &= ~CPUID_INTC_ECX_SSE3; 1436 1437 /* 1438 * [no explicit support required beyond x87 fp context] 1439 */ 1440 if (!fpu_exists) 1441 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1442 1443 /* 1444 * Now map the supported feature vector to things that we 1445 * think userland will care about. 1446 */ 1447 if (*edx & CPUID_INTC_EDX_SEP) 1448 hwcap_flags |= AV_386_SEP; 1449 if (*edx & CPUID_INTC_EDX_SSE) 1450 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1451 if (*edx & CPUID_INTC_EDX_SSE2) 1452 hwcap_flags |= AV_386_SSE2; 1453 if (*ecx & CPUID_INTC_ECX_SSE3) 1454 hwcap_flags |= AV_386_SSE3; 1455 1456 if (*edx & CPUID_INTC_EDX_FPU) 1457 hwcap_flags |= AV_386_FPU; 1458 if (*edx & CPUID_INTC_EDX_MMX) 1459 hwcap_flags |= AV_386_MMX; 1460 1461 if (*edx & CPUID_INTC_EDX_TSC) 1462 hwcap_flags |= AV_386_TSC; 1463 if (*edx & CPUID_INTC_EDX_CX8) 1464 hwcap_flags |= AV_386_CX8; 1465 if (*edx & CPUID_INTC_EDX_CMOV) 1466 hwcap_flags |= AV_386_CMOV; 1467 if (*ecx & CPUID_INTC_ECX_MON) 1468 hwcap_flags |= AV_386_MON; 1469 #if defined(CPUID_INTC_ECX_CX16) 1470 if (*ecx & CPUID_INTC_ECX_CX16) 1471 hwcap_flags |= AV_386_CX16; 1472 #endif 1473 } 1474 1475 if (x86_feature & X86_HTT) 1476 hwcap_flags |= AV_386_PAUSE; 1477 1478 if (cpi->cpi_xmaxeax < 0x80000001) 1479 goto pass4_done; 1480 1481 switch (cpi->cpi_vendor) { 1482 struct cpuid_regs cp; 1483 uint32_t *edx; 1484 1485 case X86_VENDOR_Intel: /* sigh */ 1486 case X86_VENDOR_AMD: 1487 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1488 1489 *edx = CPI_FEATURES_XTD_EDX(cpi); 1490 1491 /* 1492 * [no explicit support required beyond 1493 * x87 fp context and exception handlers] 1494 */ 1495 if (!fpu_exists) 1496 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1497 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1498 1499 if ((x86_feature & X86_ASYSC) == 0) 1500 *edx &= ~CPUID_AMD_EDX_SYSC; 1501 if ((x86_feature & X86_NX) == 0) 1502 *edx &= ~CPUID_AMD_EDX_NX; 1503 #if !defined(_LP64) 1504 *edx &= ~CPUID_AMD_EDX_LM; 1505 #endif 1506 /* 1507 * Now map the supported feature vector to 1508 * things that we think userland will care about. 1509 */ 1510 if (*edx & CPUID_AMD_EDX_SYSC) 1511 hwcap_flags |= AV_386_AMD_SYSC; 1512 if (*edx & CPUID_AMD_EDX_MMXamd) 1513 hwcap_flags |= AV_386_AMD_MMX; 1514 if (*edx & CPUID_AMD_EDX_3DNow) 1515 hwcap_flags |= AV_386_AMD_3DNow; 1516 if (*edx & CPUID_AMD_EDX_3DNowx) 1517 hwcap_flags |= AV_386_AMD_3DNowx; 1518 break; 1519 1520 case X86_VENDOR_TM: 1521 cp.cp_eax = 0x80860001; 1522 (void) __cpuid_insn(&cp); 1523 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 1524 break; 1525 1526 default: 1527 break; 1528 } 1529 1530 pass4_done: 1531 cpi->cpi_pass = 4; 1532 return (hwcap_flags); 1533 } 1534 1535 1536 /* 1537 * Simulate the cpuid instruction using the data we previously 1538 * captured about this CPU. We try our best to return the truth 1539 * about the hardware, independently of kernel support. 1540 */ 1541 uint32_t 1542 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 1543 { 1544 struct cpuid_info *cpi; 1545 struct cpuid_regs *xcp; 1546 1547 if (cpu == NULL) 1548 cpu = CPU; 1549 cpi = cpu->cpu_m.mcpu_cpi; 1550 1551 ASSERT(cpuid_checkpass(cpu, 3)); 1552 1553 /* 1554 * CPUID data is cached in two separate places: cpi_std for standard 1555 * CPUID functions, and cpi_extd for extended CPUID functions. 1556 */ 1557 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 1558 xcp = &cpi->cpi_std[cp->cp_eax]; 1559 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 1560 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 1561 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 1562 else 1563 /* 1564 * The caller is asking for data from an input parameter which 1565 * the kernel has not cached. In this case we go fetch from 1566 * the hardware and return the data directly to the user. 1567 */ 1568 return (__cpuid_insn(cp)); 1569 1570 cp->cp_eax = xcp->cp_eax; 1571 cp->cp_ebx = xcp->cp_ebx; 1572 cp->cp_ecx = xcp->cp_ecx; 1573 cp->cp_edx = xcp->cp_edx; 1574 return (cp->cp_eax); 1575 } 1576 1577 int 1578 cpuid_checkpass(cpu_t *cpu, int pass) 1579 { 1580 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 1581 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 1582 } 1583 1584 int 1585 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 1586 { 1587 ASSERT(cpuid_checkpass(cpu, 3)); 1588 1589 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 1590 } 1591 1592 int 1593 cpuid_is_cmt(cpu_t *cpu) 1594 { 1595 if (cpu == NULL) 1596 cpu = CPU; 1597 1598 ASSERT(cpuid_checkpass(cpu, 1)); 1599 1600 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 1601 } 1602 1603 /* 1604 * AMD and Intel both implement the 64-bit variant of the syscall 1605 * instruction (syscallq), so if there's -any- support for syscall, 1606 * cpuid currently says "yes, we support this". 1607 * 1608 * However, Intel decided to -not- implement the 32-bit variant of the 1609 * syscall instruction, so we provide a predicate to allow our caller 1610 * to test that subtlety here. 1611 */ 1612 /*ARGSUSED*/ 1613 int 1614 cpuid_syscall32_insn(cpu_t *cpu) 1615 { 1616 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 1617 1618 if (x86_feature & X86_ASYSC) 1619 return (x86_vendor != X86_VENDOR_Intel); 1620 return (0); 1621 } 1622 1623 int 1624 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 1625 { 1626 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1627 1628 static const char fmt[] = 1629 "x86 (%s family %d model %d step %d clock %d MHz)"; 1630 static const char fmt_ht[] = 1631 "x86 (chipid 0x%x %s family %d model %d step %d clock %d MHz)"; 1632 1633 ASSERT(cpuid_checkpass(cpu, 1)); 1634 1635 if (cpuid_is_cmt(cpu)) 1636 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 1637 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1638 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1639 return (snprintf(s, n, fmt, 1640 cpi->cpi_vendorstr, cpi->cpi_family, cpi->cpi_model, 1641 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 1642 } 1643 1644 const char * 1645 cpuid_getvendorstr(cpu_t *cpu) 1646 { 1647 ASSERT(cpuid_checkpass(cpu, 1)); 1648 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 1649 } 1650 1651 uint_t 1652 cpuid_getvendor(cpu_t *cpu) 1653 { 1654 ASSERT(cpuid_checkpass(cpu, 1)); 1655 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 1656 } 1657 1658 uint_t 1659 cpuid_getfamily(cpu_t *cpu) 1660 { 1661 ASSERT(cpuid_checkpass(cpu, 1)); 1662 return (cpu->cpu_m.mcpu_cpi->cpi_family); 1663 } 1664 1665 uint_t 1666 cpuid_getmodel(cpu_t *cpu) 1667 { 1668 ASSERT(cpuid_checkpass(cpu, 1)); 1669 return (cpu->cpu_m.mcpu_cpi->cpi_model); 1670 } 1671 1672 uint_t 1673 cpuid_get_ncpu_per_chip(cpu_t *cpu) 1674 { 1675 ASSERT(cpuid_checkpass(cpu, 1)); 1676 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 1677 } 1678 1679 uint_t 1680 cpuid_get_ncore_per_chip(cpu_t *cpu) 1681 { 1682 ASSERT(cpuid_checkpass(cpu, 1)); 1683 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 1684 } 1685 1686 uint_t 1687 cpuid_getstep(cpu_t *cpu) 1688 { 1689 ASSERT(cpuid_checkpass(cpu, 1)); 1690 return (cpu->cpu_m.mcpu_cpi->cpi_step); 1691 } 1692 1693 chipid_t 1694 chip_plat_get_chipid(cpu_t *cpu) 1695 { 1696 ASSERT(cpuid_checkpass(cpu, 1)); 1697 1698 if (cpuid_is_cmt(cpu)) 1699 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 1700 return (cpu->cpu_id); 1701 } 1702 1703 id_t 1704 chip_plat_get_coreid(cpu_t *cpu) 1705 { 1706 ASSERT(cpuid_checkpass(cpu, 1)); 1707 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 1708 } 1709 1710 int 1711 chip_plat_get_clogid(cpu_t *cpu) 1712 { 1713 ASSERT(cpuid_checkpass(cpu, 1)); 1714 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 1715 } 1716 1717 void 1718 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 1719 { 1720 struct cpuid_info *cpi; 1721 1722 if (cpu == NULL) 1723 cpu = CPU; 1724 cpi = cpu->cpu_m.mcpu_cpi; 1725 1726 ASSERT(cpuid_checkpass(cpu, 1)); 1727 1728 if (pabits) 1729 *pabits = cpi->cpi_pabits; 1730 if (vabits) 1731 *vabits = cpi->cpi_vabits; 1732 } 1733 1734 /* 1735 * Returns the number of data TLB entries for a corresponding 1736 * pagesize. If it can't be computed, or isn't known, the 1737 * routine returns zero. If you ask about an architecturally 1738 * impossible pagesize, the routine will panic (so that the 1739 * hat implementor knows that things are inconsistent.) 1740 */ 1741 uint_t 1742 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 1743 { 1744 struct cpuid_info *cpi; 1745 uint_t dtlb_nent = 0; 1746 1747 if (cpu == NULL) 1748 cpu = CPU; 1749 cpi = cpu->cpu_m.mcpu_cpi; 1750 1751 ASSERT(cpuid_checkpass(cpu, 1)); 1752 1753 /* 1754 * Check the L2 TLB info 1755 */ 1756 if (cpi->cpi_xmaxeax >= 0x80000006) { 1757 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 1758 1759 switch (pagesize) { 1760 1761 case 4 * 1024: 1762 /* 1763 * All zero in the top 16 bits of the register 1764 * indicates a unified TLB. Size is in low 16 bits. 1765 */ 1766 if ((cp->cp_ebx & 0xffff0000) == 0) 1767 dtlb_nent = cp->cp_ebx & 0x0000ffff; 1768 else 1769 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 1770 break; 1771 1772 case 2 * 1024 * 1024: 1773 if ((cp->cp_eax & 0xffff0000) == 0) 1774 dtlb_nent = cp->cp_eax & 0x0000ffff; 1775 else 1776 dtlb_nent = BITX(cp->cp_eax, 27, 16); 1777 break; 1778 1779 default: 1780 panic("unknown L2 pagesize"); 1781 /*NOTREACHED*/ 1782 } 1783 } 1784 1785 if (dtlb_nent != 0) 1786 return (dtlb_nent); 1787 1788 /* 1789 * No L2 TLB support for this size, try L1. 1790 */ 1791 if (cpi->cpi_xmaxeax >= 0x80000005) { 1792 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 1793 1794 switch (pagesize) { 1795 case 4 * 1024: 1796 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 1797 break; 1798 case 2 * 1024 * 1024: 1799 dtlb_nent = BITX(cp->cp_eax, 23, 16); 1800 break; 1801 default: 1802 panic("unknown L1 d-TLB pagesize"); 1803 /*NOTREACHED*/ 1804 } 1805 } 1806 1807 return (dtlb_nent); 1808 } 1809 1810 /* 1811 * Return 0 if the erratum is not present or not applicable, positive 1812 * if it is, and negative if the status of the erratum is unknown. 1813 * 1814 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 1815 * Processors" #25759, Rev 3.57, August 2005 1816 */ 1817 int 1818 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 1819 { 1820 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1821 uint_t eax; 1822 1823 if (cpi->cpi_vendor != X86_VENDOR_AMD) 1824 return (0); 1825 1826 eax = cpi->cpi_std[1].cp_eax; 1827 1828 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 1829 #define SH_B3(eax) (eax == 0xf51) 1830 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 1831 1832 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 1833 1834 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 1835 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 1836 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 1837 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 1838 1839 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 1840 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 1841 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 1842 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 1843 1844 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 1845 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 1846 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 1847 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 1848 #define BH_E4(eax) (eax == 0x20fb1) 1849 #define SH_E5(eax) (eax == 0x20f42) 1850 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 1851 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 1852 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 1853 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 1854 DH_E6(eax) || JH_E6(eax)) 1855 1856 switch (erratum) { 1857 case 1: 1858 return (1); 1859 case 51: /* what does the asterisk mean? */ 1860 return (B(eax) || SH_C0(eax) || CG(eax)); 1861 case 52: 1862 return (B(eax)); 1863 case 57: 1864 return (1); 1865 case 58: 1866 return (B(eax)); 1867 case 60: 1868 return (1); 1869 case 61: 1870 case 62: 1871 case 63: 1872 case 64: 1873 case 65: 1874 case 66: 1875 case 68: 1876 case 69: 1877 case 70: 1878 case 71: 1879 return (B(eax)); 1880 case 72: 1881 return (SH_B0(eax)); 1882 case 74: 1883 return (B(eax)); 1884 case 75: 1885 return (1); 1886 case 76: 1887 return (B(eax)); 1888 case 77: 1889 return (1); 1890 case 78: 1891 return (B(eax) || SH_C0(eax)); 1892 case 79: 1893 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1894 case 80: 1895 case 81: 1896 case 82: 1897 return (B(eax)); 1898 case 83: 1899 return (B(eax) || SH_C0(eax) || CG(eax)); 1900 case 85: 1901 return (1); 1902 case 86: 1903 return (SH_C0(eax) || CG(eax)); 1904 case 88: 1905 #if !defined(__amd64) 1906 return (0); 1907 #else 1908 return (B(eax) || SH_C0(eax)); 1909 #endif 1910 case 89: 1911 return (1); 1912 case 90: 1913 return (B(eax) || SH_C0(eax) || CG(eax)); 1914 case 91: 1915 case 92: 1916 return (B(eax) || SH_C0(eax)); 1917 case 93: 1918 return (SH_C0(eax)); 1919 case 94: 1920 return (B(eax) || SH_C0(eax) || CG(eax)); 1921 case 95: 1922 #if !defined(__amd64) 1923 return (0); 1924 #else 1925 return (B(eax) || SH_C0(eax)); 1926 #endif 1927 case 96: 1928 return (B(eax) || SH_C0(eax) || CG(eax)); 1929 case 97: 1930 case 98: 1931 return (SH_C0(eax) || CG(eax)); 1932 case 99: 1933 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1934 case 100: 1935 return (B(eax) || SH_C0(eax)); 1936 case 101: 1937 case 103: 1938 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1939 case 104: 1940 return (SH_C0(eax) || CG(eax) || D0(eax)); 1941 case 105: 1942 case 106: 1943 case 107: 1944 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1945 case 108: 1946 return (DH_CG(eax)); 1947 case 109: 1948 return (SH_C0(eax) || CG(eax) || D0(eax)); 1949 case 110: 1950 return (D0(eax) || EX(eax)); 1951 case 111: 1952 return (CG(eax)); 1953 case 112: 1954 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1955 case 113: 1956 return (eax == 0x20fc0); 1957 case 114: 1958 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 1959 case 115: 1960 return (SH_E0(eax) || JH_E1(eax)); 1961 case 116: 1962 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 1963 case 117: 1964 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 1965 case 118: 1966 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 1967 JH_E6(eax)); 1968 case 121: 1969 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1970 case 122: 1971 return (SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 1972 case 123: 1973 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 1974 case 131: 1975 return (1); 1976 case 6336786: 1977 /* 1978 * Test for AdvPowerMgmtInfo.TscPStateInvariant 1979 * if this is a K8 family processor 1980 */ 1981 if (CPI_FAMILY(cpi) == 0xf) { 1982 struct cpuid_regs regs; 1983 regs.cp_eax = 0x80000007; 1984 (void) __cpuid_insn(®s); 1985 return (!(regs.cp_edx & 0x100)); 1986 } 1987 return (0); 1988 case 6323525: 1989 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 1990 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 1991 1992 default: 1993 return (-1); 1994 } 1995 } 1996 1997 static const char assoc_str[] = "associativity"; 1998 static const char line_str[] = "line-size"; 1999 static const char size_str[] = "size"; 2000 2001 static void 2002 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2003 uint32_t val) 2004 { 2005 char buf[128]; 2006 2007 /* 2008 * ndi_prop_update_int() is used because it is desirable for 2009 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2010 */ 2011 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2012 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2013 } 2014 2015 /* 2016 * Intel-style cache/tlb description 2017 * 2018 * Standard cpuid level 2 gives a randomly ordered 2019 * selection of tags that index into a table that describes 2020 * cache and tlb properties. 2021 */ 2022 2023 static const char l1_icache_str[] = "l1-icache"; 2024 static const char l1_dcache_str[] = "l1-dcache"; 2025 static const char l2_cache_str[] = "l2-cache"; 2026 static const char itlb4k_str[] = "itlb-4K"; 2027 static const char dtlb4k_str[] = "dtlb-4K"; 2028 static const char itlb4M_str[] = "itlb-4M"; 2029 static const char dtlb4M_str[] = "dtlb-4M"; 2030 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2031 static const char dtlb44_str[] = "dtlb-4K-4M"; 2032 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2033 static const char sl2_cache_str[] = "sectored-l2-cache"; 2034 static const char itrace_str[] = "itrace-cache"; 2035 static const char sl3_cache_str[] = "sectored-l3-cache"; 2036 2037 static const struct cachetab { 2038 uint8_t ct_code; 2039 uint8_t ct_assoc; 2040 uint16_t ct_line_size; 2041 size_t ct_size; 2042 const char *ct_label; 2043 } intel_ctab[] = { 2044 /* maintain descending order! */ 2045 { 0xb3, 4, 0, 128, dtlb4k_str }, 2046 { 0xb0, 4, 0, 128, itlb4k_str }, 2047 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2048 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2049 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2050 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2051 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2052 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2053 { 0x81, 8, 32, 128*1024, l2_cache_str}, /* suspect! */ 2054 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2055 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2056 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2057 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2058 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2059 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2060 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2061 { 0x72, 8, 0, 32*1024, itrace_str}, 2062 { 0x71, 8, 0, 16*1024, itrace_str}, 2063 { 0x70, 8, 0, 12*1024, itrace_str}, 2064 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2065 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2066 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2067 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2068 { 0x5d, 0, 0, 256, dtlb44_str}, 2069 { 0x5c, 0, 0, 128, dtlb44_str}, 2070 { 0x5b, 0, 0, 64, dtlb44_str}, 2071 { 0x52, 0, 0, 256, itlb424_str}, 2072 { 0x51, 0, 0, 128, itlb424_str}, 2073 { 0x50, 0, 0, 64, itlb424_str}, 2074 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2075 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2076 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2077 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2078 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2079 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2080 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2081 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2082 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2083 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2084 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2085 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2086 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2087 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2088 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2089 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2090 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2091 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2092 { 0x04, 4, 0, 8, dtlb4M_str}, 2093 { 0x03, 4, 0, 64, dtlb4k_str}, 2094 { 0x02, 4, 0, 2, itlb4M_str}, 2095 { 0x01, 4, 0, 32, itlb4k_str}, 2096 { 0 } 2097 }; 2098 2099 static const struct cachetab cyrix_ctab[] = { 2100 { 0x70, 4, 0, 32, "tlb-4K" }, 2101 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2102 { 0 } 2103 }; 2104 2105 /* 2106 * Search a cache table for a matching entry 2107 */ 2108 static const struct cachetab * 2109 find_cacheent(const struct cachetab *ct, uint_t code) 2110 { 2111 if (code != 0) { 2112 for (; ct->ct_code != 0; ct++) 2113 if (ct->ct_code <= code) 2114 break; 2115 if (ct->ct_code == code) 2116 return (ct); 2117 } 2118 return (NULL); 2119 } 2120 2121 /* 2122 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2123 * The walk is terminated if the walker returns non-zero. 2124 */ 2125 static void 2126 intel_walk_cacheinfo(struct cpuid_info *cpi, 2127 void *arg, int (*func)(void *, const struct cachetab *)) 2128 { 2129 const struct cachetab *ct; 2130 uint8_t *dp; 2131 int i; 2132 2133 if ((dp = cpi->cpi_cacheinfo) == NULL) 2134 return; 2135 for (i = 0; i < cpi->cpi_ncache; i++, dp++) 2136 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2137 if (func(arg, ct) != 0) 2138 break; 2139 } 2140 } 2141 2142 /* 2143 * (Like the Intel one, except for Cyrix CPUs) 2144 */ 2145 static void 2146 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2147 void *arg, int (*func)(void *, const struct cachetab *)) 2148 { 2149 const struct cachetab *ct; 2150 uint8_t *dp; 2151 int i; 2152 2153 if ((dp = cpi->cpi_cacheinfo) == NULL) 2154 return; 2155 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2156 /* 2157 * Search Cyrix-specific descriptor table first .. 2158 */ 2159 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2160 if (func(arg, ct) != 0) 2161 break; 2162 continue; 2163 } 2164 /* 2165 * .. else fall back to the Intel one 2166 */ 2167 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2168 if (func(arg, ct) != 0) 2169 break; 2170 continue; 2171 } 2172 } 2173 } 2174 2175 /* 2176 * A cacheinfo walker that adds associativity, line-size, and size properties 2177 * to the devinfo node it is passed as an argument. 2178 */ 2179 static int 2180 add_cacheent_props(void *arg, const struct cachetab *ct) 2181 { 2182 dev_info_t *devi = arg; 2183 2184 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2185 if (ct->ct_line_size != 0) 2186 add_cache_prop(devi, ct->ct_label, line_str, 2187 ct->ct_line_size); 2188 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2189 return (0); 2190 } 2191 2192 static const char fully_assoc[] = "fully-associative?"; 2193 2194 /* 2195 * AMD style cache/tlb description 2196 * 2197 * Extended functions 5 and 6 directly describe properties of 2198 * tlbs and various cache levels. 2199 */ 2200 static void 2201 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2202 { 2203 switch (assoc) { 2204 case 0: /* reserved; ignore */ 2205 break; 2206 default: 2207 add_cache_prop(devi, label, assoc_str, assoc); 2208 break; 2209 case 0xff: 2210 add_cache_prop(devi, label, fully_assoc, 1); 2211 break; 2212 } 2213 } 2214 2215 static void 2216 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2217 { 2218 if (size == 0) 2219 return; 2220 add_cache_prop(devi, label, size_str, size); 2221 add_amd_assoc(devi, label, assoc); 2222 } 2223 2224 static void 2225 add_amd_cache(dev_info_t *devi, const char *label, 2226 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2227 { 2228 if (size == 0 || line_size == 0) 2229 return; 2230 add_amd_assoc(devi, label, assoc); 2231 /* 2232 * Most AMD parts have a sectored cache. Multiple cache lines are 2233 * associated with each tag. A sector consists of all cache lines 2234 * associated with a tag. For example, the AMD K6-III has a sector 2235 * size of 2 cache lines per tag. 2236 */ 2237 if (lines_per_tag != 0) 2238 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2239 add_cache_prop(devi, label, line_str, line_size); 2240 add_cache_prop(devi, label, size_str, size * 1024); 2241 } 2242 2243 static void 2244 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2245 { 2246 switch (assoc) { 2247 case 0: /* off */ 2248 break; 2249 case 1: 2250 case 2: 2251 case 4: 2252 add_cache_prop(devi, label, assoc_str, assoc); 2253 break; 2254 case 6: 2255 add_cache_prop(devi, label, assoc_str, 8); 2256 break; 2257 case 8: 2258 add_cache_prop(devi, label, assoc_str, 16); 2259 break; 2260 case 0xf: 2261 add_cache_prop(devi, label, fully_assoc, 1); 2262 break; 2263 default: /* reserved; ignore */ 2264 break; 2265 } 2266 } 2267 2268 static void 2269 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2270 { 2271 if (size == 0 || assoc == 0) 2272 return; 2273 add_amd_l2_assoc(devi, label, assoc); 2274 add_cache_prop(devi, label, size_str, size); 2275 } 2276 2277 static void 2278 add_amd_l2_cache(dev_info_t *devi, const char *label, 2279 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2280 { 2281 if (size == 0 || assoc == 0 || line_size == 0) 2282 return; 2283 add_amd_l2_assoc(devi, label, assoc); 2284 if (lines_per_tag != 0) 2285 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2286 add_cache_prop(devi, label, line_str, line_size); 2287 add_cache_prop(devi, label, size_str, size * 1024); 2288 } 2289 2290 static void 2291 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2292 { 2293 struct cpuid_regs *cp; 2294 2295 if (cpi->cpi_xmaxeax < 0x80000005) 2296 return; 2297 cp = &cpi->cpi_extd[5]; 2298 2299 /* 2300 * 4M/2M L1 TLB configuration 2301 * 2302 * We report the size for 2M pages because AMD uses two 2303 * TLB entries for one 4M page. 2304 */ 2305 add_amd_tlb(devi, "dtlb-2M", 2306 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2307 add_amd_tlb(devi, "itlb-2M", 2308 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2309 2310 /* 2311 * 4K L1 TLB configuration 2312 */ 2313 2314 switch (cpi->cpi_vendor) { 2315 uint_t nentries; 2316 case X86_VENDOR_TM: 2317 if (cpi->cpi_family >= 5) { 2318 /* 2319 * Crusoe processors have 256 TLB entries, but 2320 * cpuid data format constrains them to only 2321 * reporting 255 of them. 2322 */ 2323 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2324 nentries = 256; 2325 /* 2326 * Crusoe processors also have a unified TLB 2327 */ 2328 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2329 nentries); 2330 break; 2331 } 2332 /*FALLTHROUGH*/ 2333 default: 2334 add_amd_tlb(devi, itlb4k_str, 2335 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2336 add_amd_tlb(devi, dtlb4k_str, 2337 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2338 break; 2339 } 2340 2341 /* 2342 * data L1 cache configuration 2343 */ 2344 2345 add_amd_cache(devi, l1_dcache_str, 2346 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2347 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2348 2349 /* 2350 * code L1 cache configuration 2351 */ 2352 2353 add_amd_cache(devi, l1_icache_str, 2354 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2355 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2356 2357 if (cpi->cpi_xmaxeax < 0x80000006) 2358 return; 2359 cp = &cpi->cpi_extd[6]; 2360 2361 /* Check for a unified L2 TLB for large pages */ 2362 2363 if (BITX(cp->cp_eax, 31, 16) == 0) 2364 add_amd_l2_tlb(devi, "l2-tlb-2M", 2365 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2366 else { 2367 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2368 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2369 add_amd_l2_tlb(devi, "l2-itlb-2M", 2370 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2371 } 2372 2373 /* Check for a unified L2 TLB for 4K pages */ 2374 2375 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2376 add_amd_l2_tlb(devi, "l2-tlb-4K", 2377 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2378 } else { 2379 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2380 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2381 add_amd_l2_tlb(devi, "l2-itlb-4K", 2382 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2383 } 2384 2385 add_amd_l2_cache(devi, l2_cache_str, 2386 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2387 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2388 } 2389 2390 /* 2391 * There are two basic ways that the x86 world describes it cache 2392 * and tlb architecture - Intel's way and AMD's way. 2393 * 2394 * Return which flavor of cache architecture we should use 2395 */ 2396 static int 2397 x86_which_cacheinfo(struct cpuid_info *cpi) 2398 { 2399 switch (cpi->cpi_vendor) { 2400 case X86_VENDOR_Intel: 2401 if (cpi->cpi_maxeax >= 2) 2402 return (X86_VENDOR_Intel); 2403 break; 2404 case X86_VENDOR_AMD: 2405 /* 2406 * The K5 model 1 was the first part from AMD that reported 2407 * cache sizes via extended cpuid functions. 2408 */ 2409 if (cpi->cpi_family > 5 || 2410 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 2411 return (X86_VENDOR_AMD); 2412 break; 2413 case X86_VENDOR_TM: 2414 if (cpi->cpi_family >= 5) 2415 return (X86_VENDOR_AMD); 2416 /*FALLTHROUGH*/ 2417 default: 2418 /* 2419 * If they have extended CPU data for 0x80000005 2420 * then we assume they have AMD-format cache 2421 * information. 2422 * 2423 * If not, and the vendor happens to be Cyrix, 2424 * then try our-Cyrix specific handler. 2425 * 2426 * If we're not Cyrix, then assume we're using Intel's 2427 * table-driven format instead. 2428 */ 2429 if (cpi->cpi_xmaxeax >= 0x80000005) 2430 return (X86_VENDOR_AMD); 2431 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 2432 return (X86_VENDOR_Cyrix); 2433 else if (cpi->cpi_maxeax >= 2) 2434 return (X86_VENDOR_Intel); 2435 break; 2436 } 2437 return (-1); 2438 } 2439 2440 /* 2441 * create a node for the given cpu under the prom root node. 2442 * Also, create a cpu node in the device tree. 2443 */ 2444 static dev_info_t *cpu_nex_devi = NULL; 2445 static kmutex_t cpu_node_lock; 2446 2447 /* 2448 * Called from post_startup() and mp_startup() 2449 */ 2450 void 2451 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 2452 { 2453 dev_info_t *cpu_devi; 2454 int create; 2455 2456 mutex_enter(&cpu_node_lock); 2457 2458 /* 2459 * create a nexus node for all cpus identified as 'cpu_id' under 2460 * the root node. 2461 */ 2462 if (cpu_nex_devi == NULL) { 2463 if (ndi_devi_alloc(ddi_root_node(), "cpus", 2464 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 2465 mutex_exit(&cpu_node_lock); 2466 return; 2467 } 2468 (void) ndi_devi_online(cpu_nex_devi, 0); 2469 } 2470 2471 /* 2472 * create a child node for cpu identified as 'cpu_id' 2473 */ 2474 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 2475 cpu_id); 2476 if (cpu_devi == NULL) { 2477 mutex_exit(&cpu_node_lock); 2478 return; 2479 } 2480 2481 /* device_type */ 2482 2483 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2484 "device_type", "cpu"); 2485 2486 /* reg */ 2487 2488 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2489 "reg", cpu_id); 2490 2491 /* cpu-mhz, and clock-frequency */ 2492 2493 if (cpu_freq > 0) { 2494 long long mul; 2495 2496 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2497 "cpu-mhz", cpu_freq); 2498 2499 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 2500 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2501 "clock-frequency", (int)mul); 2502 } 2503 2504 (void) ndi_devi_online(cpu_devi, 0); 2505 2506 if ((x86_feature & X86_CPUID) == 0) { 2507 mutex_exit(&cpu_node_lock); 2508 return; 2509 } 2510 2511 /* vendor-id */ 2512 2513 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2514 "vendor-id", cpi->cpi_vendorstr); 2515 2516 if (cpi->cpi_maxeax == 0) { 2517 mutex_exit(&cpu_node_lock); 2518 return; 2519 } 2520 2521 /* 2522 * family, model, and step 2523 */ 2524 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2525 "family", CPI_FAMILY(cpi)); 2526 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2527 "cpu-model", CPI_MODEL(cpi)); 2528 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2529 "stepping-id", CPI_STEP(cpi)); 2530 2531 /* type */ 2532 2533 switch (cpi->cpi_vendor) { 2534 case X86_VENDOR_Intel: 2535 create = 1; 2536 break; 2537 default: 2538 create = 0; 2539 break; 2540 } 2541 if (create) 2542 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2543 "type", CPI_TYPE(cpi)); 2544 2545 /* ext-family */ 2546 2547 switch (cpi->cpi_vendor) { 2548 case X86_VENDOR_Intel: 2549 case X86_VENDOR_AMD: 2550 create = cpi->cpi_family >= 0xf; 2551 break; 2552 default: 2553 create = 0; 2554 break; 2555 } 2556 if (create) 2557 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2558 "ext-family", CPI_FAMILY_XTD(cpi)); 2559 2560 /* ext-model */ 2561 2562 switch (cpi->cpi_vendor) { 2563 case X86_VENDOR_Intel: 2564 case X86_VENDOR_AMD: 2565 create = CPI_FAMILY(cpi) == 0xf; 2566 break; 2567 default: 2568 create = 0; 2569 break; 2570 } 2571 if (create) 2572 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2573 "ext-model", CPI_MODEL_XTD(cpi)); 2574 2575 /* generation */ 2576 2577 switch (cpi->cpi_vendor) { 2578 case X86_VENDOR_AMD: 2579 /* 2580 * AMD K5 model 1 was the first part to support this 2581 */ 2582 create = cpi->cpi_xmaxeax >= 0x80000001; 2583 break; 2584 default: 2585 create = 0; 2586 break; 2587 } 2588 if (create) 2589 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2590 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 2591 2592 /* brand-id */ 2593 2594 switch (cpi->cpi_vendor) { 2595 case X86_VENDOR_Intel: 2596 /* 2597 * brand id first appeared on Pentium III Xeon model 8, 2598 * and Celeron model 8 processors and Opteron 2599 */ 2600 create = cpi->cpi_family > 6 || 2601 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 2602 break; 2603 case X86_VENDOR_AMD: 2604 create = cpi->cpi_family >= 0xf; 2605 break; 2606 default: 2607 create = 0; 2608 break; 2609 } 2610 if (create && cpi->cpi_brandid != 0) { 2611 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2612 "brand-id", cpi->cpi_brandid); 2613 } 2614 2615 /* chunks, and apic-id */ 2616 2617 switch (cpi->cpi_vendor) { 2618 case X86_VENDOR_Intel: 2619 case X86_VENDOR_AMD: 2620 /* 2621 * first available on Pentium IV and Opteron (K8) 2622 */ 2623 create = cpi->cpi_family >= 0xf; 2624 break; 2625 default: 2626 create = 0; 2627 break; 2628 } 2629 if (create) { 2630 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2631 "chunks", CPI_CHUNKS(cpi)); 2632 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2633 "apic-id", CPI_APIC_ID(cpi)); 2634 if (cpi->cpi_chipid >= 0) { 2635 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2636 "chip#", cpi->cpi_chipid); 2637 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2638 "clog#", cpi->cpi_clogid); 2639 } 2640 } 2641 2642 /* cpuid-features */ 2643 2644 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2645 "cpuid-features", CPI_FEATURES_EDX(cpi)); 2646 2647 2648 /* cpuid-features-ecx */ 2649 2650 switch (cpi->cpi_vendor) { 2651 case X86_VENDOR_Intel: 2652 create = cpi->cpi_family >= 0xf; 2653 break; 2654 default: 2655 create = 0; 2656 break; 2657 } 2658 if (create) 2659 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2660 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 2661 2662 /* ext-cpuid-features */ 2663 2664 switch (cpi->cpi_vendor) { 2665 case X86_VENDOR_AMD: 2666 case X86_VENDOR_Cyrix: 2667 case X86_VENDOR_TM: 2668 case X86_VENDOR_Centaur: 2669 /* 2670 * The extended cpuid features are not relevant on 2671 * Intel but are available from the AMD K5 model 1 2672 * and most Cyrix GXm and later. 2673 */ 2674 create = cpi->cpi_xmaxeax >= 0x80000001; 2675 break; 2676 default: 2677 create = 0; 2678 break; 2679 } 2680 if (create) 2681 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 2682 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 2683 2684 /* 2685 * Brand String first appeared in Intel Pentium IV, AMD K5 2686 * model 1, and Cyrix GXm. On earlier models we try and 2687 * simulate something similar .. so this string should always 2688 * same -something- about the processor, however lame. 2689 */ 2690 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 2691 "brand-string", cpi->cpi_brandstr); 2692 2693 /* 2694 * Finally, cache and tlb information 2695 */ 2696 switch (x86_which_cacheinfo(cpi)) { 2697 case X86_VENDOR_Intel: 2698 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2699 break; 2700 case X86_VENDOR_Cyrix: 2701 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 2702 break; 2703 case X86_VENDOR_AMD: 2704 amd_cache_info(cpi, cpu_devi); 2705 break; 2706 default: 2707 break; 2708 } 2709 2710 mutex_exit(&cpu_node_lock); 2711 } 2712 2713 struct l2info { 2714 int *l2i_csz; 2715 int *l2i_lsz; 2716 int *l2i_assoc; 2717 int l2i_ret; 2718 }; 2719 2720 /* 2721 * A cacheinfo walker that fetches the size, line-size and associativity 2722 * of the L2 cache 2723 */ 2724 static int 2725 intel_l2cinfo(void *arg, const struct cachetab *ct) 2726 { 2727 struct l2info *l2i = arg; 2728 int *ip; 2729 2730 if (ct->ct_label != l2_cache_str && 2731 ct->ct_label != sl2_cache_str) 2732 return (0); /* not an L2 -- keep walking */ 2733 2734 if ((ip = l2i->l2i_csz) != NULL) 2735 *ip = ct->ct_size; 2736 if ((ip = l2i->l2i_lsz) != NULL) 2737 *ip = ct->ct_line_size; 2738 if ((ip = l2i->l2i_assoc) != NULL) 2739 *ip = ct->ct_assoc; 2740 l2i->l2i_ret = ct->ct_size; 2741 return (1); /* was an L2 -- terminate walk */ 2742 } 2743 2744 static void 2745 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 2746 { 2747 struct cpuid_regs *cp; 2748 uint_t size, assoc; 2749 int *ip; 2750 2751 if (cpi->cpi_xmaxeax < 0x80000006) 2752 return; 2753 cp = &cpi->cpi_extd[6]; 2754 2755 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 2756 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 2757 uint_t cachesz = size * 1024; 2758 2759 2760 if ((ip = l2i->l2i_csz) != NULL) 2761 *ip = cachesz; 2762 if ((ip = l2i->l2i_lsz) != NULL) 2763 *ip = BITX(cp->cp_ecx, 7, 0); 2764 if ((ip = l2i->l2i_assoc) != NULL) 2765 *ip = assoc; 2766 l2i->l2i_ret = cachesz; 2767 } 2768 } 2769 2770 int 2771 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 2772 { 2773 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2774 struct l2info __l2info, *l2i = &__l2info; 2775 2776 l2i->l2i_csz = csz; 2777 l2i->l2i_lsz = lsz; 2778 l2i->l2i_assoc = assoc; 2779 l2i->l2i_ret = -1; 2780 2781 switch (x86_which_cacheinfo(cpi)) { 2782 case X86_VENDOR_Intel: 2783 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2784 break; 2785 case X86_VENDOR_Cyrix: 2786 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 2787 break; 2788 case X86_VENDOR_AMD: 2789 amd_l2cacheinfo(cpi, l2i); 2790 break; 2791 default: 2792 break; 2793 } 2794 return (l2i->l2i_ret); 2795 } 2796