1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/pg.h> 44 #include <sys/fp.h> 45 #include <sys/controlregs.h> 46 #include <sys/auxv_386.h> 47 #include <sys/bitmap.h> 48 #include <sys/memnode.h> 49 50 /* 51 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 52 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 53 * them accordingly. For most modern processors, feature detection occurs here 54 * in pass 1. 55 * 56 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 57 * for the boot CPU and does the basic analysis that the early kernel needs. 58 * x86_feature is set based on the return value of cpuid_pass1() of the boot 59 * CPU. 60 * 61 * Pass 1 includes: 62 * 63 * o Determining vendor/model/family/stepping and setting x86_type and 64 * x86_vendor accordingly. 65 * o Processing the feature flags returned by the cpuid instruction while 66 * applying any workarounds or tricks for the specific processor. 67 * o Mapping the feature flags into Solaris feature bits (X86_*). 68 * o Processing extended feature flags if supported by the processor, 69 * again while applying specific processor knowledge. 70 * o Determining the CMT characteristics of the system. 71 * 72 * Pass 1 is done on non-boot CPUs during their initialization and the results 73 * are used only as a meager attempt at ensuring that all processors within the 74 * system support the same features. 75 * 76 * Pass 2 of cpuid feature analysis happens just at the beginning 77 * of startup(). It just copies in and corrects the remainder 78 * of the cpuid data we depend on: standard cpuid functions that we didn't 79 * need for pass1 feature analysis, and extended cpuid functions beyond the 80 * simple feature processing done in pass1. 81 * 82 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 83 * particular kernel memory allocation has been made available. It creates a 84 * readable brand string based on the data collected in the first two passes. 85 * 86 * Pass 4 of cpuid analysis is invoked after post_startup() when all 87 * the support infrastructure for various hardware features has been 88 * initialized. It determines which processor features will be reported 89 * to userland via the aux vector. 90 * 91 * All passes are executed on all CPUs, but only the boot CPU determines what 92 * features the kernel will use. 93 * 94 * Much of the worst junk in this file is for the support of processors 95 * that didn't really implement the cpuid instruction properly. 96 * 97 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 98 * the pass numbers. Accordingly, changes to the pass code may require changes 99 * to the accessor code. 100 */ 101 102 uint_t x86_feature = 0; 103 uint_t x86_vendor = X86_VENDOR_IntelClone; 104 uint_t x86_type = X86_TYPE_OTHER; 105 106 uint_t pentiumpro_bug4046376; 107 uint_t pentiumpro_bug4064495; 108 109 uint_t enable486; 110 111 /* 112 * This set of strings are for processors rumored to support the cpuid 113 * instruction, and is used by locore.s to figure out how to set x86_vendor 114 */ 115 const char CyrixInstead[] = "CyrixInstead"; 116 117 /* 118 * monitor/mwait info. 119 */ 120 struct mwait_info { 121 size_t mon_min; /* min size to avoid missed wakeups */ 122 size_t mon_max; /* size to avoid false wakeups */ 123 uint32_t support; /* processor support of monitor/mwait */ 124 }; 125 126 /* 127 * These constants determine how many of the elements of the 128 * cpuid we cache in the cpuid_info data structure; the 129 * remaining elements are accessible via the cpuid instruction. 130 */ 131 132 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 133 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 134 135 struct cpuid_info { 136 uint_t cpi_pass; /* last pass completed */ 137 /* 138 * standard function information 139 */ 140 uint_t cpi_maxeax; /* fn 0: %eax */ 141 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 142 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 143 144 uint_t cpi_family; /* fn 1: extended family */ 145 uint_t cpi_model; /* fn 1: extended model */ 146 uint_t cpi_step; /* fn 1: stepping */ 147 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 148 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 149 int cpi_clogid; /* fn 1: %ebx: thread # */ 150 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 151 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 152 uint_t cpi_ncache; /* fn 2: number of elements */ 153 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 154 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 155 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 156 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 157 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 158 /* 159 * extended function information 160 */ 161 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 162 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 163 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 164 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 165 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 166 id_t cpi_coreid; 167 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 168 /* Intel: fn 4: %eax[31-26] */ 169 /* 170 * supported feature information 171 */ 172 uint32_t cpi_support[5]; 173 #define STD_EDX_FEATURES 0 174 #define AMD_EDX_FEATURES 1 175 #define TM_EDX_FEATURES 2 176 #define STD_ECX_FEATURES 3 177 #define AMD_ECX_FEATURES 4 178 /* 179 * Synthesized information, where known. 180 */ 181 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 182 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 183 uint32_t cpi_socket; /* Chip package/socket type */ 184 185 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 186 }; 187 188 189 static struct cpuid_info cpuid_info0; 190 191 /* 192 * These bit fields are defined by the Intel Application Note AP-485 193 * "Intel Processor Identification and the CPUID Instruction" 194 */ 195 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 196 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 197 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 198 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 199 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 200 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 201 202 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 203 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 204 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 205 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 206 207 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 208 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 209 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 210 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 211 212 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 213 #define CPI_XMAXEAX_MAX 0x80000100 214 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 215 216 /* 217 * Function 4 (Deterministic Cache Parameters) macros 218 * Defined by Intel Application Note AP-485 219 */ 220 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 221 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 222 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 223 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 224 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 225 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 226 227 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 228 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 229 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 230 231 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 232 233 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 234 235 236 /* 237 * A couple of shorthand macros to identify "later" P6-family chips 238 * like the Pentium M and Core. First, the "older" P6-based stuff 239 * (loosely defined as "pre-Pentium-4"): 240 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 241 */ 242 243 #define IS_LEGACY_P6(cpi) ( \ 244 cpi->cpi_family == 6 && \ 245 (cpi->cpi_model == 1 || \ 246 cpi->cpi_model == 3 || \ 247 cpi->cpi_model == 5 || \ 248 cpi->cpi_model == 6 || \ 249 cpi->cpi_model == 7 || \ 250 cpi->cpi_model == 8 || \ 251 cpi->cpi_model == 0xA || \ 252 cpi->cpi_model == 0xB) \ 253 ) 254 255 /* A "new F6" is everything with family 6 that's not the above */ 256 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 257 258 /* 259 * AMD family 0xf socket types. 260 * First index is 0 for revs B thru E, 1 for F and G. 261 * Second index by (model & 0x3) 262 */ 263 static uint32_t amd_skts[2][4] = { 264 { 265 X86_SOCKET_754, /* 0b00 */ 266 X86_SOCKET_940, /* 0b01 */ 267 X86_SOCKET_754, /* 0b10 */ 268 X86_SOCKET_939 /* 0b11 */ 269 }, 270 { 271 X86_SOCKET_S1g1, /* 0b00 */ 272 X86_SOCKET_F1207, /* 0b01 */ 273 X86_SOCKET_UNKNOWN, /* 0b10 */ 274 X86_SOCKET_AM2 /* 0b11 */ 275 } 276 }; 277 278 /* 279 * Table for mapping AMD Family 0xf model/stepping combination to 280 * chip "revision" and socket type. Only rm_family 0xf is used at the 281 * moment, but AMD family 0x10 will extend the exsiting revision names 282 * so will likely also use this table. 283 * 284 * The first member of this array that matches a given family, extended model 285 * plus model range, and stepping range will be considered a match. 286 */ 287 static const struct amd_rev_mapent { 288 uint_t rm_family; 289 uint_t rm_modello; 290 uint_t rm_modelhi; 291 uint_t rm_steplo; 292 uint_t rm_stephi; 293 uint32_t rm_chiprev; 294 const char *rm_chiprevstr; 295 int rm_sktidx; 296 } amd_revmap[] = { 297 /* 298 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 299 */ 300 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, 301 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 }, 302 /* 303 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 304 */ 305 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 }, 306 /* 307 * Rev CG is the rest of extended model 0x0 - i.e., everything 308 * but the rev B and C0 combinations covered above. 309 */ 310 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 }, 311 /* 312 * Rev D has extended model 0x1. 313 */ 314 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 }, 315 /* 316 * Rev E has extended model 0x2. 317 * Extended model 0x3 is unused but available to grow into. 318 */ 319 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 }, 320 /* 321 * Rev F has extended models 0x4 and 0x5. 322 */ 323 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 }, 324 /* 325 * Rev G has extended model 0x6. 326 */ 327 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 }, 328 }; 329 330 /* 331 * Info for monitor/mwait idle loop. 332 * 333 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 334 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 335 * 2006. 336 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 337 * Documentation Updates" #33633, Rev 2.05, December 2006. 338 */ 339 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 340 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 341 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 342 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 343 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 344 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 345 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 346 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 347 /* 348 * Number of sub-cstates for a given c-state. 349 */ 350 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 351 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 352 353 static void 354 synth_amd_info(struct cpuid_info *cpi) 355 { 356 const struct amd_rev_mapent *rmp; 357 uint_t family, model, step; 358 int i; 359 360 /* 361 * Currently only AMD family 0xf uses these fields. 362 */ 363 if (cpi->cpi_family != 0xf) 364 return; 365 366 family = cpi->cpi_family; 367 model = cpi->cpi_model; 368 step = cpi->cpi_step; 369 370 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 371 i++, rmp++) { 372 if (family == rmp->rm_family && 373 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 374 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 375 cpi->cpi_chiprev = rmp->rm_chiprev; 376 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 377 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 378 return; 379 } 380 } 381 } 382 383 static void 384 synth_info(struct cpuid_info *cpi) 385 { 386 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 387 cpi->cpi_chiprevstr = "Unknown"; 388 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 389 390 switch (cpi->cpi_vendor) { 391 case X86_VENDOR_AMD: 392 synth_amd_info(cpi); 393 break; 394 395 default: 396 break; 397 398 } 399 } 400 401 /* 402 * Apply up various platform-dependent restrictions where the 403 * underlying platform restrictions mean the CPU can be marked 404 * as less capable than its cpuid instruction would imply. 405 */ 406 407 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 408 409 /* 410 * Some undocumented ways of patching the results of the cpuid 411 * instruction to permit running Solaris 10 on future cpus that 412 * we don't currently support. Could be set to non-zero values 413 * via settings in eeprom. 414 */ 415 416 uint32_t cpuid_feature_ecx_include; 417 uint32_t cpuid_feature_ecx_exclude; 418 uint32_t cpuid_feature_edx_include; 419 uint32_t cpuid_feature_edx_exclude; 420 421 void 422 cpuid_alloc_space(cpu_t *cpu) 423 { 424 /* 425 * By convention, cpu0 is the boot cpu, which is set up 426 * before memory allocation is available. All other cpus get 427 * their cpuid_info struct allocated here. 428 */ 429 ASSERT(cpu->cpu_id != 0); 430 cpu->cpu_m.mcpu_cpi = 431 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 432 } 433 434 void 435 cpuid_free_space(cpu_t *cpu) 436 { 437 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 438 int i; 439 440 ASSERT(cpu->cpu_id != 0); 441 442 /* 443 * Free up any function 4 related dynamic storage 444 */ 445 for (i = 1; i < cpi->cpi_std_4_size; i++) 446 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 447 if (cpi->cpi_std_4_size > 0) 448 kmem_free(cpi->cpi_std_4, 449 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 450 451 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 452 } 453 454 uint_t 455 cpuid_pass1(cpu_t *cpu) 456 { 457 uint32_t mask_ecx, mask_edx; 458 uint_t feature = X86_CPUID; 459 struct cpuid_info *cpi; 460 struct cpuid_regs *cp; 461 int xcpuid; 462 463 464 /* 465 * Space statically allocated for cpu0, ensure pointer is set 466 */ 467 if (cpu->cpu_id == 0) 468 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 469 cpi = cpu->cpu_m.mcpu_cpi; 470 ASSERT(cpi != NULL); 471 cp = &cpi->cpi_std[0]; 472 cp->cp_eax = 0; 473 cpi->cpi_maxeax = __cpuid_insn(cp); 474 { 475 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 476 *iptr++ = cp->cp_ebx; 477 *iptr++ = cp->cp_edx; 478 *iptr++ = cp->cp_ecx; 479 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 480 } 481 482 /* 483 * Map the vendor string to a type code 484 */ 485 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 486 cpi->cpi_vendor = X86_VENDOR_Intel; 487 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 488 cpi->cpi_vendor = X86_VENDOR_AMD; 489 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 490 cpi->cpi_vendor = X86_VENDOR_TM; 491 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 492 /* 493 * CyrixInstead is a variable used by the Cyrix detection code 494 * in locore. 495 */ 496 cpi->cpi_vendor = X86_VENDOR_Cyrix; 497 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 498 cpi->cpi_vendor = X86_VENDOR_UMC; 499 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 500 cpi->cpi_vendor = X86_VENDOR_NexGen; 501 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 502 cpi->cpi_vendor = X86_VENDOR_Centaur; 503 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 504 cpi->cpi_vendor = X86_VENDOR_Rise; 505 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 506 cpi->cpi_vendor = X86_VENDOR_SiS; 507 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 508 cpi->cpi_vendor = X86_VENDOR_NSC; 509 else 510 cpi->cpi_vendor = X86_VENDOR_IntelClone; 511 512 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 513 514 /* 515 * Limit the range in case of weird hardware 516 */ 517 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 518 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 519 if (cpi->cpi_maxeax < 1) 520 goto pass1_done; 521 522 cp = &cpi->cpi_std[1]; 523 cp->cp_eax = 1; 524 (void) __cpuid_insn(cp); 525 526 /* 527 * Extract identifying constants for easy access. 528 */ 529 cpi->cpi_model = CPI_MODEL(cpi); 530 cpi->cpi_family = CPI_FAMILY(cpi); 531 532 if (cpi->cpi_family == 0xf) 533 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 534 535 /* 536 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 537 * Intel, and presumably everyone else, uses model == 0xf, as 538 * one would expect (max value means possible overflow). Sigh. 539 */ 540 541 switch (cpi->cpi_vendor) { 542 case X86_VENDOR_AMD: 543 if (CPI_FAMILY(cpi) == 0xf) 544 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 545 break; 546 default: 547 if (cpi->cpi_model == 0xf) 548 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 549 break; 550 } 551 552 cpi->cpi_step = CPI_STEP(cpi); 553 cpi->cpi_brandid = CPI_BRANDID(cpi); 554 555 /* 556 * *default* assumptions: 557 * - believe %edx feature word 558 * - ignore %ecx feature word 559 * - 32-bit virtual and physical addressing 560 */ 561 mask_edx = 0xffffffff; 562 mask_ecx = 0; 563 564 cpi->cpi_pabits = cpi->cpi_vabits = 32; 565 566 switch (cpi->cpi_vendor) { 567 case X86_VENDOR_Intel: 568 if (cpi->cpi_family == 5) 569 x86_type = X86_TYPE_P5; 570 else if (IS_LEGACY_P6(cpi)) { 571 x86_type = X86_TYPE_P6; 572 pentiumpro_bug4046376 = 1; 573 pentiumpro_bug4064495 = 1; 574 /* 575 * Clear the SEP bit when it was set erroneously 576 */ 577 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 578 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 579 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 580 x86_type = X86_TYPE_P4; 581 /* 582 * We don't currently depend on any of the %ecx 583 * features until Prescott, so we'll only check 584 * this from P4 onwards. We might want to revisit 585 * that idea later. 586 */ 587 mask_ecx = 0xffffffff; 588 } else if (cpi->cpi_family > 0xf) 589 mask_ecx = 0xffffffff; 590 break; 591 case X86_VENDOR_IntelClone: 592 default: 593 break; 594 case X86_VENDOR_AMD: 595 #if defined(OPTERON_ERRATUM_108) 596 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 597 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 598 cpi->cpi_model = 0xc; 599 } else 600 #endif 601 if (cpi->cpi_family == 5) { 602 /* 603 * AMD K5 and K6 604 * 605 * These CPUs have an incomplete implementation 606 * of MCA/MCE which we mask away. 607 */ 608 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 609 610 /* 611 * Model 0 uses the wrong (APIC) bit 612 * to indicate PGE. Fix it here. 613 */ 614 if (cpi->cpi_model == 0) { 615 if (cp->cp_edx & 0x200) { 616 cp->cp_edx &= ~0x200; 617 cp->cp_edx |= CPUID_INTC_EDX_PGE; 618 } 619 } 620 621 /* 622 * Early models had problems w/ MMX; disable. 623 */ 624 if (cpi->cpi_model < 6) 625 mask_edx &= ~CPUID_INTC_EDX_MMX; 626 } 627 628 /* 629 * For newer families, SSE3 and CX16, at least, are valid; 630 * enable all 631 */ 632 if (cpi->cpi_family >= 0xf) 633 mask_ecx = 0xffffffff; 634 break; 635 case X86_VENDOR_TM: 636 /* 637 * workaround the NT workaround in CMS 4.1 638 */ 639 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 640 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 641 cp->cp_edx |= CPUID_INTC_EDX_CX8; 642 break; 643 case X86_VENDOR_Centaur: 644 /* 645 * workaround the NT workarounds again 646 */ 647 if (cpi->cpi_family == 6) 648 cp->cp_edx |= CPUID_INTC_EDX_CX8; 649 break; 650 case X86_VENDOR_Cyrix: 651 /* 652 * We rely heavily on the probing in locore 653 * to actually figure out what parts, if any, 654 * of the Cyrix cpuid instruction to believe. 655 */ 656 switch (x86_type) { 657 case X86_TYPE_CYRIX_486: 658 mask_edx = 0; 659 break; 660 case X86_TYPE_CYRIX_6x86: 661 mask_edx = 0; 662 break; 663 case X86_TYPE_CYRIX_6x86L: 664 mask_edx = 665 CPUID_INTC_EDX_DE | 666 CPUID_INTC_EDX_CX8; 667 break; 668 case X86_TYPE_CYRIX_6x86MX: 669 mask_edx = 670 CPUID_INTC_EDX_DE | 671 CPUID_INTC_EDX_MSR | 672 CPUID_INTC_EDX_CX8 | 673 CPUID_INTC_EDX_PGE | 674 CPUID_INTC_EDX_CMOV | 675 CPUID_INTC_EDX_MMX; 676 break; 677 case X86_TYPE_CYRIX_GXm: 678 mask_edx = 679 CPUID_INTC_EDX_MSR | 680 CPUID_INTC_EDX_CX8 | 681 CPUID_INTC_EDX_CMOV | 682 CPUID_INTC_EDX_MMX; 683 break; 684 case X86_TYPE_CYRIX_MediaGX: 685 break; 686 case X86_TYPE_CYRIX_MII: 687 case X86_TYPE_VIA_CYRIX_III: 688 mask_edx = 689 CPUID_INTC_EDX_DE | 690 CPUID_INTC_EDX_TSC | 691 CPUID_INTC_EDX_MSR | 692 CPUID_INTC_EDX_CX8 | 693 CPUID_INTC_EDX_PGE | 694 CPUID_INTC_EDX_CMOV | 695 CPUID_INTC_EDX_MMX; 696 break; 697 default: 698 break; 699 } 700 break; 701 } 702 703 /* 704 * Now we've figured out the masks that determine 705 * which bits we choose to believe, apply the masks 706 * to the feature words, then map the kernel's view 707 * of these feature words into its feature word. 708 */ 709 cp->cp_edx &= mask_edx; 710 cp->cp_ecx &= mask_ecx; 711 712 /* 713 * apply any platform restrictions (we don't call this 714 * immediately after __cpuid_insn here, because we need the 715 * workarounds applied above first) 716 */ 717 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 718 719 /* 720 * fold in overrides from the "eeprom" mechanism 721 */ 722 cp->cp_edx |= cpuid_feature_edx_include; 723 cp->cp_edx &= ~cpuid_feature_edx_exclude; 724 725 cp->cp_ecx |= cpuid_feature_ecx_include; 726 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 727 728 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 729 feature |= X86_LARGEPAGE; 730 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 731 feature |= X86_TSC; 732 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 733 feature |= X86_MSR; 734 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 735 feature |= X86_MTRR; 736 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 737 feature |= X86_PGE; 738 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 739 feature |= X86_CMOV; 740 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 741 feature |= X86_MMX; 742 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 743 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 744 feature |= X86_MCA; 745 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 746 feature |= X86_PAE; 747 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 748 feature |= X86_CX8; 749 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 750 feature |= X86_CX16; 751 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 752 feature |= X86_PAT; 753 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 754 feature |= X86_SEP; 755 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 756 /* 757 * In our implementation, fxsave/fxrstor 758 * are prerequisites before we'll even 759 * try and do SSE things. 760 */ 761 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 762 feature |= X86_SSE; 763 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 764 feature |= X86_SSE2; 765 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 766 feature |= X86_SSE3; 767 } 768 if (cp->cp_edx & CPUID_INTC_EDX_DE) 769 feature |= X86_DE; 770 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 771 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 772 feature |= X86_MWAIT; 773 } 774 775 if (feature & X86_PAE) 776 cpi->cpi_pabits = 36; 777 778 /* 779 * Hyperthreading configuration is slightly tricky on Intel 780 * and pure clones, and even trickier on AMD. 781 * 782 * (AMD chose to set the HTT bit on their CMP processors, 783 * even though they're not actually hyperthreaded. Thus it 784 * takes a bit more work to figure out what's really going 785 * on ... see the handling of the CMP_LGCY bit below) 786 */ 787 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 788 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 789 if (cpi->cpi_ncpu_per_chip > 1) 790 feature |= X86_HTT; 791 } else { 792 cpi->cpi_ncpu_per_chip = 1; 793 } 794 795 /* 796 * Work on the "extended" feature information, doing 797 * some basic initialization for cpuid_pass2() 798 */ 799 xcpuid = 0; 800 switch (cpi->cpi_vendor) { 801 case X86_VENDOR_Intel: 802 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 803 xcpuid++; 804 break; 805 case X86_VENDOR_AMD: 806 if (cpi->cpi_family > 5 || 807 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 808 xcpuid++; 809 break; 810 case X86_VENDOR_Cyrix: 811 /* 812 * Only these Cyrix CPUs are -known- to support 813 * extended cpuid operations. 814 */ 815 if (x86_type == X86_TYPE_VIA_CYRIX_III || 816 x86_type == X86_TYPE_CYRIX_GXm) 817 xcpuid++; 818 break; 819 case X86_VENDOR_Centaur: 820 case X86_VENDOR_TM: 821 default: 822 xcpuid++; 823 break; 824 } 825 826 if (xcpuid) { 827 cp = &cpi->cpi_extd[0]; 828 cp->cp_eax = 0x80000000; 829 cpi->cpi_xmaxeax = __cpuid_insn(cp); 830 } 831 832 if (cpi->cpi_xmaxeax & 0x80000000) { 833 834 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 835 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 836 837 switch (cpi->cpi_vendor) { 838 case X86_VENDOR_Intel: 839 case X86_VENDOR_AMD: 840 if (cpi->cpi_xmaxeax < 0x80000001) 841 break; 842 cp = &cpi->cpi_extd[1]; 843 cp->cp_eax = 0x80000001; 844 (void) __cpuid_insn(cp); 845 846 if (cpi->cpi_vendor == X86_VENDOR_AMD && 847 cpi->cpi_family == 5 && 848 cpi->cpi_model == 6 && 849 cpi->cpi_step == 6) { 850 /* 851 * K6 model 6 uses bit 10 to indicate SYSC 852 * Later models use bit 11. Fix it here. 853 */ 854 if (cp->cp_edx & 0x400) { 855 cp->cp_edx &= ~0x400; 856 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 857 } 858 } 859 860 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 861 862 /* 863 * Compute the additions to the kernel's feature word. 864 */ 865 if (cp->cp_edx & CPUID_AMD_EDX_NX) 866 feature |= X86_NX; 867 868 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 869 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 870 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 871 feature |= X86_SSE4A; 872 873 /* 874 * If both the HTT and CMP_LGCY bits are set, 875 * then we're not actually HyperThreaded. Read 876 * "AMD CPUID Specification" for more details. 877 */ 878 if (cpi->cpi_vendor == X86_VENDOR_AMD && 879 (feature & X86_HTT) && 880 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 881 feature &= ~X86_HTT; 882 feature |= X86_CMP; 883 } 884 #if defined(__amd64) 885 /* 886 * It's really tricky to support syscall/sysret in 887 * the i386 kernel; we rely on sysenter/sysexit 888 * instead. In the amd64 kernel, things are -way- 889 * better. 890 */ 891 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 892 feature |= X86_ASYSC; 893 894 /* 895 * While we're thinking about system calls, note 896 * that AMD processors don't support sysenter 897 * in long mode at all, so don't try to program them. 898 */ 899 if (x86_vendor == X86_VENDOR_AMD) 900 feature &= ~X86_SEP; 901 #endif 902 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 903 feature |= X86_TSCP; 904 break; 905 default: 906 break; 907 } 908 909 /* 910 * Get CPUID data about processor cores and hyperthreads. 911 */ 912 switch (cpi->cpi_vendor) { 913 case X86_VENDOR_Intel: 914 if (cpi->cpi_maxeax >= 4) { 915 cp = &cpi->cpi_std[4]; 916 cp->cp_eax = 4; 917 cp->cp_ecx = 0; 918 (void) __cpuid_insn(cp); 919 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 920 } 921 /*FALLTHROUGH*/ 922 case X86_VENDOR_AMD: 923 if (cpi->cpi_xmaxeax < 0x80000008) 924 break; 925 cp = &cpi->cpi_extd[8]; 926 cp->cp_eax = 0x80000008; 927 (void) __cpuid_insn(cp); 928 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 929 930 /* 931 * Virtual and physical address limits from 932 * cpuid override previously guessed values. 933 */ 934 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 935 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 936 break; 937 default: 938 break; 939 } 940 941 /* 942 * Derive the number of cores per chip 943 */ 944 switch (cpi->cpi_vendor) { 945 case X86_VENDOR_Intel: 946 if (cpi->cpi_maxeax < 4) { 947 cpi->cpi_ncore_per_chip = 1; 948 break; 949 } else { 950 cpi->cpi_ncore_per_chip = 951 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 952 } 953 break; 954 case X86_VENDOR_AMD: 955 if (cpi->cpi_xmaxeax < 0x80000008) { 956 cpi->cpi_ncore_per_chip = 1; 957 break; 958 } else { 959 cpi->cpi_ncore_per_chip = 960 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 961 } 962 break; 963 default: 964 cpi->cpi_ncore_per_chip = 1; 965 break; 966 } 967 } 968 969 /* 970 * If more than one core, then this processor is CMP. 971 */ 972 if (cpi->cpi_ncore_per_chip > 1) 973 feature |= X86_CMP; 974 975 /* 976 * If the number of cores is the same as the number 977 * of CPUs, then we cannot have HyperThreading. 978 */ 979 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 980 feature &= ~X86_HTT; 981 982 if ((feature & (X86_HTT | X86_CMP)) == 0) { 983 /* 984 * Single-core single-threaded processors. 985 */ 986 cpi->cpi_chipid = -1; 987 cpi->cpi_clogid = 0; 988 cpi->cpi_coreid = cpu->cpu_id; 989 } else if (cpi->cpi_ncpu_per_chip > 1) { 990 uint_t i; 991 uint_t chipid_shift = 0; 992 uint_t coreid_shift = 0; 993 uint_t apic_id = CPI_APIC_ID(cpi); 994 995 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 996 chipid_shift++; 997 cpi->cpi_chipid = apic_id >> chipid_shift; 998 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 999 1000 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1001 if (feature & X86_CMP) { 1002 /* 1003 * Multi-core (and possibly multi-threaded) 1004 * processors. 1005 */ 1006 uint_t ncpu_per_core; 1007 if (cpi->cpi_ncore_per_chip == 1) 1008 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1009 else if (cpi->cpi_ncore_per_chip > 1) 1010 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1011 cpi->cpi_ncore_per_chip; 1012 /* 1013 * 8bit APIC IDs on dual core Pentiums 1014 * look like this: 1015 * 1016 * +-----------------------+------+------+ 1017 * | Physical Package ID | MC | HT | 1018 * +-----------------------+------+------+ 1019 * <------- chipid --------> 1020 * <------- coreid ---------------> 1021 * <--- clogid --> 1022 * 1023 * Where the number of bits necessary to 1024 * represent MC and HT fields together equals 1025 * to the minimum number of bits necessary to 1026 * store the value of cpi->cpi_ncpu_per_chip. 1027 * Of those bits, the MC part uses the number 1028 * of bits necessary to store the value of 1029 * cpi->cpi_ncore_per_chip. 1030 */ 1031 for (i = 1; i < ncpu_per_core; i <<= 1) 1032 coreid_shift++; 1033 cpi->cpi_coreid = apic_id >> coreid_shift; 1034 } else if (feature & X86_HTT) { 1035 /* 1036 * Single-core multi-threaded processors. 1037 */ 1038 cpi->cpi_coreid = cpi->cpi_chipid; 1039 } 1040 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1041 /* 1042 * AMD currently only has dual-core processors with 1043 * single-threaded cores. If they ever release 1044 * multi-threaded processors, then this code 1045 * will have to be updated. 1046 */ 1047 cpi->cpi_coreid = cpu->cpu_id; 1048 } else { 1049 /* 1050 * All other processors are currently 1051 * assumed to have single cores. 1052 */ 1053 cpi->cpi_coreid = cpi->cpi_chipid; 1054 } 1055 } 1056 1057 /* 1058 * Synthesize chip "revision" and socket type 1059 */ 1060 synth_info(cpi); 1061 1062 pass1_done: 1063 cpi->cpi_pass = 1; 1064 return (feature); 1065 } 1066 1067 /* 1068 * Make copies of the cpuid table entries we depend on, in 1069 * part for ease of parsing now, in part so that we have only 1070 * one place to correct any of it, in part for ease of 1071 * later export to userland, and in part so we can look at 1072 * this stuff in a crash dump. 1073 */ 1074 1075 /*ARGSUSED*/ 1076 void 1077 cpuid_pass2(cpu_t *cpu) 1078 { 1079 uint_t n, nmax; 1080 int i; 1081 struct cpuid_regs *cp; 1082 uint8_t *dp; 1083 uint32_t *iptr; 1084 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1085 1086 ASSERT(cpi->cpi_pass == 1); 1087 1088 if (cpi->cpi_maxeax < 1) 1089 goto pass2_done; 1090 1091 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1092 nmax = NMAX_CPI_STD; 1093 /* 1094 * (We already handled n == 0 and n == 1 in pass 1) 1095 */ 1096 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1097 cp->cp_eax = n; 1098 1099 /* 1100 * CPUID function 4 expects %ecx to be initialized 1101 * with an index which indicates which cache to return 1102 * information about. The OS is expected to call function 4 1103 * with %ecx set to 0, 1, 2, ... until it returns with 1104 * EAX[4:0] set to 0, which indicates there are no more 1105 * caches. 1106 * 1107 * Here, populate cpi_std[4] with the information returned by 1108 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1109 * when dynamic memory allocation becomes available. 1110 * 1111 * Note: we need to explicitly initialize %ecx here, since 1112 * function 4 may have been previously invoked. 1113 */ 1114 if (n == 4) 1115 cp->cp_ecx = 0; 1116 1117 (void) __cpuid_insn(cp); 1118 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1119 switch (n) { 1120 case 2: 1121 /* 1122 * "the lower 8 bits of the %eax register 1123 * contain a value that identifies the number 1124 * of times the cpuid [instruction] has to be 1125 * executed to obtain a complete image of the 1126 * processor's caching systems." 1127 * 1128 * How *do* they make this stuff up? 1129 */ 1130 cpi->cpi_ncache = sizeof (*cp) * 1131 BITX(cp->cp_eax, 7, 0); 1132 if (cpi->cpi_ncache == 0) 1133 break; 1134 cpi->cpi_ncache--; /* skip count byte */ 1135 1136 /* 1137 * Well, for now, rather than attempt to implement 1138 * this slightly dubious algorithm, we just look 1139 * at the first 15 .. 1140 */ 1141 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1142 cpi->cpi_ncache = sizeof (*cp) - 1; 1143 1144 dp = cpi->cpi_cacheinfo; 1145 if (BITX(cp->cp_eax, 31, 31) == 0) { 1146 uint8_t *p = (void *)&cp->cp_eax; 1147 for (i = 1; i < 3; i++) 1148 if (p[i] != 0) 1149 *dp++ = p[i]; 1150 } 1151 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1152 uint8_t *p = (void *)&cp->cp_ebx; 1153 for (i = 0; i < 4; i++) 1154 if (p[i] != 0) 1155 *dp++ = p[i]; 1156 } 1157 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1158 uint8_t *p = (void *)&cp->cp_ecx; 1159 for (i = 0; i < 4; i++) 1160 if (p[i] != 0) 1161 *dp++ = p[i]; 1162 } 1163 if (BITX(cp->cp_edx, 31, 31) == 0) { 1164 uint8_t *p = (void *)&cp->cp_edx; 1165 for (i = 0; i < 4; i++) 1166 if (p[i] != 0) 1167 *dp++ = p[i]; 1168 } 1169 break; 1170 1171 case 3: /* Processor serial number, if PSN supported */ 1172 break; 1173 1174 case 4: /* Deterministic cache parameters */ 1175 break; 1176 1177 case 5: /* Monitor/Mwait parameters */ 1178 1179 /* 1180 * check cpi_mwait.support which was set in cpuid_pass1 1181 */ 1182 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1183 break; 1184 1185 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1186 cpi->cpi_mwait.mon_max = (size_t)MWAIT_SIZE_MAX(cpi); 1187 if (MWAIT_EXTENSION(cpi)) { 1188 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1189 if (MWAIT_INT_ENABLE(cpi)) 1190 cpi->cpi_mwait.support |= 1191 MWAIT_ECX_INT_ENABLE; 1192 } 1193 break; 1194 default: 1195 break; 1196 } 1197 } 1198 1199 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1200 goto pass2_done; 1201 1202 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1203 nmax = NMAX_CPI_EXTD; 1204 /* 1205 * Copy the extended properties, fixing them as we go. 1206 * (We already handled n == 0 and n == 1 in pass 1) 1207 */ 1208 iptr = (void *)cpi->cpi_brandstr; 1209 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1210 cp->cp_eax = 0x80000000 + n; 1211 (void) __cpuid_insn(cp); 1212 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1213 switch (n) { 1214 case 2: 1215 case 3: 1216 case 4: 1217 /* 1218 * Extract the brand string 1219 */ 1220 *iptr++ = cp->cp_eax; 1221 *iptr++ = cp->cp_ebx; 1222 *iptr++ = cp->cp_ecx; 1223 *iptr++ = cp->cp_edx; 1224 break; 1225 case 5: 1226 switch (cpi->cpi_vendor) { 1227 case X86_VENDOR_AMD: 1228 /* 1229 * The Athlon and Duron were the first 1230 * parts to report the sizes of the 1231 * TLB for large pages. Before then, 1232 * we don't trust the data. 1233 */ 1234 if (cpi->cpi_family < 6 || 1235 (cpi->cpi_family == 6 && 1236 cpi->cpi_model < 1)) 1237 cp->cp_eax = 0; 1238 break; 1239 default: 1240 break; 1241 } 1242 break; 1243 case 6: 1244 switch (cpi->cpi_vendor) { 1245 case X86_VENDOR_AMD: 1246 /* 1247 * The Athlon and Duron were the first 1248 * AMD parts with L2 TLB's. 1249 * Before then, don't trust the data. 1250 */ 1251 if (cpi->cpi_family < 6 || 1252 cpi->cpi_family == 6 && 1253 cpi->cpi_model < 1) 1254 cp->cp_eax = cp->cp_ebx = 0; 1255 /* 1256 * AMD Duron rev A0 reports L2 1257 * cache size incorrectly as 1K 1258 * when it is really 64K 1259 */ 1260 if (cpi->cpi_family == 6 && 1261 cpi->cpi_model == 3 && 1262 cpi->cpi_step == 0) { 1263 cp->cp_ecx &= 0xffff; 1264 cp->cp_ecx |= 0x400000; 1265 } 1266 break; 1267 case X86_VENDOR_Cyrix: /* VIA C3 */ 1268 /* 1269 * VIA C3 processors are a bit messed 1270 * up w.r.t. encoding cache sizes in %ecx 1271 */ 1272 if (cpi->cpi_family != 6) 1273 break; 1274 /* 1275 * model 7 and 8 were incorrectly encoded 1276 * 1277 * xxx is model 8 really broken? 1278 */ 1279 if (cpi->cpi_model == 7 || 1280 cpi->cpi_model == 8) 1281 cp->cp_ecx = 1282 BITX(cp->cp_ecx, 31, 24) << 16 | 1283 BITX(cp->cp_ecx, 23, 16) << 12 | 1284 BITX(cp->cp_ecx, 15, 8) << 8 | 1285 BITX(cp->cp_ecx, 7, 0); 1286 /* 1287 * model 9 stepping 1 has wrong associativity 1288 */ 1289 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1290 cp->cp_ecx |= 8 << 12; 1291 break; 1292 case X86_VENDOR_Intel: 1293 /* 1294 * Extended L2 Cache features function. 1295 * First appeared on Prescott. 1296 */ 1297 default: 1298 break; 1299 } 1300 break; 1301 default: 1302 break; 1303 } 1304 } 1305 1306 pass2_done: 1307 cpi->cpi_pass = 2; 1308 } 1309 1310 static const char * 1311 intel_cpubrand(const struct cpuid_info *cpi) 1312 { 1313 int i; 1314 1315 if ((x86_feature & X86_CPUID) == 0 || 1316 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1317 return ("i486"); 1318 1319 switch (cpi->cpi_family) { 1320 case 5: 1321 return ("Intel Pentium(r)"); 1322 case 6: 1323 switch (cpi->cpi_model) { 1324 uint_t celeron, xeon; 1325 const struct cpuid_regs *cp; 1326 case 0: 1327 case 1: 1328 case 2: 1329 return ("Intel Pentium(r) Pro"); 1330 case 3: 1331 case 4: 1332 return ("Intel Pentium(r) II"); 1333 case 6: 1334 return ("Intel Celeron(r)"); 1335 case 5: 1336 case 7: 1337 celeron = xeon = 0; 1338 cp = &cpi->cpi_std[2]; /* cache info */ 1339 1340 for (i = 1; i < 3; i++) { 1341 uint_t tmp; 1342 1343 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1344 if (tmp == 0x40) 1345 celeron++; 1346 if (tmp >= 0x44 && tmp <= 0x45) 1347 xeon++; 1348 } 1349 1350 for (i = 0; i < 2; i++) { 1351 uint_t tmp; 1352 1353 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1354 if (tmp == 0x40) 1355 celeron++; 1356 else if (tmp >= 0x44 && tmp <= 0x45) 1357 xeon++; 1358 } 1359 1360 for (i = 0; i < 4; i++) { 1361 uint_t tmp; 1362 1363 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1364 if (tmp == 0x40) 1365 celeron++; 1366 else if (tmp >= 0x44 && tmp <= 0x45) 1367 xeon++; 1368 } 1369 1370 for (i = 0; i < 4; i++) { 1371 uint_t tmp; 1372 1373 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1374 if (tmp == 0x40) 1375 celeron++; 1376 else if (tmp >= 0x44 && tmp <= 0x45) 1377 xeon++; 1378 } 1379 1380 if (celeron) 1381 return ("Intel Celeron(r)"); 1382 if (xeon) 1383 return (cpi->cpi_model == 5 ? 1384 "Intel Pentium(r) II Xeon(tm)" : 1385 "Intel Pentium(r) III Xeon(tm)"); 1386 return (cpi->cpi_model == 5 ? 1387 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1388 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1389 default: 1390 break; 1391 } 1392 default: 1393 break; 1394 } 1395 1396 /* BrandID is present if the field is nonzero */ 1397 if (cpi->cpi_brandid != 0) { 1398 static const struct { 1399 uint_t bt_bid; 1400 const char *bt_str; 1401 } brand_tbl[] = { 1402 { 0x1, "Intel(r) Celeron(r)" }, 1403 { 0x2, "Intel(r) Pentium(r) III" }, 1404 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1405 { 0x4, "Intel(r) Pentium(r) III" }, 1406 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1407 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1408 { 0x8, "Intel(r) Pentium(r) 4" }, 1409 { 0x9, "Intel(r) Pentium(r) 4" }, 1410 { 0xa, "Intel(r) Celeron(r)" }, 1411 { 0xb, "Intel(r) Xeon(tm)" }, 1412 { 0xc, "Intel(r) Xeon(tm) MP" }, 1413 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1414 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1415 { 0x11, "Mobile Genuine Intel(r)" }, 1416 { 0x12, "Intel(r) Celeron(r) M" }, 1417 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1418 { 0x14, "Intel(r) Celeron(r)" }, 1419 { 0x15, "Mobile Genuine Intel(r)" }, 1420 { 0x16, "Intel(r) Pentium(r) M" }, 1421 { 0x17, "Mobile Intel(r) Celeron(r)" } 1422 }; 1423 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1424 uint_t sgn; 1425 1426 sgn = (cpi->cpi_family << 8) | 1427 (cpi->cpi_model << 4) | cpi->cpi_step; 1428 1429 for (i = 0; i < btblmax; i++) 1430 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1431 break; 1432 if (i < btblmax) { 1433 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1434 return ("Intel(r) Celeron(r)"); 1435 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1436 return ("Intel(r) Xeon(tm) MP"); 1437 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1438 return ("Intel(r) Xeon(tm)"); 1439 return (brand_tbl[i].bt_str); 1440 } 1441 } 1442 1443 return (NULL); 1444 } 1445 1446 static const char * 1447 amd_cpubrand(const struct cpuid_info *cpi) 1448 { 1449 if ((x86_feature & X86_CPUID) == 0 || 1450 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1451 return ("i486 compatible"); 1452 1453 switch (cpi->cpi_family) { 1454 case 5: 1455 switch (cpi->cpi_model) { 1456 case 0: 1457 case 1: 1458 case 2: 1459 case 3: 1460 case 4: 1461 case 5: 1462 return ("AMD-K5(r)"); 1463 case 6: 1464 case 7: 1465 return ("AMD-K6(r)"); 1466 case 8: 1467 return ("AMD-K6(r)-2"); 1468 case 9: 1469 return ("AMD-K6(r)-III"); 1470 default: 1471 return ("AMD (family 5)"); 1472 } 1473 case 6: 1474 switch (cpi->cpi_model) { 1475 case 1: 1476 return ("AMD-K7(tm)"); 1477 case 0: 1478 case 2: 1479 case 4: 1480 return ("AMD Athlon(tm)"); 1481 case 3: 1482 case 7: 1483 return ("AMD Duron(tm)"); 1484 case 6: 1485 case 8: 1486 case 10: 1487 /* 1488 * Use the L2 cache size to distinguish 1489 */ 1490 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1491 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1492 default: 1493 return ("AMD (family 6)"); 1494 } 1495 default: 1496 break; 1497 } 1498 1499 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1500 cpi->cpi_brandid != 0) { 1501 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1502 case 3: 1503 return ("AMD Opteron(tm) UP 1xx"); 1504 case 4: 1505 return ("AMD Opteron(tm) DP 2xx"); 1506 case 5: 1507 return ("AMD Opteron(tm) MP 8xx"); 1508 default: 1509 return ("AMD Opteron(tm)"); 1510 } 1511 } 1512 1513 return (NULL); 1514 } 1515 1516 static const char * 1517 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1518 { 1519 if ((x86_feature & X86_CPUID) == 0 || 1520 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1521 type == X86_TYPE_CYRIX_486) 1522 return ("i486 compatible"); 1523 1524 switch (type) { 1525 case X86_TYPE_CYRIX_6x86: 1526 return ("Cyrix 6x86"); 1527 case X86_TYPE_CYRIX_6x86L: 1528 return ("Cyrix 6x86L"); 1529 case X86_TYPE_CYRIX_6x86MX: 1530 return ("Cyrix 6x86MX"); 1531 case X86_TYPE_CYRIX_GXm: 1532 return ("Cyrix GXm"); 1533 case X86_TYPE_CYRIX_MediaGX: 1534 return ("Cyrix MediaGX"); 1535 case X86_TYPE_CYRIX_MII: 1536 return ("Cyrix M2"); 1537 case X86_TYPE_VIA_CYRIX_III: 1538 return ("VIA Cyrix M3"); 1539 default: 1540 /* 1541 * Have another wild guess .. 1542 */ 1543 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1544 return ("Cyrix 5x86"); 1545 else if (cpi->cpi_family == 5) { 1546 switch (cpi->cpi_model) { 1547 case 2: 1548 return ("Cyrix 6x86"); /* Cyrix M1 */ 1549 case 4: 1550 return ("Cyrix MediaGX"); 1551 default: 1552 break; 1553 } 1554 } else if (cpi->cpi_family == 6) { 1555 switch (cpi->cpi_model) { 1556 case 0: 1557 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1558 case 5: 1559 case 6: 1560 case 7: 1561 case 8: 1562 case 9: 1563 return ("VIA C3"); 1564 default: 1565 break; 1566 } 1567 } 1568 break; 1569 } 1570 return (NULL); 1571 } 1572 1573 /* 1574 * This only gets called in the case that the CPU extended 1575 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1576 * aren't available, or contain null bytes for some reason. 1577 */ 1578 static void 1579 fabricate_brandstr(struct cpuid_info *cpi) 1580 { 1581 const char *brand = NULL; 1582 1583 switch (cpi->cpi_vendor) { 1584 case X86_VENDOR_Intel: 1585 brand = intel_cpubrand(cpi); 1586 break; 1587 case X86_VENDOR_AMD: 1588 brand = amd_cpubrand(cpi); 1589 break; 1590 case X86_VENDOR_Cyrix: 1591 brand = cyrix_cpubrand(cpi, x86_type); 1592 break; 1593 case X86_VENDOR_NexGen: 1594 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1595 brand = "NexGen Nx586"; 1596 break; 1597 case X86_VENDOR_Centaur: 1598 if (cpi->cpi_family == 5) 1599 switch (cpi->cpi_model) { 1600 case 4: 1601 brand = "Centaur C6"; 1602 break; 1603 case 8: 1604 brand = "Centaur C2"; 1605 break; 1606 case 9: 1607 brand = "Centaur C3"; 1608 break; 1609 default: 1610 break; 1611 } 1612 break; 1613 case X86_VENDOR_Rise: 1614 if (cpi->cpi_family == 5 && 1615 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1616 brand = "Rise mP6"; 1617 break; 1618 case X86_VENDOR_SiS: 1619 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1620 brand = "SiS 55x"; 1621 break; 1622 case X86_VENDOR_TM: 1623 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1624 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1625 break; 1626 case X86_VENDOR_NSC: 1627 case X86_VENDOR_UMC: 1628 default: 1629 break; 1630 } 1631 if (brand) { 1632 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1633 return; 1634 } 1635 1636 /* 1637 * If all else fails ... 1638 */ 1639 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1640 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1641 cpi->cpi_model, cpi->cpi_step); 1642 } 1643 1644 /* 1645 * This routine is called just after kernel memory allocation 1646 * becomes available on cpu0, and as part of mp_startup() on 1647 * the other cpus. 1648 * 1649 * Fixup the brand string, and collect any information from cpuid 1650 * that requires dynamicically allocated storage to represent. 1651 */ 1652 /*ARGSUSED*/ 1653 void 1654 cpuid_pass3(cpu_t *cpu) 1655 { 1656 int i, max, shft, level, size; 1657 struct cpuid_regs regs; 1658 struct cpuid_regs *cp; 1659 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1660 1661 ASSERT(cpi->cpi_pass == 2); 1662 1663 /* 1664 * Function 4: Deterministic cache parameters 1665 * 1666 * Take this opportunity to detect the number of threads 1667 * sharing the last level cache, and construct a corresponding 1668 * cache id. The respective cpuid_info members are initialized 1669 * to the default case of "no last level cache sharing". 1670 */ 1671 cpi->cpi_ncpu_shr_last_cache = 1; 1672 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1673 1674 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1675 1676 /* 1677 * Find the # of elements (size) returned by fn 4, and along 1678 * the way detect last level cache sharing details. 1679 */ 1680 bzero(®s, sizeof (regs)); 1681 cp = ®s; 1682 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1683 cp->cp_eax = 4; 1684 cp->cp_ecx = i; 1685 1686 (void) __cpuid_insn(cp); 1687 1688 if (CPI_CACHE_TYPE(cp) == 0) 1689 break; 1690 level = CPI_CACHE_LVL(cp); 1691 if (level > max) { 1692 max = level; 1693 cpi->cpi_ncpu_shr_last_cache = 1694 CPI_NTHR_SHR_CACHE(cp) + 1; 1695 } 1696 } 1697 cpi->cpi_std_4_size = size = i; 1698 1699 /* 1700 * Allocate the cpi_std_4 array. The first element 1701 * references the regs for fn 4, %ecx == 0, which 1702 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1703 */ 1704 if (size > 0) { 1705 cpi->cpi_std_4 = 1706 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1707 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1708 1709 /* 1710 * Allocate storage to hold the additional regs 1711 * for function 4, %ecx == 1 .. cpi_std_4_size. 1712 * 1713 * The regs for fn 4, %ecx == 0 has already 1714 * been allocated as indicated above. 1715 */ 1716 for (i = 1; i < size; i++) { 1717 cp = cpi->cpi_std_4[i] = 1718 kmem_zalloc(sizeof (regs), KM_SLEEP); 1719 cp->cp_eax = 4; 1720 cp->cp_ecx = i; 1721 1722 (void) __cpuid_insn(cp); 1723 } 1724 } 1725 /* 1726 * Determine the number of bits needed to represent 1727 * the number of CPUs sharing the last level cache. 1728 * 1729 * Shift off that number of bits from the APIC id to 1730 * derive the cache id. 1731 */ 1732 shft = 0; 1733 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1734 shft++; 1735 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1736 } 1737 1738 /* 1739 * Now fixup the brand string 1740 */ 1741 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1742 fabricate_brandstr(cpi); 1743 } else { 1744 1745 /* 1746 * If we successfully extracted a brand string from the cpuid 1747 * instruction, clean it up by removing leading spaces and 1748 * similar junk. 1749 */ 1750 if (cpi->cpi_brandstr[0]) { 1751 size_t maxlen = sizeof (cpi->cpi_brandstr); 1752 char *src, *dst; 1753 1754 dst = src = (char *)cpi->cpi_brandstr; 1755 src[maxlen - 1] = '\0'; 1756 /* 1757 * strip leading spaces 1758 */ 1759 while (*src == ' ') 1760 src++; 1761 /* 1762 * Remove any 'Genuine' or "Authentic" prefixes 1763 */ 1764 if (strncmp(src, "Genuine ", 8) == 0) 1765 src += 8; 1766 if (strncmp(src, "Authentic ", 10) == 0) 1767 src += 10; 1768 1769 /* 1770 * Now do an in-place copy. 1771 * Map (R) to (r) and (TM) to (tm). 1772 * The era of teletypes is long gone, and there's 1773 * -really- no need to shout. 1774 */ 1775 while (*src != '\0') { 1776 if (src[0] == '(') { 1777 if (strncmp(src + 1, "R)", 2) == 0) { 1778 (void) strncpy(dst, "(r)", 3); 1779 src += 3; 1780 dst += 3; 1781 continue; 1782 } 1783 if (strncmp(src + 1, "TM)", 3) == 0) { 1784 (void) strncpy(dst, "(tm)", 4); 1785 src += 4; 1786 dst += 4; 1787 continue; 1788 } 1789 } 1790 *dst++ = *src++; 1791 } 1792 *dst = '\0'; 1793 1794 /* 1795 * Finally, remove any trailing spaces 1796 */ 1797 while (--dst > cpi->cpi_brandstr) 1798 if (*dst == ' ') 1799 *dst = '\0'; 1800 else 1801 break; 1802 } else 1803 fabricate_brandstr(cpi); 1804 } 1805 cpi->cpi_pass = 3; 1806 } 1807 1808 /* 1809 * This routine is called out of bind_hwcap() much later in the life 1810 * of the kernel (post_startup()). The job of this routine is to resolve 1811 * the hardware feature support and kernel support for those features into 1812 * what we're actually going to tell applications via the aux vector. 1813 */ 1814 uint_t 1815 cpuid_pass4(cpu_t *cpu) 1816 { 1817 struct cpuid_info *cpi; 1818 uint_t hwcap_flags = 0; 1819 1820 if (cpu == NULL) 1821 cpu = CPU; 1822 cpi = cpu->cpu_m.mcpu_cpi; 1823 1824 ASSERT(cpi->cpi_pass == 3); 1825 1826 if (cpi->cpi_maxeax >= 1) { 1827 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1828 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1829 1830 *edx = CPI_FEATURES_EDX(cpi); 1831 *ecx = CPI_FEATURES_ECX(cpi); 1832 1833 /* 1834 * [these require explicit kernel support] 1835 */ 1836 if ((x86_feature & X86_SEP) == 0) 1837 *edx &= ~CPUID_INTC_EDX_SEP; 1838 1839 if ((x86_feature & X86_SSE) == 0) 1840 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 1841 if ((x86_feature & X86_SSE2) == 0) 1842 *edx &= ~CPUID_INTC_EDX_SSE2; 1843 1844 if ((x86_feature & X86_HTT) == 0) 1845 *edx &= ~CPUID_INTC_EDX_HTT; 1846 1847 if ((x86_feature & X86_SSE3) == 0) 1848 *ecx &= ~CPUID_INTC_ECX_SSE3; 1849 1850 /* 1851 * [no explicit support required beyond x87 fp context] 1852 */ 1853 if (!fpu_exists) 1854 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 1855 1856 /* 1857 * Now map the supported feature vector to things that we 1858 * think userland will care about. 1859 */ 1860 if (*edx & CPUID_INTC_EDX_SEP) 1861 hwcap_flags |= AV_386_SEP; 1862 if (*edx & CPUID_INTC_EDX_SSE) 1863 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 1864 if (*edx & CPUID_INTC_EDX_SSE2) 1865 hwcap_flags |= AV_386_SSE2; 1866 if (*ecx & CPUID_INTC_ECX_SSE3) 1867 hwcap_flags |= AV_386_SSE3; 1868 if (*ecx & CPUID_INTC_ECX_POPCNT) 1869 hwcap_flags |= AV_386_POPCNT; 1870 if (*edx & CPUID_INTC_EDX_FPU) 1871 hwcap_flags |= AV_386_FPU; 1872 if (*edx & CPUID_INTC_EDX_MMX) 1873 hwcap_flags |= AV_386_MMX; 1874 1875 if (*edx & CPUID_INTC_EDX_TSC) 1876 hwcap_flags |= AV_386_TSC; 1877 if (*edx & CPUID_INTC_EDX_CX8) 1878 hwcap_flags |= AV_386_CX8; 1879 if (*edx & CPUID_INTC_EDX_CMOV) 1880 hwcap_flags |= AV_386_CMOV; 1881 if (*ecx & CPUID_INTC_ECX_MON) 1882 hwcap_flags |= AV_386_MON; 1883 if (*ecx & CPUID_INTC_ECX_CX16) 1884 hwcap_flags |= AV_386_CX16; 1885 } 1886 1887 if (x86_feature & X86_HTT) 1888 hwcap_flags |= AV_386_PAUSE; 1889 1890 if (cpi->cpi_xmaxeax < 0x80000001) 1891 goto pass4_done; 1892 1893 switch (cpi->cpi_vendor) { 1894 struct cpuid_regs cp; 1895 uint32_t *edx, *ecx; 1896 1897 case X86_VENDOR_Intel: 1898 /* 1899 * Seems like Intel duplicated what we necessary 1900 * here to make the initial crop of 64-bit OS's work. 1901 * Hopefully, those are the only "extended" bits 1902 * they'll add. 1903 */ 1904 /*FALLTHROUGH*/ 1905 1906 case X86_VENDOR_AMD: 1907 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 1908 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 1909 1910 *edx = CPI_FEATURES_XTD_EDX(cpi); 1911 *ecx = CPI_FEATURES_XTD_ECX(cpi); 1912 1913 /* 1914 * [these features require explicit kernel support] 1915 */ 1916 switch (cpi->cpi_vendor) { 1917 case X86_VENDOR_Intel: 1918 break; 1919 1920 case X86_VENDOR_AMD: 1921 if ((x86_feature & X86_TSCP) == 0) 1922 *edx &= ~CPUID_AMD_EDX_TSCP; 1923 if ((x86_feature & X86_SSE4A) == 0) 1924 *ecx &= ~CPUID_AMD_ECX_SSE4A; 1925 break; 1926 1927 default: 1928 break; 1929 } 1930 1931 /* 1932 * [no explicit support required beyond 1933 * x87 fp context and exception handlers] 1934 */ 1935 if (!fpu_exists) 1936 *edx &= ~(CPUID_AMD_EDX_MMXamd | 1937 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 1938 1939 if ((x86_feature & X86_NX) == 0) 1940 *edx &= ~CPUID_AMD_EDX_NX; 1941 #if !defined(__amd64) 1942 *edx &= ~CPUID_AMD_EDX_LM; 1943 #endif 1944 /* 1945 * Now map the supported feature vector to 1946 * things that we think userland will care about. 1947 */ 1948 #if defined(__amd64) 1949 if (*edx & CPUID_AMD_EDX_SYSC) 1950 hwcap_flags |= AV_386_AMD_SYSC; 1951 #endif 1952 if (*edx & CPUID_AMD_EDX_MMXamd) 1953 hwcap_flags |= AV_386_AMD_MMX; 1954 if (*edx & CPUID_AMD_EDX_3DNow) 1955 hwcap_flags |= AV_386_AMD_3DNow; 1956 if (*edx & CPUID_AMD_EDX_3DNowx) 1957 hwcap_flags |= AV_386_AMD_3DNowx; 1958 1959 switch (cpi->cpi_vendor) { 1960 case X86_VENDOR_AMD: 1961 if (*edx & CPUID_AMD_EDX_TSCP) 1962 hwcap_flags |= AV_386_TSCP; 1963 if (*ecx & CPUID_AMD_ECX_AHF64) 1964 hwcap_flags |= AV_386_AHF; 1965 if (*ecx & CPUID_AMD_ECX_SSE4A) 1966 hwcap_flags |= AV_386_AMD_SSE4A; 1967 if (*ecx & CPUID_AMD_ECX_LZCNT) 1968 hwcap_flags |= AV_386_AMD_LZCNT; 1969 break; 1970 1971 case X86_VENDOR_Intel: 1972 /* 1973 * Aarrgh. 1974 * Intel uses a different bit in the same word. 1975 */ 1976 if (*ecx & CPUID_INTC_ECX_AHF64) 1977 hwcap_flags |= AV_386_AHF; 1978 break; 1979 1980 default: 1981 break; 1982 } 1983 break; 1984 1985 case X86_VENDOR_TM: 1986 cp.cp_eax = 0x80860001; 1987 (void) __cpuid_insn(&cp); 1988 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 1989 break; 1990 1991 default: 1992 break; 1993 } 1994 1995 pass4_done: 1996 cpi->cpi_pass = 4; 1997 return (hwcap_flags); 1998 } 1999 2000 2001 /* 2002 * Simulate the cpuid instruction using the data we previously 2003 * captured about this CPU. We try our best to return the truth 2004 * about the hardware, independently of kernel support. 2005 */ 2006 uint32_t 2007 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2008 { 2009 struct cpuid_info *cpi; 2010 struct cpuid_regs *xcp; 2011 2012 if (cpu == NULL) 2013 cpu = CPU; 2014 cpi = cpu->cpu_m.mcpu_cpi; 2015 2016 ASSERT(cpuid_checkpass(cpu, 3)); 2017 2018 /* 2019 * CPUID data is cached in two separate places: cpi_std for standard 2020 * CPUID functions, and cpi_extd for extended CPUID functions. 2021 */ 2022 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2023 xcp = &cpi->cpi_std[cp->cp_eax]; 2024 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2025 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2026 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2027 else 2028 /* 2029 * The caller is asking for data from an input parameter which 2030 * the kernel has not cached. In this case we go fetch from 2031 * the hardware and return the data directly to the user. 2032 */ 2033 return (__cpuid_insn(cp)); 2034 2035 cp->cp_eax = xcp->cp_eax; 2036 cp->cp_ebx = xcp->cp_ebx; 2037 cp->cp_ecx = xcp->cp_ecx; 2038 cp->cp_edx = xcp->cp_edx; 2039 return (cp->cp_eax); 2040 } 2041 2042 int 2043 cpuid_checkpass(cpu_t *cpu, int pass) 2044 { 2045 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2046 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2047 } 2048 2049 int 2050 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2051 { 2052 ASSERT(cpuid_checkpass(cpu, 3)); 2053 2054 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2055 } 2056 2057 int 2058 cpuid_is_cmt(cpu_t *cpu) 2059 { 2060 if (cpu == NULL) 2061 cpu = CPU; 2062 2063 ASSERT(cpuid_checkpass(cpu, 1)); 2064 2065 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2066 } 2067 2068 /* 2069 * AMD and Intel both implement the 64-bit variant of the syscall 2070 * instruction (syscallq), so if there's -any- support for syscall, 2071 * cpuid currently says "yes, we support this". 2072 * 2073 * However, Intel decided to -not- implement the 32-bit variant of the 2074 * syscall instruction, so we provide a predicate to allow our caller 2075 * to test that subtlety here. 2076 */ 2077 /*ARGSUSED*/ 2078 int 2079 cpuid_syscall32_insn(cpu_t *cpu) 2080 { 2081 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2082 2083 if (cpu == NULL) 2084 cpu = CPU; 2085 2086 /*CSTYLED*/ 2087 { 2088 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2089 2090 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2091 cpi->cpi_xmaxeax >= 0x80000001 && 2092 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2093 return (1); 2094 } 2095 return (0); 2096 } 2097 2098 int 2099 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2100 { 2101 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2102 2103 static const char fmt[] = 2104 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2105 static const char fmt_ht[] = 2106 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2107 2108 ASSERT(cpuid_checkpass(cpu, 1)); 2109 2110 if (cpuid_is_cmt(cpu)) 2111 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2112 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2113 cpi->cpi_family, cpi->cpi_model, 2114 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2115 return (snprintf(s, n, fmt, 2116 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2117 cpi->cpi_family, cpi->cpi_model, 2118 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2119 } 2120 2121 const char * 2122 cpuid_getvendorstr(cpu_t *cpu) 2123 { 2124 ASSERT(cpuid_checkpass(cpu, 1)); 2125 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2126 } 2127 2128 uint_t 2129 cpuid_getvendor(cpu_t *cpu) 2130 { 2131 ASSERT(cpuid_checkpass(cpu, 1)); 2132 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2133 } 2134 2135 uint_t 2136 cpuid_getfamily(cpu_t *cpu) 2137 { 2138 ASSERT(cpuid_checkpass(cpu, 1)); 2139 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2140 } 2141 2142 uint_t 2143 cpuid_getmodel(cpu_t *cpu) 2144 { 2145 ASSERT(cpuid_checkpass(cpu, 1)); 2146 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2147 } 2148 2149 uint_t 2150 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2151 { 2152 ASSERT(cpuid_checkpass(cpu, 1)); 2153 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2154 } 2155 2156 uint_t 2157 cpuid_get_ncore_per_chip(cpu_t *cpu) 2158 { 2159 ASSERT(cpuid_checkpass(cpu, 1)); 2160 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2161 } 2162 2163 uint_t 2164 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2165 { 2166 ASSERT(cpuid_checkpass(cpu, 2)); 2167 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2168 } 2169 2170 id_t 2171 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2172 { 2173 ASSERT(cpuid_checkpass(cpu, 2)); 2174 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2175 } 2176 2177 uint_t 2178 cpuid_getstep(cpu_t *cpu) 2179 { 2180 ASSERT(cpuid_checkpass(cpu, 1)); 2181 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2182 } 2183 2184 uint_t 2185 cpuid_getsig(struct cpu *cpu) 2186 { 2187 ASSERT(cpuid_checkpass(cpu, 1)); 2188 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2189 } 2190 2191 uint32_t 2192 cpuid_getchiprev(struct cpu *cpu) 2193 { 2194 ASSERT(cpuid_checkpass(cpu, 1)); 2195 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2196 } 2197 2198 const char * 2199 cpuid_getchiprevstr(struct cpu *cpu) 2200 { 2201 ASSERT(cpuid_checkpass(cpu, 1)); 2202 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2203 } 2204 2205 uint32_t 2206 cpuid_getsockettype(struct cpu *cpu) 2207 { 2208 ASSERT(cpuid_checkpass(cpu, 1)); 2209 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2210 } 2211 2212 int 2213 cpuid_get_chipid(cpu_t *cpu) 2214 { 2215 ASSERT(cpuid_checkpass(cpu, 1)); 2216 2217 if (cpuid_is_cmt(cpu)) 2218 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2219 return (cpu->cpu_id); 2220 } 2221 2222 id_t 2223 cpuid_get_coreid(cpu_t *cpu) 2224 { 2225 ASSERT(cpuid_checkpass(cpu, 1)); 2226 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2227 } 2228 2229 int 2230 cpuid_get_clogid(cpu_t *cpu) 2231 { 2232 ASSERT(cpuid_checkpass(cpu, 1)); 2233 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2234 } 2235 2236 void 2237 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2238 { 2239 struct cpuid_info *cpi; 2240 2241 if (cpu == NULL) 2242 cpu = CPU; 2243 cpi = cpu->cpu_m.mcpu_cpi; 2244 2245 ASSERT(cpuid_checkpass(cpu, 1)); 2246 2247 if (pabits) 2248 *pabits = cpi->cpi_pabits; 2249 if (vabits) 2250 *vabits = cpi->cpi_vabits; 2251 } 2252 2253 /* 2254 * Returns the number of data TLB entries for a corresponding 2255 * pagesize. If it can't be computed, or isn't known, the 2256 * routine returns zero. If you ask about an architecturally 2257 * impossible pagesize, the routine will panic (so that the 2258 * hat implementor knows that things are inconsistent.) 2259 */ 2260 uint_t 2261 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2262 { 2263 struct cpuid_info *cpi; 2264 uint_t dtlb_nent = 0; 2265 2266 if (cpu == NULL) 2267 cpu = CPU; 2268 cpi = cpu->cpu_m.mcpu_cpi; 2269 2270 ASSERT(cpuid_checkpass(cpu, 1)); 2271 2272 /* 2273 * Check the L2 TLB info 2274 */ 2275 if (cpi->cpi_xmaxeax >= 0x80000006) { 2276 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2277 2278 switch (pagesize) { 2279 2280 case 4 * 1024: 2281 /* 2282 * All zero in the top 16 bits of the register 2283 * indicates a unified TLB. Size is in low 16 bits. 2284 */ 2285 if ((cp->cp_ebx & 0xffff0000) == 0) 2286 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2287 else 2288 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2289 break; 2290 2291 case 2 * 1024 * 1024: 2292 if ((cp->cp_eax & 0xffff0000) == 0) 2293 dtlb_nent = cp->cp_eax & 0x0000ffff; 2294 else 2295 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2296 break; 2297 2298 default: 2299 panic("unknown L2 pagesize"); 2300 /*NOTREACHED*/ 2301 } 2302 } 2303 2304 if (dtlb_nent != 0) 2305 return (dtlb_nent); 2306 2307 /* 2308 * No L2 TLB support for this size, try L1. 2309 */ 2310 if (cpi->cpi_xmaxeax >= 0x80000005) { 2311 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2312 2313 switch (pagesize) { 2314 case 4 * 1024: 2315 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2316 break; 2317 case 2 * 1024 * 1024: 2318 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2319 break; 2320 default: 2321 panic("unknown L1 d-TLB pagesize"); 2322 /*NOTREACHED*/ 2323 } 2324 } 2325 2326 return (dtlb_nent); 2327 } 2328 2329 /* 2330 * Return 0 if the erratum is not present or not applicable, positive 2331 * if it is, and negative if the status of the erratum is unknown. 2332 * 2333 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2334 * Processors" #25759, Rev 3.57, August 2005 2335 */ 2336 int 2337 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2338 { 2339 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2340 uint_t eax; 2341 2342 /* 2343 * Bail out if this CPU isn't an AMD CPU, or if it's 2344 * a legacy (32-bit) AMD CPU. 2345 */ 2346 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2347 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2348 cpi->cpi_family == 6) 2349 2350 return (0); 2351 2352 eax = cpi->cpi_std[1].cp_eax; 2353 2354 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2355 #define SH_B3(eax) (eax == 0xf51) 2356 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2357 2358 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2359 2360 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2361 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2362 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2363 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2364 2365 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2366 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2367 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2368 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2369 2370 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2371 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2372 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2373 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2374 #define BH_E4(eax) (eax == 0x20fb1) 2375 #define SH_E5(eax) (eax == 0x20f42) 2376 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2377 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2378 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2379 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2380 DH_E6(eax) || JH_E6(eax)) 2381 2382 switch (erratum) { 2383 case 1: 2384 return (cpi->cpi_family < 0x10); 2385 case 51: /* what does the asterisk mean? */ 2386 return (B(eax) || SH_C0(eax) || CG(eax)); 2387 case 52: 2388 return (B(eax)); 2389 case 57: 2390 return (cpi->cpi_family <= 0x10); 2391 case 58: 2392 return (B(eax)); 2393 case 60: 2394 return (cpi->cpi_family <= 0x10); 2395 case 61: 2396 case 62: 2397 case 63: 2398 case 64: 2399 case 65: 2400 case 66: 2401 case 68: 2402 case 69: 2403 case 70: 2404 case 71: 2405 return (B(eax)); 2406 case 72: 2407 return (SH_B0(eax)); 2408 case 74: 2409 return (B(eax)); 2410 case 75: 2411 return (cpi->cpi_family < 0x10); 2412 case 76: 2413 return (B(eax)); 2414 case 77: 2415 return (cpi->cpi_family <= 0x10); 2416 case 78: 2417 return (B(eax) || SH_C0(eax)); 2418 case 79: 2419 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2420 case 80: 2421 case 81: 2422 case 82: 2423 return (B(eax)); 2424 case 83: 2425 return (B(eax) || SH_C0(eax) || CG(eax)); 2426 case 85: 2427 return (cpi->cpi_family < 0x10); 2428 case 86: 2429 return (SH_C0(eax) || CG(eax)); 2430 case 88: 2431 #if !defined(__amd64) 2432 return (0); 2433 #else 2434 return (B(eax) || SH_C0(eax)); 2435 #endif 2436 case 89: 2437 return (cpi->cpi_family < 0x10); 2438 case 90: 2439 return (B(eax) || SH_C0(eax) || CG(eax)); 2440 case 91: 2441 case 92: 2442 return (B(eax) || SH_C0(eax)); 2443 case 93: 2444 return (SH_C0(eax)); 2445 case 94: 2446 return (B(eax) || SH_C0(eax) || CG(eax)); 2447 case 95: 2448 #if !defined(__amd64) 2449 return (0); 2450 #else 2451 return (B(eax) || SH_C0(eax)); 2452 #endif 2453 case 96: 2454 return (B(eax) || SH_C0(eax) || CG(eax)); 2455 case 97: 2456 case 98: 2457 return (SH_C0(eax) || CG(eax)); 2458 case 99: 2459 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2460 case 100: 2461 return (B(eax) || SH_C0(eax)); 2462 case 101: 2463 case 103: 2464 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2465 case 104: 2466 return (SH_C0(eax) || CG(eax) || D0(eax)); 2467 case 105: 2468 case 106: 2469 case 107: 2470 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2471 case 108: 2472 return (DH_CG(eax)); 2473 case 109: 2474 return (SH_C0(eax) || CG(eax) || D0(eax)); 2475 case 110: 2476 return (D0(eax) || EX(eax)); 2477 case 111: 2478 return (CG(eax)); 2479 case 112: 2480 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2481 case 113: 2482 return (eax == 0x20fc0); 2483 case 114: 2484 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2485 case 115: 2486 return (SH_E0(eax) || JH_E1(eax)); 2487 case 116: 2488 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2489 case 117: 2490 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2491 case 118: 2492 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2493 JH_E6(eax)); 2494 case 121: 2495 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2496 case 122: 2497 return (cpi->cpi_family < 0x10); 2498 case 123: 2499 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2500 case 131: 2501 return (cpi->cpi_family < 0x10); 2502 case 6336786: 2503 /* 2504 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2505 * if this is a K8 family or newer processor 2506 */ 2507 if (CPI_FAMILY(cpi) == 0xf) { 2508 struct cpuid_regs regs; 2509 regs.cp_eax = 0x80000007; 2510 (void) __cpuid_insn(®s); 2511 return (!(regs.cp_edx & 0x100)); 2512 } 2513 return (0); 2514 case 6323525: 2515 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2516 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2517 2518 default: 2519 return (-1); 2520 } 2521 } 2522 2523 static const char assoc_str[] = "associativity"; 2524 static const char line_str[] = "line-size"; 2525 static const char size_str[] = "size"; 2526 2527 static void 2528 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2529 uint32_t val) 2530 { 2531 char buf[128]; 2532 2533 /* 2534 * ndi_prop_update_int() is used because it is desirable for 2535 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2536 */ 2537 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2538 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2539 } 2540 2541 /* 2542 * Intel-style cache/tlb description 2543 * 2544 * Standard cpuid level 2 gives a randomly ordered 2545 * selection of tags that index into a table that describes 2546 * cache and tlb properties. 2547 */ 2548 2549 static const char l1_icache_str[] = "l1-icache"; 2550 static const char l1_dcache_str[] = "l1-dcache"; 2551 static const char l2_cache_str[] = "l2-cache"; 2552 static const char l3_cache_str[] = "l3-cache"; 2553 static const char itlb4k_str[] = "itlb-4K"; 2554 static const char dtlb4k_str[] = "dtlb-4K"; 2555 static const char itlb4M_str[] = "itlb-4M"; 2556 static const char dtlb4M_str[] = "dtlb-4M"; 2557 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2558 static const char dtlb44_str[] = "dtlb-4K-4M"; 2559 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2560 static const char sl2_cache_str[] = "sectored-l2-cache"; 2561 static const char itrace_str[] = "itrace-cache"; 2562 static const char sl3_cache_str[] = "sectored-l3-cache"; 2563 2564 static const struct cachetab { 2565 uint8_t ct_code; 2566 uint8_t ct_assoc; 2567 uint16_t ct_line_size; 2568 size_t ct_size; 2569 const char *ct_label; 2570 } intel_ctab[] = { 2571 /* maintain descending order! */ 2572 { 0xb4, 4, 0, 256, dtlb4k_str }, 2573 { 0xb3, 4, 0, 128, dtlb4k_str }, 2574 { 0xb0, 4, 0, 128, itlb4k_str }, 2575 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2576 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2577 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2578 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2579 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2580 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2581 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2582 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2583 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2584 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2585 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2586 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2587 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2588 { 0x73, 8, 0, 64*1024, itrace_str}, 2589 { 0x72, 8, 0, 32*1024, itrace_str}, 2590 { 0x71, 8, 0, 16*1024, itrace_str}, 2591 { 0x70, 8, 0, 12*1024, itrace_str}, 2592 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2593 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2594 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2595 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2596 { 0x5d, 0, 0, 256, dtlb44_str}, 2597 { 0x5c, 0, 0, 128, dtlb44_str}, 2598 { 0x5b, 0, 0, 64, dtlb44_str}, 2599 { 0x52, 0, 0, 256, itlb424_str}, 2600 { 0x51, 0, 0, 128, itlb424_str}, 2601 { 0x50, 0, 0, 64, itlb424_str}, 2602 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2603 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2604 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2605 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2606 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2607 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2608 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2609 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2610 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2611 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2612 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2613 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2614 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2615 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2616 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2617 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2618 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2619 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2620 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2621 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2622 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2623 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2624 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2625 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2626 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2627 { 0x0b, 4, 0, 4, itlb4M_str}, 2628 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2629 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2630 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2631 { 0x04, 4, 0, 8, dtlb4M_str}, 2632 { 0x03, 4, 0, 64, dtlb4k_str}, 2633 { 0x02, 4, 0, 2, itlb4M_str}, 2634 { 0x01, 4, 0, 32, itlb4k_str}, 2635 { 0 } 2636 }; 2637 2638 static const struct cachetab cyrix_ctab[] = { 2639 { 0x70, 4, 0, 32, "tlb-4K" }, 2640 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2641 { 0 } 2642 }; 2643 2644 /* 2645 * Search a cache table for a matching entry 2646 */ 2647 static const struct cachetab * 2648 find_cacheent(const struct cachetab *ct, uint_t code) 2649 { 2650 if (code != 0) { 2651 for (; ct->ct_code != 0; ct++) 2652 if (ct->ct_code <= code) 2653 break; 2654 if (ct->ct_code == code) 2655 return (ct); 2656 } 2657 return (NULL); 2658 } 2659 2660 /* 2661 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2662 * The walk is terminated if the walker returns non-zero. 2663 */ 2664 static void 2665 intel_walk_cacheinfo(struct cpuid_info *cpi, 2666 void *arg, int (*func)(void *, const struct cachetab *)) 2667 { 2668 const struct cachetab *ct; 2669 uint8_t *dp; 2670 int i; 2671 2672 if ((dp = cpi->cpi_cacheinfo) == NULL) 2673 return; 2674 for (i = 0; i < cpi->cpi_ncache; i++, dp++) 2675 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2676 if (func(arg, ct) != 0) 2677 break; 2678 } 2679 } 2680 2681 /* 2682 * (Like the Intel one, except for Cyrix CPUs) 2683 */ 2684 static void 2685 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2686 void *arg, int (*func)(void *, const struct cachetab *)) 2687 { 2688 const struct cachetab *ct; 2689 uint8_t *dp; 2690 int i; 2691 2692 if ((dp = cpi->cpi_cacheinfo) == NULL) 2693 return; 2694 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2695 /* 2696 * Search Cyrix-specific descriptor table first .. 2697 */ 2698 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2699 if (func(arg, ct) != 0) 2700 break; 2701 continue; 2702 } 2703 /* 2704 * .. else fall back to the Intel one 2705 */ 2706 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2707 if (func(arg, ct) != 0) 2708 break; 2709 continue; 2710 } 2711 } 2712 } 2713 2714 /* 2715 * A cacheinfo walker that adds associativity, line-size, and size properties 2716 * to the devinfo node it is passed as an argument. 2717 */ 2718 static int 2719 add_cacheent_props(void *arg, const struct cachetab *ct) 2720 { 2721 dev_info_t *devi = arg; 2722 2723 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2724 if (ct->ct_line_size != 0) 2725 add_cache_prop(devi, ct->ct_label, line_str, 2726 ct->ct_line_size); 2727 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2728 return (0); 2729 } 2730 2731 static const char fully_assoc[] = "fully-associative?"; 2732 2733 /* 2734 * AMD style cache/tlb description 2735 * 2736 * Extended functions 5 and 6 directly describe properties of 2737 * tlbs and various cache levels. 2738 */ 2739 static void 2740 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2741 { 2742 switch (assoc) { 2743 case 0: /* reserved; ignore */ 2744 break; 2745 default: 2746 add_cache_prop(devi, label, assoc_str, assoc); 2747 break; 2748 case 0xff: 2749 add_cache_prop(devi, label, fully_assoc, 1); 2750 break; 2751 } 2752 } 2753 2754 static void 2755 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2756 { 2757 if (size == 0) 2758 return; 2759 add_cache_prop(devi, label, size_str, size); 2760 add_amd_assoc(devi, label, assoc); 2761 } 2762 2763 static void 2764 add_amd_cache(dev_info_t *devi, const char *label, 2765 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2766 { 2767 if (size == 0 || line_size == 0) 2768 return; 2769 add_amd_assoc(devi, label, assoc); 2770 /* 2771 * Most AMD parts have a sectored cache. Multiple cache lines are 2772 * associated with each tag. A sector consists of all cache lines 2773 * associated with a tag. For example, the AMD K6-III has a sector 2774 * size of 2 cache lines per tag. 2775 */ 2776 if (lines_per_tag != 0) 2777 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2778 add_cache_prop(devi, label, line_str, line_size); 2779 add_cache_prop(devi, label, size_str, size * 1024); 2780 } 2781 2782 static void 2783 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2784 { 2785 switch (assoc) { 2786 case 0: /* off */ 2787 break; 2788 case 1: 2789 case 2: 2790 case 4: 2791 add_cache_prop(devi, label, assoc_str, assoc); 2792 break; 2793 case 6: 2794 add_cache_prop(devi, label, assoc_str, 8); 2795 break; 2796 case 8: 2797 add_cache_prop(devi, label, assoc_str, 16); 2798 break; 2799 case 0xf: 2800 add_cache_prop(devi, label, fully_assoc, 1); 2801 break; 2802 default: /* reserved; ignore */ 2803 break; 2804 } 2805 } 2806 2807 static void 2808 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 2809 { 2810 if (size == 0 || assoc == 0) 2811 return; 2812 add_amd_l2_assoc(devi, label, assoc); 2813 add_cache_prop(devi, label, size_str, size); 2814 } 2815 2816 static void 2817 add_amd_l2_cache(dev_info_t *devi, const char *label, 2818 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 2819 { 2820 if (size == 0 || assoc == 0 || line_size == 0) 2821 return; 2822 add_amd_l2_assoc(devi, label, assoc); 2823 if (lines_per_tag != 0) 2824 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 2825 add_cache_prop(devi, label, line_str, line_size); 2826 add_cache_prop(devi, label, size_str, size * 1024); 2827 } 2828 2829 static void 2830 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 2831 { 2832 struct cpuid_regs *cp; 2833 2834 if (cpi->cpi_xmaxeax < 0x80000005) 2835 return; 2836 cp = &cpi->cpi_extd[5]; 2837 2838 /* 2839 * 4M/2M L1 TLB configuration 2840 * 2841 * We report the size for 2M pages because AMD uses two 2842 * TLB entries for one 4M page. 2843 */ 2844 add_amd_tlb(devi, "dtlb-2M", 2845 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 2846 add_amd_tlb(devi, "itlb-2M", 2847 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 2848 2849 /* 2850 * 4K L1 TLB configuration 2851 */ 2852 2853 switch (cpi->cpi_vendor) { 2854 uint_t nentries; 2855 case X86_VENDOR_TM: 2856 if (cpi->cpi_family >= 5) { 2857 /* 2858 * Crusoe processors have 256 TLB entries, but 2859 * cpuid data format constrains them to only 2860 * reporting 255 of them. 2861 */ 2862 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 2863 nentries = 256; 2864 /* 2865 * Crusoe processors also have a unified TLB 2866 */ 2867 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 2868 nentries); 2869 break; 2870 } 2871 /*FALLTHROUGH*/ 2872 default: 2873 add_amd_tlb(devi, itlb4k_str, 2874 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 2875 add_amd_tlb(devi, dtlb4k_str, 2876 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 2877 break; 2878 } 2879 2880 /* 2881 * data L1 cache configuration 2882 */ 2883 2884 add_amd_cache(devi, l1_dcache_str, 2885 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 2886 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 2887 2888 /* 2889 * code L1 cache configuration 2890 */ 2891 2892 add_amd_cache(devi, l1_icache_str, 2893 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 2894 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 2895 2896 if (cpi->cpi_xmaxeax < 0x80000006) 2897 return; 2898 cp = &cpi->cpi_extd[6]; 2899 2900 /* Check for a unified L2 TLB for large pages */ 2901 2902 if (BITX(cp->cp_eax, 31, 16) == 0) 2903 add_amd_l2_tlb(devi, "l2-tlb-2M", 2904 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2905 else { 2906 add_amd_l2_tlb(devi, "l2-dtlb-2M", 2907 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2908 add_amd_l2_tlb(devi, "l2-itlb-2M", 2909 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2910 } 2911 2912 /* Check for a unified L2 TLB for 4K pages */ 2913 2914 if (BITX(cp->cp_ebx, 31, 16) == 0) { 2915 add_amd_l2_tlb(devi, "l2-tlb-4K", 2916 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2917 } else { 2918 add_amd_l2_tlb(devi, "l2-dtlb-4K", 2919 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 2920 add_amd_l2_tlb(devi, "l2-itlb-4K", 2921 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 2922 } 2923 2924 add_amd_l2_cache(devi, l2_cache_str, 2925 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 2926 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 2927 } 2928 2929 /* 2930 * There are two basic ways that the x86 world describes it cache 2931 * and tlb architecture - Intel's way and AMD's way. 2932 * 2933 * Return which flavor of cache architecture we should use 2934 */ 2935 static int 2936 x86_which_cacheinfo(struct cpuid_info *cpi) 2937 { 2938 switch (cpi->cpi_vendor) { 2939 case X86_VENDOR_Intel: 2940 if (cpi->cpi_maxeax >= 2) 2941 return (X86_VENDOR_Intel); 2942 break; 2943 case X86_VENDOR_AMD: 2944 /* 2945 * The K5 model 1 was the first part from AMD that reported 2946 * cache sizes via extended cpuid functions. 2947 */ 2948 if (cpi->cpi_family > 5 || 2949 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 2950 return (X86_VENDOR_AMD); 2951 break; 2952 case X86_VENDOR_TM: 2953 if (cpi->cpi_family >= 5) 2954 return (X86_VENDOR_AMD); 2955 /*FALLTHROUGH*/ 2956 default: 2957 /* 2958 * If they have extended CPU data for 0x80000005 2959 * then we assume they have AMD-format cache 2960 * information. 2961 * 2962 * If not, and the vendor happens to be Cyrix, 2963 * then try our-Cyrix specific handler. 2964 * 2965 * If we're not Cyrix, then assume we're using Intel's 2966 * table-driven format instead. 2967 */ 2968 if (cpi->cpi_xmaxeax >= 0x80000005) 2969 return (X86_VENDOR_AMD); 2970 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 2971 return (X86_VENDOR_Cyrix); 2972 else if (cpi->cpi_maxeax >= 2) 2973 return (X86_VENDOR_Intel); 2974 break; 2975 } 2976 return (-1); 2977 } 2978 2979 /* 2980 * create a node for the given cpu under the prom root node. 2981 * Also, create a cpu node in the device tree. 2982 */ 2983 static dev_info_t *cpu_nex_devi = NULL; 2984 static kmutex_t cpu_node_lock; 2985 2986 /* 2987 * Called from post_startup() and mp_startup() 2988 */ 2989 void 2990 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 2991 { 2992 dev_info_t *cpu_devi; 2993 int create; 2994 2995 mutex_enter(&cpu_node_lock); 2996 2997 /* 2998 * create a nexus node for all cpus identified as 'cpu_id' under 2999 * the root node. 3000 */ 3001 if (cpu_nex_devi == NULL) { 3002 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3003 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3004 mutex_exit(&cpu_node_lock); 3005 return; 3006 } 3007 (void) ndi_devi_online(cpu_nex_devi, 0); 3008 } 3009 3010 /* 3011 * create a child node for cpu identified as 'cpu_id' 3012 */ 3013 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3014 cpu_id); 3015 if (cpu_devi == NULL) { 3016 mutex_exit(&cpu_node_lock); 3017 return; 3018 } 3019 3020 /* device_type */ 3021 3022 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3023 "device_type", "cpu"); 3024 3025 /* reg */ 3026 3027 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3028 "reg", cpu_id); 3029 3030 /* cpu-mhz, and clock-frequency */ 3031 3032 if (cpu_freq > 0) { 3033 long long mul; 3034 3035 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3036 "cpu-mhz", cpu_freq); 3037 3038 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3039 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3040 "clock-frequency", (int)mul); 3041 } 3042 3043 (void) ndi_devi_online(cpu_devi, 0); 3044 3045 if ((x86_feature & X86_CPUID) == 0) { 3046 mutex_exit(&cpu_node_lock); 3047 return; 3048 } 3049 3050 /* vendor-id */ 3051 3052 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3053 "vendor-id", cpi->cpi_vendorstr); 3054 3055 if (cpi->cpi_maxeax == 0) { 3056 mutex_exit(&cpu_node_lock); 3057 return; 3058 } 3059 3060 /* 3061 * family, model, and step 3062 */ 3063 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3064 "family", CPI_FAMILY(cpi)); 3065 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3066 "cpu-model", CPI_MODEL(cpi)); 3067 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3068 "stepping-id", CPI_STEP(cpi)); 3069 3070 /* type */ 3071 3072 switch (cpi->cpi_vendor) { 3073 case X86_VENDOR_Intel: 3074 create = 1; 3075 break; 3076 default: 3077 create = 0; 3078 break; 3079 } 3080 if (create) 3081 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3082 "type", CPI_TYPE(cpi)); 3083 3084 /* ext-family */ 3085 3086 switch (cpi->cpi_vendor) { 3087 case X86_VENDOR_Intel: 3088 case X86_VENDOR_AMD: 3089 create = cpi->cpi_family >= 0xf; 3090 break; 3091 default: 3092 create = 0; 3093 break; 3094 } 3095 if (create) 3096 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3097 "ext-family", CPI_FAMILY_XTD(cpi)); 3098 3099 /* ext-model */ 3100 3101 switch (cpi->cpi_vendor) { 3102 case X86_VENDOR_Intel: 3103 create = CPI_MODEL(cpi) == 0xf; 3104 break; 3105 case X86_VENDOR_AMD: 3106 create = CPI_FAMILY(cpi) == 0xf; 3107 break; 3108 default: 3109 create = 0; 3110 break; 3111 } 3112 if (create) 3113 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3114 "ext-model", CPI_MODEL_XTD(cpi)); 3115 3116 /* generation */ 3117 3118 switch (cpi->cpi_vendor) { 3119 case X86_VENDOR_AMD: 3120 /* 3121 * AMD K5 model 1 was the first part to support this 3122 */ 3123 create = cpi->cpi_xmaxeax >= 0x80000001; 3124 break; 3125 default: 3126 create = 0; 3127 break; 3128 } 3129 if (create) 3130 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3131 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3132 3133 /* brand-id */ 3134 3135 switch (cpi->cpi_vendor) { 3136 case X86_VENDOR_Intel: 3137 /* 3138 * brand id first appeared on Pentium III Xeon model 8, 3139 * and Celeron model 8 processors and Opteron 3140 */ 3141 create = cpi->cpi_family > 6 || 3142 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3143 break; 3144 case X86_VENDOR_AMD: 3145 create = cpi->cpi_family >= 0xf; 3146 break; 3147 default: 3148 create = 0; 3149 break; 3150 } 3151 if (create && cpi->cpi_brandid != 0) { 3152 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3153 "brand-id", cpi->cpi_brandid); 3154 } 3155 3156 /* chunks, and apic-id */ 3157 3158 switch (cpi->cpi_vendor) { 3159 /* 3160 * first available on Pentium IV and Opteron (K8) 3161 */ 3162 case X86_VENDOR_Intel: 3163 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3164 break; 3165 case X86_VENDOR_AMD: 3166 create = cpi->cpi_family >= 0xf; 3167 break; 3168 default: 3169 create = 0; 3170 break; 3171 } 3172 if (create) { 3173 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3174 "chunks", CPI_CHUNKS(cpi)); 3175 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3176 "apic-id", CPI_APIC_ID(cpi)); 3177 if (cpi->cpi_chipid >= 0) { 3178 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3179 "chip#", cpi->cpi_chipid); 3180 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3181 "clog#", cpi->cpi_clogid); 3182 } 3183 } 3184 3185 /* cpuid-features */ 3186 3187 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3188 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3189 3190 3191 /* cpuid-features-ecx */ 3192 3193 switch (cpi->cpi_vendor) { 3194 case X86_VENDOR_Intel: 3195 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3196 break; 3197 default: 3198 create = 0; 3199 break; 3200 } 3201 if (create) 3202 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3203 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3204 3205 /* ext-cpuid-features */ 3206 3207 switch (cpi->cpi_vendor) { 3208 case X86_VENDOR_Intel: 3209 case X86_VENDOR_AMD: 3210 case X86_VENDOR_Cyrix: 3211 case X86_VENDOR_TM: 3212 case X86_VENDOR_Centaur: 3213 create = cpi->cpi_xmaxeax >= 0x80000001; 3214 break; 3215 default: 3216 create = 0; 3217 break; 3218 } 3219 if (create) { 3220 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3221 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3222 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3223 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3224 } 3225 3226 /* 3227 * Brand String first appeared in Intel Pentium IV, AMD K5 3228 * model 1, and Cyrix GXm. On earlier models we try and 3229 * simulate something similar .. so this string should always 3230 * same -something- about the processor, however lame. 3231 */ 3232 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3233 "brand-string", cpi->cpi_brandstr); 3234 3235 /* 3236 * Finally, cache and tlb information 3237 */ 3238 switch (x86_which_cacheinfo(cpi)) { 3239 case X86_VENDOR_Intel: 3240 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3241 break; 3242 case X86_VENDOR_Cyrix: 3243 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3244 break; 3245 case X86_VENDOR_AMD: 3246 amd_cache_info(cpi, cpu_devi); 3247 break; 3248 default: 3249 break; 3250 } 3251 3252 mutex_exit(&cpu_node_lock); 3253 } 3254 3255 struct l2info { 3256 int *l2i_csz; 3257 int *l2i_lsz; 3258 int *l2i_assoc; 3259 int l2i_ret; 3260 }; 3261 3262 /* 3263 * A cacheinfo walker that fetches the size, line-size and associativity 3264 * of the L2 cache 3265 */ 3266 static int 3267 intel_l2cinfo(void *arg, const struct cachetab *ct) 3268 { 3269 struct l2info *l2i = arg; 3270 int *ip; 3271 3272 if (ct->ct_label != l2_cache_str && 3273 ct->ct_label != sl2_cache_str) 3274 return (0); /* not an L2 -- keep walking */ 3275 3276 if ((ip = l2i->l2i_csz) != NULL) 3277 *ip = ct->ct_size; 3278 if ((ip = l2i->l2i_lsz) != NULL) 3279 *ip = ct->ct_line_size; 3280 if ((ip = l2i->l2i_assoc) != NULL) 3281 *ip = ct->ct_assoc; 3282 l2i->l2i_ret = ct->ct_size; 3283 return (1); /* was an L2 -- terminate walk */ 3284 } 3285 3286 static void 3287 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3288 { 3289 struct cpuid_regs *cp; 3290 uint_t size, assoc; 3291 int *ip; 3292 3293 if (cpi->cpi_xmaxeax < 0x80000006) 3294 return; 3295 cp = &cpi->cpi_extd[6]; 3296 3297 if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 && 3298 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3299 uint_t cachesz = size * 1024; 3300 3301 3302 if ((ip = l2i->l2i_csz) != NULL) 3303 *ip = cachesz; 3304 if ((ip = l2i->l2i_lsz) != NULL) 3305 *ip = BITX(cp->cp_ecx, 7, 0); 3306 if ((ip = l2i->l2i_assoc) != NULL) 3307 *ip = assoc; 3308 l2i->l2i_ret = cachesz; 3309 } 3310 } 3311 3312 int 3313 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3314 { 3315 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3316 struct l2info __l2info, *l2i = &__l2info; 3317 3318 l2i->l2i_csz = csz; 3319 l2i->l2i_lsz = lsz; 3320 l2i->l2i_assoc = assoc; 3321 l2i->l2i_ret = -1; 3322 3323 switch (x86_which_cacheinfo(cpi)) { 3324 case X86_VENDOR_Intel: 3325 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3326 break; 3327 case X86_VENDOR_Cyrix: 3328 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3329 break; 3330 case X86_VENDOR_AMD: 3331 amd_l2cacheinfo(cpi, l2i); 3332 break; 3333 default: 3334 break; 3335 } 3336 return (l2i->l2i_ret); 3337 } 3338 3339 size_t 3340 cpuid_get_mwait_size(cpu_t *cpu) 3341 { 3342 ASSERT(cpuid_checkpass(cpu, 2)); 3343 return (cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max); 3344 } 3345