1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * apic_introp.c: 31 * Has code for Advanced DDI interrupt framework support. 32 */ 33 34 #include <sys/cpuvar.h> 35 #include <sys/psm.h> 36 #include "apic.h" 37 #include <sys/sunddi.h> 38 #include <sys/ddi_impldefs.h> 39 #include <sys/trap.h> 40 #include <sys/pci.h> 41 #include <sys/pci_intr_lib.h> 42 43 /* 44 * Local Function Prototypes 45 */ 46 int apic_pci_msi_enable_vector(dev_info_t *, int, int, 47 int, int, int); 48 apic_irq_t *apic_find_irq(dev_info_t *, struct intrspec *, int); 49 static int apic_get_pending(apic_irq_t *, int); 50 static void apic_clear_mask(apic_irq_t *); 51 static void apic_set_mask(apic_irq_t *); 52 static uchar_t apic_find_multi_vectors(int, int); 53 int apic_navail_vector(dev_info_t *, int); 54 int apic_alloc_vectors(dev_info_t *, int, int, int, int); 55 void apic_free_vectors(dev_info_t *, int, int, int, int); 56 int apic_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *, 57 psm_intr_op_t, int *); 58 59 extern int intr_clear(void); 60 extern void intr_restore(uint_t); 61 extern uchar_t apic_bind_intr(dev_info_t *, int, uchar_t, uchar_t); 62 extern int apic_allocate_irq(int); 63 extern int apic_introp_xlate(dev_info_t *, struct intrspec *, int); 64 65 /* 66 * MSI support flag: 67 * reflects whether MSI is supported at APIC level 68 * it can also be patched through /etc/system 69 * 70 * 0 = default value - don't know and need to call apic_check_msi_support() 71 * to find out then set it accordingly 72 * 1 = supported 73 * -1 = not supported 74 */ 75 int apic_support_msi = 0; 76 77 /* Multiple vector support for MSI */ 78 int apic_multi_msi_enable = 1; 79 int apic_multi_msi_max = 2; 80 81 extern uchar_t apic_ipltopri[MAXIPL+1]; 82 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 83 extern int apic_max_device_irq; 84 extern int apic_min_device_irq; 85 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 86 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 87 extern volatile int32_t *apicioadr[MAX_IO_APIC]; 88 extern lock_t apic_ioapic_lock; 89 extern kmutex_t airq_mutex; 90 extern apic_cpus_info_t *apic_cpus; 91 92 93 /* 94 * apic_pci_msi_enable_vector: 95 * Set the address/data fields in the MSI/X capability structure 96 * XXX: MSI-X support 97 */ 98 /* ARGSUSED */ 99 int 100 apic_pci_msi_enable_vector(dev_info_t *dip, int type, int inum, int vector, 101 int count, int target_apic_id) 102 { 103 uint64_t msi_addr, msi_data; 104 105 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: dip=0x%p\n" 106 "\tdriver = %s, inum=0x%x vector=0x%x apicid=0x%x\n", (void *)dip, 107 ddi_driver_name(dip), inum, vector, target_apic_id)); 108 109 /* MSI Address */ 110 msi_addr = (MSI_ADDR_HDR | (target_apic_id << MSI_ADDR_DEST_SHIFT)); 111 msi_addr |= ((MSI_ADDR_RH_FIXED << MSI_ADDR_RH_SHIFT) | 112 (MSI_ADDR_DM_PHYSICAL << MSI_ADDR_DM_SHIFT)); 113 114 /* MSI Data: MSI is edge triggered according to spec */ 115 msi_data = ((MSI_DATA_TM_EDGE << MSI_DATA_TM_SHIFT) | vector); 116 117 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: addr=0x%lx " 118 "data=0x%lx\n", (long)msi_addr, (long)msi_data)); 119 120 if (pci_msi_configure(dip, type, count, inum, msi_addr, msi_data) != 121 DDI_SUCCESS) { 122 DDI_INTR_IMPLDBG((CE_CONT, "apic_pci_msi_enable_vector: " 123 "pci_msi_configure failed\n")); 124 return (PSM_FAILURE); 125 } 126 127 return (PSM_SUCCESS); 128 } 129 130 131 /* 132 * This function returns the no. of vectors available for the pri. 133 * dip is not used at this moment. If we really don't need that, 134 * it will be removed. 135 */ 136 /*ARGSUSED*/ 137 int 138 apic_navail_vector(dev_info_t *dip, int pri) 139 { 140 int lowest, highest, i, navail, count; 141 142 DDI_INTR_IMPLDBG((CE_CONT, "apic_navail_vector: dip: %p, pri: %x\n", 143 (void *)dip, pri)); 144 145 highest = apic_ipltopri[pri] + APIC_VECTOR_MASK; 146 lowest = apic_ipltopri[pri - 1] + APIC_VECTOR_PER_IPL; 147 navail = count = 0; 148 149 /* It has to be contiguous */ 150 for (i = lowest; i < highest; i++) { 151 count = 0; 152 while ((apic_vector_to_irq[i] == APIC_RESV_IRQ) && 153 (i < highest)) { 154 if ((i == T_FASTTRAP) || (i == APIC_SPUR_INTR)) 155 break; 156 count++; 157 i++; 158 } 159 if (count > navail) 160 navail = count; 161 } 162 return (navail); 163 } 164 165 static uchar_t 166 apic_find_multi_vectors(int pri, int count) 167 { 168 int lowest, highest, i, navail, start; 169 170 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_mult: pri: %x, count: %x\n", 171 pri, count)); 172 173 highest = apic_ipltopri[pri] + APIC_VECTOR_MASK; 174 lowest = apic_ipltopri[pri - 1] + APIC_VECTOR_PER_IPL; 175 navail = 0; 176 177 /* It has to be contiguous */ 178 for (i = lowest; i < highest; i++) { 179 navail = 0; 180 start = i; 181 while ((apic_vector_to_irq[i] == APIC_RESV_IRQ) && 182 (i < highest)) { 183 if ((i == T_FASTTRAP) || (i == APIC_SPUR_INTR)) 184 break; 185 navail++; 186 if (navail >= count) 187 return (start); 188 i++; 189 } 190 } 191 return (0); 192 } 193 194 195 /* 196 * It finds the apic_irq_t associates with the dip, ispec and type. 197 */ 198 apic_irq_t * 199 apic_find_irq(dev_info_t *dip, struct intrspec *ispec, int type) 200 { 201 apic_irq_t *irqp; 202 int i; 203 204 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_irq: dip=0x%p vec=0x%x " 205 "ipl=0x%x type=0x%x\n", (void *)dip, ispec->intrspec_vec, 206 ispec->intrspec_pri, type)); 207 208 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 209 if ((irqp = apic_irq_table[i]) == NULL) 210 continue; 211 if ((irqp->airq_dip == dip) && 212 (irqp->airq_origirq == ispec->intrspec_vec) && 213 (irqp->airq_ipl == ispec->intrspec_pri)) { 214 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 215 if (APIC_IS_MSI_OR_MSIX_INDEX(irqp-> 216 airq_mps_intr_index)) 217 return (irqp); 218 } else 219 return (irqp); 220 } 221 } 222 DDI_INTR_IMPLDBG((CE_CONT, "apic_find_irq: return NULL\n")); 223 return (NULL); 224 } 225 226 227 /* 228 * This function will return the pending bit of the irqp. 229 * It either comes from the IRR register of the APIC or the RDT 230 * entry of the I/O APIC. 231 * For the IRR to work, it needs to be to its binding CPU 232 */ 233 static int 234 apic_get_pending(apic_irq_t *irqp, int type) 235 { 236 int bit, index, irr, pending; 237 int intin_no; 238 volatile int32_t *ioapic; 239 240 DDI_INTR_IMPLDBG((CE_CONT, "apic_get_pending: irqp: %p, cpuid: %x " 241 "type: %x\n", (void *)irqp, irqp->airq_cpu & ~IRQ_USER_BOUND, 242 type)); 243 244 /* need to get on the bound cpu */ 245 mutex_enter(&cpu_lock); 246 affinity_set(irqp->airq_cpu & ~IRQ_USER_BOUND); 247 248 index = irqp->airq_vector / 32; 249 bit = irqp->airq_vector % 32; 250 irr = apicadr[APIC_IRR_REG + index]; 251 252 affinity_clear(); 253 mutex_exit(&cpu_lock); 254 255 pending = (irr & (1 << bit)) ? 1 : 0; 256 if (!pending && (type == DDI_INTR_TYPE_FIXED)) { 257 /* check I/O APIC for fixed interrupt */ 258 intin_no = irqp->airq_intin_no; 259 ioapic = apicioadr[irqp->airq_ioapicindex]; 260 pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no) & 261 AV_PENDING) ? 1 : 0; 262 } 263 return (pending); 264 } 265 266 267 /* 268 * This function will clear the mask for the interrupt on the I/O APIC 269 */ 270 static void 271 apic_clear_mask(apic_irq_t *irqp) 272 { 273 int intin_no; 274 int iflag; 275 int32_t rdt_entry; 276 volatile int32_t *ioapic; 277 278 DDI_INTR_IMPLDBG((CE_CONT, "apic_clear_mask: irqp: %p\n", 279 (void *)irqp)); 280 281 intin_no = irqp->airq_intin_no; 282 ioapic = apicioadr[irqp->airq_ioapicindex]; 283 284 iflag = intr_clear(); 285 lock_set(&apic_ioapic_lock); 286 287 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no); 288 289 /* clear mask */ 290 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no, 291 ((~AV_MASK) & rdt_entry)); 292 293 lock_clear(&apic_ioapic_lock); 294 intr_restore(iflag); 295 } 296 297 298 /* 299 * This function will mask the interrupt on the I/O APIC 300 */ 301 static void 302 apic_set_mask(apic_irq_t *irqp) 303 { 304 int intin_no; 305 volatile int32_t *ioapic; 306 int iflag; 307 int32_t rdt_entry; 308 309 DDI_INTR_IMPLDBG((CE_CONT, "apic_set_mask: irqp: %p\n", (void *)irqp)); 310 311 intin_no = irqp->airq_intin_no; 312 ioapic = apicioadr[irqp->airq_ioapicindex]; 313 314 iflag = intr_clear(); 315 316 lock_set(&apic_ioapic_lock); 317 318 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no); 319 320 /* mask it */ 321 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no, 322 (AV_MASK | rdt_entry)); 323 324 lock_clear(&apic_ioapic_lock); 325 intr_restore(iflag); 326 } 327 328 329 /* 330 * This function allocate "count" vector(s) for the given "dip/pri/type" 331 */ 332 int 333 apic_alloc_vectors(dev_info_t *dip, int inum, int count, int pri, int type) 334 { 335 int rcount, i; 336 uchar_t start, irqno, cpu; 337 short idx; 338 major_t major; 339 apic_irq_t *irqptr; 340 341 /* for MSI/X only */ 342 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) 343 return (0); 344 345 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_vectors: dip=0x%p type=%d " 346 "inum=0x%x pri=0x%x count=0x%x\n", 347 (void *)dip, type, inum, pri, count)); 348 349 if (count > 1) { 350 if (apic_multi_msi_enable == 0) 351 count = 1; 352 else if (count > apic_multi_msi_max) 353 count = apic_multi_msi_max; 354 } 355 356 if ((rcount = apic_navail_vector(dip, pri)) > count) 357 rcount = count; 358 359 mutex_enter(&airq_mutex); 360 361 for (start = 0; rcount > 0; rcount--) { 362 if ((start = apic_find_multi_vectors(pri, rcount)) != 0) 363 break; 364 } 365 366 if (start == 0) { 367 /* no vector available */ 368 mutex_exit(&airq_mutex); 369 return (0); 370 } 371 372 idx = (short)((type == DDI_INTR_TYPE_MSI) ? MSI_INDEX : MSIX_INDEX); 373 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 374 for (i = 0; i < rcount; i++) { 375 if ((irqno = apic_allocate_irq(APIC_FIRST_FREE_IRQ)) == 376 (uchar_t)-1) { 377 mutex_exit(&airq_mutex); 378 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_vectors: " 379 "apic_allocate_irq failed\n")); 380 return (i); 381 } 382 apic_max_device_irq = max(irqno, apic_max_device_irq); 383 apic_min_device_irq = min(irqno, apic_min_device_irq); 384 irqptr = apic_irq_table[irqno]; 385 #ifdef DEBUG 386 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 387 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_vectors: " 388 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 389 #endif 390 apic_vector_to_irq[start + i] = (uchar_t)irqno; 391 392 irqptr->airq_vector = (uchar_t)(start + i); 393 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 394 irqptr->airq_intin_no = (uchar_t)rcount; 395 irqptr->airq_ipl = pri; 396 irqptr->airq_vector = start + i; 397 irqptr->airq_origirq = (uchar_t)(inum + i); 398 irqptr->airq_share_id = 0; 399 irqptr->airq_mps_intr_index = idx; 400 irqptr->airq_dip = dip; 401 irqptr->airq_major = major; 402 if (i == 0) /* they all bound to the same cpu */ 403 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 404 0xff, 0xff); 405 else 406 irqptr->airq_cpu = cpu; 407 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_vectors: irq=0x%x " 408 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 409 (void *)irqptr->airq_dip, irqptr->airq_vector, 410 irqptr->airq_origirq, pri)); 411 } 412 mutex_exit(&airq_mutex); 413 return (rcount); 414 } 415 416 417 void 418 apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, int type) 419 { 420 int i; 421 apic_irq_t *irqptr; 422 struct intrspec ispec; 423 424 DDI_INTR_IMPLDBG((CE_CONT, "apic_free_vectors: dip: %p inum: %x " 425 "count: %x pri: %x type: %x\n", 426 (void *)dip, inum, count, pri, type)); 427 428 /* for MSI/X only */ 429 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) 430 return; 431 432 for (i = 0; i < count; i++) { 433 DDI_INTR_IMPLDBG((CE_CONT, "apic_free_vectors: inum=0x%x " 434 "pri=0x%x count=0x%x\n", inum, pri, count)); 435 ispec.intrspec_vec = inum + i; 436 ispec.intrspec_pri = pri; 437 if ((irqptr = apic_find_irq(dip, &ispec, type)) == NULL) { 438 DDI_INTR_IMPLDBG((CE_CONT, "apic_free_vectors: " 439 "dip=0x%p inum=0x%x pri=0x%x apic_find_irq() " 440 "failed\n", (void *)dip, inum, pri)); 441 continue; 442 } 443 irqptr->airq_mps_intr_index = FREE_INDEX; 444 apic_vector_to_irq[irqptr->airq_vector] = APIC_RESV_IRQ; 445 } 446 } 447 448 449 /* 450 * check whether the system supports MSI 451 * 452 * If PCI-E capability is found, then this must be a PCI-E system. 453 * Since MSI is required for PCI-E system, it returns PSM_SUCCESS 454 * to indicate this system supports MSI. 455 */ 456 int 457 apic_check_msi_support(dev_info_t *dip) 458 { 459 460 dev_info_t *rootdip; 461 462 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: dip: 0x%p\n", 463 (void *)dip)); 464 465 /* check whether the device or its ancestors have PCI-E capability */ 466 for (rootdip = ddi_root_node(); dip != rootdip && 467 pci_check_pciex(dip) != DDI_SUCCESS; dip = ddi_get_parent(dip)); 468 469 /* PCI-E capability found */ 470 if (dip != rootdip) { 471 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: " 472 "PCI-E capability found @ nodename %s driver %s%d\n", 473 ddi_node_name(dip), ddi_driver_name(dip), 474 ddi_get_instance(dip))); 475 return (PSM_SUCCESS); 476 } 477 478 /* MSI is not supported on this system */ 479 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: " 480 "no PCI-E capability found\n")); 481 return (PSM_FAILURE); 482 } 483 484 /* 485 * This function provides external interface to the nexus for all 486 * functionalities related to the new DDI interrupt framework. 487 * 488 * Input: 489 * dip - pointer to the dev_info structure of the requested device 490 * hdlp - pointer to the internal interrupt handle structure for the 491 * requested interrupt 492 * intr_op - opcode for this call 493 * result - pointer to the integer that will hold the result to be 494 * passed back if return value is PSM_SUCCESS 495 * 496 * Output: 497 * return value is either PSM_SUCCESS or PSM_FAILURE 498 */ 499 int 500 apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 501 psm_intr_op_t intr_op, int *result) 502 { 503 int cap; 504 int count_vec; 505 int old_priority; 506 int new_priority; 507 apic_irq_t *irqp; 508 struct intrspec *ispec, intr_spec; 509 510 DDI_INTR_IMPLDBG((CE_CONT, "apic_intr_ops: dip: %p hdlp: %p " 511 "intr_op: %x\n", (void *)dip, (void *)hdlp, intr_op)); 512 513 ispec = &intr_spec; 514 ispec->intrspec_pri = hdlp->ih_pri; 515 ispec->intrspec_vec = hdlp->ih_inum; 516 ispec->intrspec_func = hdlp->ih_cb_func; 517 518 switch (intr_op) { 519 case PSM_INTR_OP_CHECK_MSI: 520 /* 521 * Check MSI/X is supported or not at APIC level and 522 * masked off the MSI/X bits in hdlp->ih_type if not 523 * supported before return. If MSI/X is supported, 524 * leave the ih_type unchanged and return. 525 * 526 * hdlp->ih_type passed in from the nexus has all the 527 * interrupt types supported by the device. 528 */ 529 if (apic_support_msi == 0) { 530 /* 531 * if apic_support_msi is not set, call 532 * apic_check_msi_support() to check whether msi 533 * is supported first 534 */ 535 if (apic_check_msi_support(dip) == PSM_SUCCESS) 536 apic_support_msi = 1; 537 else 538 apic_support_msi = -1; 539 } 540 if (apic_support_msi == 1) 541 *result = hdlp->ih_type; 542 else 543 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI | 544 DDI_INTR_TYPE_MSIX); 545 break; 546 case PSM_INTR_OP_ALLOC_VECTORS: 547 *result = apic_alloc_vectors(dip, hdlp->ih_inum, 548 hdlp->ih_scratch1, hdlp->ih_pri, hdlp->ih_type); 549 break; 550 case PSM_INTR_OP_FREE_VECTORS: 551 apic_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1, 552 hdlp->ih_pri, hdlp->ih_type); 553 break; 554 case PSM_INTR_OP_NAVAIL_VECTORS: 555 *result = apic_navail_vector(dip, hdlp->ih_pri); 556 break; 557 case PSM_INTR_OP_XLATE_VECTOR: 558 ispec = (struct intrspec *)hdlp->ih_private; 559 *result = apic_introp_xlate(dip, ispec, hdlp->ih_type); 560 break; 561 case PSM_INTR_OP_GET_PENDING: 562 if ((irqp = apic_find_irq(dip, ispec, hdlp->ih_type)) == NULL) 563 return (PSM_FAILURE); 564 *result = apic_get_pending(irqp, hdlp->ih_type); 565 break; 566 case PSM_INTR_OP_CLEAR_MASK: 567 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 568 return (PSM_FAILURE); 569 irqp = apic_find_irq(dip, ispec, hdlp->ih_type); 570 if (irqp == NULL) 571 return (PSM_FAILURE); 572 apic_clear_mask(irqp); 573 break; 574 case PSM_INTR_OP_SET_MASK: 575 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 576 return (PSM_FAILURE); 577 if ((irqp = apic_find_irq(dip, ispec, hdlp->ih_type)) == NULL) 578 return (PSM_FAILURE); 579 apic_set_mask(irqp); 580 break; 581 case PSM_INTR_OP_GET_CAP: 582 cap = DDI_INTR_FLAG_PENDING; 583 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 584 cap |= DDI_INTR_FLAG_MASKABLE; 585 *result = cap; 586 break; 587 case PSM_INTR_OP_GET_SHARED: 588 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 589 return (PSM_FAILURE); 590 if ((irqp = apic_find_irq(dip, ispec, hdlp->ih_type)) == NULL) 591 return (PSM_FAILURE); 592 *result = irqp->airq_share ? 1: 0; 593 break; 594 case PSM_INTR_OP_SET_PRI: 595 old_priority = hdlp->ih_pri; /* save old value */ 596 new_priority = *(int *)result; /* try the new value */ 597 598 /* First, check if "hdlp->ih_scratch1" vectors exist? */ 599 if (apic_navail_vector(dip, new_priority) < hdlp->ih_scratch1) 600 return (PSM_FAILURE); 601 602 /* Now allocate the vectors */ 603 count_vec = apic_alloc_vectors(dip, hdlp->ih_inum, 604 hdlp->ih_scratch1, new_priority, hdlp->ih_type); 605 606 /* Did we get fewer vectors? */ 607 if (count_vec != hdlp->ih_scratch1) { 608 apic_free_vectors(dip, hdlp->ih_inum, count_vec, 609 new_priority, hdlp->ih_type); 610 return (PSM_FAILURE); 611 } 612 613 /* Finally, free the previously allocated vectors */ 614 apic_free_vectors(dip, hdlp->ih_inum, count_vec, 615 old_priority, hdlp->ih_type); 616 hdlp->ih_pri = new_priority; /* set the new value */ 617 break; 618 case PSM_INTR_OP_SET_CAP: 619 default: 620 return (PSM_FAILURE); 621 } 622 return (PSM_SUCCESS); 623 } 624