xref: /titanic_41/usr/src/uts/i86pc/io/pci/pci_common.h (revision 3ad28c1e51ef5773481ccea340f94723d9d7b1aa)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 
23 /*
24  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
25  * Use is subject to license terms.
26  */
27 
28 #ifndef	_PCI_PCI_COMMON_H
29 #define	_PCI_PCI_COMMON_H
30 
31 #pragma ident	"%Z%%M%	%I%	%E% SMI"
32 
33 #ifdef	__cplusplus
34 extern "C" {
35 #endif
36 
37 /*
38  *	Common header file with definitions shared between
39  *	pci(7d) and npe(7d)
40  */
41 
42 /* State structure. */
43 typedef struct pci_state {
44 	dev_info_t *pci_dip;
45 } pci_state_t;
46 
47 /* AMD's northbridges vendor-id and device-ids */
48 #define	AMD_NTBRDIGE_VID		0x1022	/* AMD vendor-id */
49 #define	AMD_HT_NTBRIDGE_DID		0x1100	/* HT Configuration */
50 #define	AMD_AM_NTBRIDGE_DID		0x1101	/* Address Map */
51 #define	AMD_DC_NTBRIDGE_DID		0x1102	/* DRAM Controller */
52 #define	AMD_MC_NTBRIDGE_DID		0x1103	/* Misc Controller */
53 
54 /*
55  * Check if the given device is an AMD northbridge
56  */
57 #define	IS_AMD_NTBRIDGE(vid, did) \
58 	    (((vid) == AMD_NTBRDIGE_VID) && \
59 	    (((did) == AMD_HT_NTBRIDGE_DID) || \
60 	    ((did) == AMD_AM_NTBRIDGE_DID) || \
61 	    ((did) == AMD_DC_NTBRIDGE_DID) || \
62 	    ((did) == AMD_MC_NTBRIDGE_DID)))
63 
64 /*
65  * Check if the give device is a PCI northbridge
66  */
67 int		is_amd_northbridge(dev_info_t *dip);
68 
69 /*
70  * These are the access routines.
71  * The pci_bus_map sets the handle to point to these in pci(7d).
72  * The npe_bus_map sets the handle to point to these in npe(7d).
73  */
74 uint8_t		pci_config_rd8(ddi_acc_impl_t *hdlp, uint8_t *addr);
75 uint16_t	pci_config_rd16(ddi_acc_impl_t *hdlp, uint16_t *addr);
76 uint32_t	pci_config_rd32(ddi_acc_impl_t *hdlp, uint32_t *addr);
77 uint64_t	pci_config_rd64(ddi_acc_impl_t *hdlp, uint64_t *addr);
78 
79 void		pci_config_wr8(ddi_acc_impl_t *hdlp, uint8_t *addr,
80 		    uint8_t value);
81 void		pci_config_wr16(ddi_acc_impl_t *hdlp, uint16_t *addr,
82 		    uint16_t value);
83 void		pci_config_wr32(ddi_acc_impl_t *hdlp, uint32_t *addr,
84 		    uint32_t value);
85 void		pci_config_wr64(ddi_acc_impl_t *hdlp, uint64_t *addr,
86 		    uint64_t value);
87 
88 void		pci_config_rep_rd8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
89 		    uint8_t *dev_addr, size_t repcount, uint_t flags);
90 void		pci_config_rep_rd16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
91 		    uint16_t *dev_addr, size_t repcount, uint_t flags);
92 void		pci_config_rep_rd32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
93 		    uint32_t *dev_addr, size_t repcount, uint_t flags);
94 void		pci_config_rep_rd64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
95 		    uint64_t *dev_addr, size_t repcount, uint_t flags);
96 
97 void		pci_config_rep_wr8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
98 		    uint8_t *dev_addr, size_t repcount, uint_t flags);
99 void		pci_config_rep_wr16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
100 		    uint16_t *dev_addr, size_t repcount, uint_t flags);
101 void		pci_config_rep_wr32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
102 		    uint32_t *dev_addr, size_t repcount, uint_t flags);
103 void		pci_config_rep_wr64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
104 		    uint64_t *dev_addr, size_t repcount, uint_t flags);
105 
106 /*
107  * PCI tool related declarations
108  */
109 int	pci_common_ioctl(dev_info_t *dip, dev_t dev, int cmd,
110 	    intptr_t arg, int mode, cred_t *credp, int *rvalp);
111 
112 /*
113  * Interrupt related declaration
114  */
115 int	pci_common_intr_ops(dev_info_t *, dev_info_t *, ddi_intr_op_t,
116 	    ddi_intr_handle_impl_t *, void *);
117 void	pci_common_set_parent_private_data(dev_info_t *);
118 
119 /*
120  * Miscellaneous library functions
121  */
122 int	pci_common_get_reg_prop(dev_info_t *dip, pci_regspec_t *pci_rp);
123 int	pci_common_name_child(dev_info_t *child, char *name, int namelen);
124 
125 #ifdef	__cplusplus
126 }
127 #endif
128 
129 #endif	/* _PCI_PCI_COMMON_H */
130