xref: /titanic_41/usr/src/uts/common/sys/pic.h (revision 70025d765b044c6d8594bb965a2247a61e991a99)
1  /*
2   * CDDL HEADER START
3   *
4   * The contents of this file are subject to the terms of the
5   * Common Development and Distribution License, Version 1.0 only
6   * (the "License").  You may not use this file except in compliance
7   * with the License.
8   *
9   * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10   * or http://www.opensolaris.org/os/licensing.
11   * See the License for the specific language governing permissions
12   * and limitations under the License.
13   *
14   * When distributing Covered Code, include this CDDL HEADER in each
15   * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16   * If applicable, add the following below this CDDL HEADER, with the
17   * fields enclosed by brackets "[]" replaced with your own identifying
18   * information: Portions Copyright [yyyy] [name of copyright owner]
19   *
20   * CDDL HEADER END
21   */
22  /*
23   * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24   * Use is subject to license terms.
25   */
26  
27  /*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
28  /*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
29  /*	  All Rights Reserved  	*/
30  
31  #ifndef _SYS_PIC_H
32  #define	_SYS_PIC_H
33  
34  #pragma ident	"%Z%%M%	%I%	%E% SMI"
35  
36  #include <sys/avintr.h>
37  
38  #ifdef	__cplusplus
39  extern "C" {
40  #endif
41  
42  /* Definitions for 8259 Programmable Interrupt Controller */
43  
44  #define	PIC_NEEDICW4	0x01		/* ICW4 needed */
45  #define	PIC_ICW1BASE	0x10		/* base for ICW1 */
46  #define	PIC_LTIM	0x08		/* level-triggered mode */
47  #define	PIC_86MODE	0x01		/* MCS 86 mode */
48  #define	PIC_AUTOEOI	0x02		/* do auto eoi's */
49  #define	PIC_SLAVEBUF	0x08		/* put slave in buffered mode */
50  #define	PIC_MASTERBUF	0x0C		/* put master in buffered mode */
51  #define	PIC_SPFMODE	0x10		/* special fully nested mode */
52  #define	PIC_READISR	0x0B		/* Read the ISR */
53  #define	PIC_READIRR	0x0A		/* Read the IRR */
54  #define	PIC_NSEOI	0x20		/* Non-specific EOI command */
55  #define	PIC_SEOI	0x60		/* specific EOI command */
56  #define	PIC_SEOI_LVL7	(PIC_SEOI | 0x7)	/* specific EOI for level 7 */
57  
58  #if defined(__i386) || defined(__amd64)
59  #define	PIC_VECTBASE	0x20		/* Vectors for external interrupts */
60  					/* start at 32. */
61  #endif	/* __i386 || __amd64 */
62  
63  /*
64   * Interrupt configuration information specific to a particular computer.
65   * These constants are used to initialize tables in modules/pic/space.c.
66   * NOTE: The master pic must always be pic zero.
67   */
68  
69  #define	NPIC		2		/* 2 PICs */
70  /* Port addresses */
71  #define	MCMD_PORT	0x20		/* master command port */
72  #define	MIMR_PORT	0x21		/* master intr mask register port */
73  #define	SCMD_PORT	0xA0		/* slave command port */
74  #define	SIMR_PORT	0xA1		/* slave intr mask register port */
75  #define	MASTERLINE	0x02		/* slave on IR2 of master PIC */
76  #define	SLAVEBASE	8		/* slave IR0 interrupt number */
77  #define	PICBUFFERED	0		/* PICs not in buffered mode */
78  
79  struct standard_pic {
80  	short c_npic;
81  	uchar_t c_curmask[NPIC];
82  	uchar_t c_iplmask[MAXIPL*NPIC];
83  };
84  
85  #define	CLOCK_VECTOR	0 	/* line at which clock interrupt comes */
86  
87  #ifdef	__cplusplus
88  }
89  #endif
90  
91  #endif /* _SYS_PIC_H */
92