1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIFM_H 27 #define _SYS_PCIFM_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/dditypes.h> /* for ddi_acc_handle_t */ 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 38 /* 39 * PCI device type defines. 40 */ 41 #define PCI_BRIDGE_DEV 0x02 42 #define PCIX_DEV 0x04 43 #define PCIEX_DEV 0x08 44 #define PCIEX_ADV_DEV 0x10 45 #define PCIEX_RC_DEV 0x20 46 #define PCIEX_2PCI_DEV 0x40 47 48 /* 49 * PCI and PCI-X valid flags 50 */ 51 #define PCI_ERR_STATUS_VALID 0x1 52 #define PCI_BDG_SEC_STAT_VALID 0x2 53 #define PCI_BDG_CTRL_VALID 0x4 54 #define PCIX_ERR_STATUS_VALID 0x8 55 #define PCIX_ERR_ECC_STS_VALID 0x10 56 #define PCIX_ERR_S_ECC_STS_VALID 0x20 57 #define PCIX_BDG_STATUS_VALID 0x40 58 #define PCIX_BDG_SEC_STATUS_VALID 0x80 59 60 /* 61 * PCI Express valid flags 62 */ 63 #define PCIE_ERR_STATUS_VALID 0x1 64 #define PCIE_CE_STATUS_VALID 0x2 65 #define PCIE_UE_STATUS_VALID 0x4 66 #define PCIE_RC_ERR_STATUS_VALID 0x8 67 #define PCIE_SUE_STATUS_VALID 0x10 68 #define PCIE_SUE_HDR_VALID 0x20 69 #define PCIE_UE_HDR_VALID 0x40 70 #define PCIE_SRC_ID_VALID 0x80 71 72 /* 73 * PCI(-X) structures used (by pci_ereport_setup, pci_ereport_post, and 74 * pci_ereport_teardown) to gather and report errors detected by PCI(-X) 75 * compliant devices. 76 */ 77 typedef struct pci_bdg_error_regs { 78 uint16_t pci_bdg_vflags; /* status valid bits */ 79 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 80 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 81 } pci_bdg_error_regs_t; 82 83 typedef struct pci_error_regs { 84 uint16_t pci_vflags; /* status valid bits */ 85 uint8_t pci_cap_ptr; /* PCI Capability pointer */ 86 uint16_t pci_err_status; /* pci status register */ 87 uint16_t pci_cfg_comm; /* pci command register */ 88 pci_bdg_error_regs_t *pci_bdg_regs; 89 } pci_error_regs_t; 90 91 typedef struct pci_erpt { 92 ddi_acc_handle_t pe_hdl; /* Config space access handle */ 93 uint64_t pe_dflags; /* Device type flags */ 94 uint16_t pe_bdf; /* bus/device/function of device */ 95 pci_error_regs_t *pe_pci_regs; /* PCI generic error registers */ 96 void *pe_regs; /* Pointer to extended error regs */ 97 } pci_erpt_t; 98 99 typedef struct pcix_ecc_regs { 100 uint16_t pcix_ecc_vflags; /* pcix ecc valid flags */ 101 uint16_t pcix_ecc_bdf; /* pcix ecc bdf */ 102 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 103 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 104 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 105 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 106 } pcix_ecc_regs_t; 107 108 typedef struct pcix_error_regs { 109 uint16_t pcix_vflags; /* pcix valid flags */ 110 uint8_t pcix_cap_ptr; /* pcix capability pointer */ 111 uint16_t pcix_ver; /* pcix version */ 112 uint16_t pcix_command; /* pcix command register */ 113 uint32_t pcix_status; /* pcix status register */ 114 pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 115 } pcix_error_regs_t; 116 117 typedef struct pcix_bdg_error_regs { 118 uint16_t pcix_bdg_vflags; /* pcix valid flags */ 119 uint8_t pcix_bdg_cap_ptr; /* pcix bridge capability pointer */ 120 uint16_t pcix_bdg_ver; /* pcix version */ 121 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 122 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 123 pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 124 } pcix_bdg_error_regs_t; 125 126 /* 127 * PCI Express error register structures used (by pci_ereport_setup, 128 * pci_ereport_post, and pci_ereport_teardown) to gather and report errors 129 * detected by PCI Express compliant devices. 130 */ 131 typedef struct pcie_adv_bdg_error_regs { 132 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 133 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 134 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 135 uint32_t pcie_sue_hdr0; /* pcie bridge secondary ue hdr log */ 136 uint32_t pcie_sue_hdr[3]; /* pcie bridge secondary ue hdr log */ 137 } pcie_adv_bdg_error_regs_t; 138 139 typedef struct pcie_adv_rc_error_regs { 140 uint32_t pcie_rc_err_status; /* pcie root complex error status reg */ 141 uint32_t pcie_rc_err_cmd; /* pcie root complex error cmd reg */ 142 uint16_t pcie_rc_ce_src_id; /* pcie root complex ce source id */ 143 uint16_t pcie_rc_ue_src_id; /* pcie root complex ue source id */ 144 } pcie_adv_rc_error_regs_t; 145 146 typedef struct pcie_adv_error_regs { 147 uint16_t pcie_adv_vflags; /* pcie advanced error valid flags */ 148 uint16_t pcie_adv_cap_ptr; /* pcie advanced capability pointer */ 149 uint16_t pcie_adv_bdf; /* pcie bdf */ 150 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 151 uint32_t pcie_ce_status; /* pcie ce error status reg */ 152 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 153 uint32_t pcie_ue_status; /* pcie ue error status reg */ 154 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 155 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 156 uint32_t pcie_ue_hdr0; /* pcie ue header log */ 157 uint32_t pcie_ue_hdr[3]; /* pcie ue header log */ 158 pcie_adv_bdg_error_regs_t *pcie_adv_bdg_regs; /* pcie bridge regs */ 159 pcie_adv_rc_error_regs_t *pcie_adv_rc_regs; /* pcie rc regs */ 160 } pcie_adv_error_regs_t; 161 162 typedef struct pcie_rc_error_regs { 163 uint32_t pcie_rc_status; /* root complex status register */ 164 uint16_t pcie_rc_ctl; /* root complex control register */ 165 } pcie_rc_error_regs_t; 166 167 typedef struct pcie_error_regs { 168 uint16_t pcie_vflags; /* pcie valid flags */ 169 uint8_t pcie_cap_ptr; /* PCI Express capability pointer */ 170 uint16_t pcie_cap; /* PCI Express capability register */ 171 uint16_t pcie_err_status; /* pcie device status register */ 172 uint16_t pcie_err_ctl; /* pcie error control register */ 173 uint16_t pcie_dev_cap; /* pcie device capabilities register */ 174 pcix_bdg_error_regs_t *pcix_bdg_regs; /* pcix bridge regs */ 175 pcie_rc_error_regs_t *pcie_rc_regs; /* pcie root complex regs */ 176 pcie_adv_error_regs_t *pcie_adv_regs; /* pcie advanced err regs */ 177 } pcie_error_regs_t; 178 179 /* 180 * pcie bus specific structure 181 */ 182 183 typedef struct pci_fme_bus_specific { 184 int pci_bs_type; 185 uint64_t pci_bs_addr; 186 uint16_t pci_bs_bdf; 187 int pci_bs_flags; 188 } pci_fme_bus_specific_t; 189 190 #define PCI_BS_ADDR_VALID 1 191 #define PCI_BS_BDF_VALID 2 192 193 /* 194 * target error queue defines 195 */ 196 #define TARGET_MAX_ERRS 6 197 #define TGT_PCI_SPACE_UNKNOWN 4 198 199 typedef struct pci_target_err { 200 uint64_t tgt_err_addr; 201 uint64_t tgt_err_ena; 202 uint64_t tgt_pci_addr; 203 uint32_t tgt_pci_space; 204 dev_info_t *tgt_dip; 205 char *tgt_err_class; 206 char *tgt_bridge_type; 207 } pci_target_err_t; 208 209 #define PCI_FM_SEV_INC(x) ((x) == DDI_FM_FATAL) ? fatal++ :\ 210 (((x) == DDI_FM_NONFATAL) ? nonfatal++ :\ 211 (((x) == DDI_FM_UNKNOWN) ? unknown++ : ok++)); 212 213 #define PCIEX_TYPE_CE 0x0 214 #define PCIEX_TYPE_UE 0x1 215 #define PCIEX_TYPE_GEN 0x2 216 #define PCIEX_TYPE_RC_UE_MSG 0x3 217 #define PCIEX_TYPE_RC_CE_MSG 0x4 218 #define PCIEX_TYPE_RC_MULT_MSG 0x5 219 220 #ifdef __cplusplus 221 } 222 #endif 223 224 #endif /* _SYS_PCIFM_H */ 225