1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIFM_H 27 #define _SYS_PCIFM_H 28 29 #include <sys/dditypes.h> /* for ddi_acc_handle_t */ 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 36 /* 37 * PCI device type defines. 38 */ 39 #define PCI_BRIDGE_DEV 0x02 40 #define PCIX_DEV 0x04 41 42 /* 43 * PCI and PCI-X valid flags 44 */ 45 #define PCI_ERR_STATUS_VALID 0x1 46 #define PCI_BDG_SEC_STAT_VALID 0x2 47 #define PCI_BDG_CTRL_VALID 0x4 48 #define PCIX_ERR_STATUS_VALID 0x8 49 #define PCIX_ERR_ECC_STS_VALID 0x10 50 #define PCIX_ERR_S_ECC_STS_VALID 0x20 51 #define PCIX_BDG_STATUS_VALID 0x40 52 #define PCIX_BDG_SEC_STATUS_VALID 0x80 53 54 55 /* 56 * PCI(-X) structures used (by pci_ereport_setup, pci_ereport_post, and 57 * pci_ereport_teardown) to gather and report errors detected by PCI(-X) 58 * compliant devices. 59 */ 60 typedef struct pci_bdg_error_regs { 61 uint16_t pci_bdg_vflags; /* status valid bits */ 62 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 63 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 64 } pci_bdg_error_regs_t; 65 66 typedef struct pci_error_regs { 67 uint16_t pci_vflags; /* status valid bits */ 68 uint8_t pci_cap_ptr; /* PCI Capability pointer */ 69 uint16_t pci_err_status; /* pci status register */ 70 uint16_t pci_cfg_comm; /* pci command register */ 71 pci_bdg_error_regs_t *pci_bdg_regs; 72 } pci_error_regs_t; 73 74 typedef struct pci_erpt { 75 ddi_acc_handle_t pe_hdl; /* Config space access handle */ 76 uint64_t pe_dflags; /* Device type flags */ 77 uint16_t pe_bdf; /* bus/device/function of device */ 78 pci_error_regs_t *pe_pci_regs; /* PCI generic error registers */ 79 void *pe_regs; /* Pointer to extended error regs */ 80 } pci_erpt_t; 81 82 typedef struct pcix_ecc_regs { 83 uint16_t pcix_ecc_vflags; /* pcix ecc valid flags */ 84 uint16_t pcix_ecc_bdf; /* pcix ecc bdf */ 85 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 86 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 87 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 88 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 89 } pcix_ecc_regs_t; 90 91 typedef struct pcix_error_regs { 92 uint16_t pcix_vflags; /* pcix valid flags */ 93 uint8_t pcix_cap_ptr; /* pcix capability pointer */ 94 uint16_t pcix_ver; /* pcix version */ 95 uint16_t pcix_command; /* pcix command register */ 96 uint32_t pcix_status; /* pcix status register */ 97 pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 98 } pcix_error_regs_t; 99 100 typedef struct pcix_bdg_error_regs { 101 uint16_t pcix_bdg_vflags; /* pcix valid flags */ 102 uint8_t pcix_bdg_cap_ptr; /* pcix bridge capability pointer */ 103 uint16_t pcix_bdg_ver; /* pcix version */ 104 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 105 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 106 pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 107 } pcix_bdg_error_regs_t; 108 109 /* 110 * pcie bus specific structure 111 */ 112 113 typedef struct pci_fme_bus_specific { 114 int pci_bs_type; 115 uint64_t pci_bs_addr; 116 uint16_t pci_bs_bdf; 117 int pci_bs_flags; 118 } pci_fme_bus_specific_t; 119 120 #define PCI_BS_ADDR_VALID 1 121 #define PCI_BS_BDF_VALID 2 122 123 /* 124 * target error queue defines 125 */ 126 #define TARGET_MAX_ERRS 6 127 #define TGT_PCI_SPACE_UNKNOWN 4 128 129 typedef struct pci_target_err { 130 uint64_t tgt_err_addr; 131 uint64_t tgt_err_ena; 132 uint64_t tgt_pci_addr; 133 uint32_t tgt_pci_space; 134 dev_info_t *tgt_dip; 135 char *tgt_err_class; 136 char *tgt_bridge_type; 137 } pci_target_err_t; 138 139 #define PCI_FM_SEV_INC(x) ((x) == DDI_FM_FATAL) ? fatal++ :\ 140 (((x) == DDI_FM_NONFATAL) ? nonfatal++ :\ 141 (((x) == DDI_FM_UNKNOWN) ? unknown++ : ok++)); 142 143 #ifdef __cplusplus 144 } 145 #endif 146 147 #endif /* _SYS_PCIFM_H */ 148