1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIE_IMPL_H 27 #define _SYS_PCIE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/pcie.h> 36 37 /* PCI-E config space data for error handling and ereport */ 38 typedef struct pf_data { 39 dev_info_t *dip; 40 pcie_req_id_t bdf; 41 uint32_t severity_flags; 42 int parent_index; 43 pcie_req_id_t fault_bdf; 44 uint32_t fault_addr; 45 int send_erpt; 46 47 /* 0-3Fh. PCI */ 48 uint16_t vendor_id; 49 uint16_t device_id; 50 uint8_t hdr_type; 51 uint16_t command; /* command */ 52 uint16_t status; /* status */ 53 uint8_t rev_id; 54 uint16_t s_status; /* Bridge secondary status */ 55 pcie_req_id_t bdg_secbus; /* Bridge secondary bus num */ 56 57 /* 40h-FFh. PCI-X Capability */ 58 uint16_t pcix_s_status; /* PCI-X Secondary status */ 59 uint32_t pcix_bdg_status; /* PCI-X Bridge status */ 60 61 /* 40h-FFh. PCI-E Capability */ 62 uint16_t pcie_off; /* PCI-E capability offset */ 63 uint8_t dev_type; /* device/port type */ 64 uint16_t dev_status; /* device status */ 65 66 /* 100h-FFFh. Extended PCI-E */ 67 uint16_t aer_off; /* AER offset */ 68 69 uint32_t aer_ce_status; /* AER Correctable Errors */ 70 71 uint32_t aer_ue_status; /* AER Uncorrectable Errors */ 72 uint32_t aer_severity; 73 uint32_t aer_control; 74 uint32_t aer_h0; 75 uint32_t aer_h1; 76 uint32_t aer_h2; 77 uint32_t aer_h3; 78 79 uint32_t s_aer_ue_status; /* Secondary AER UEs */ 80 uint32_t s_aer_control; 81 uint32_t s_aer_severity; 82 uint32_t s_aer_h0; 83 uint32_t s_aer_h1; 84 uint32_t s_aer_h2; 85 uint32_t s_aer_h3; 86 } pf_data_t; 87 88 /* Information used while handling errors in the fabric. */ 89 typedef struct pf_impl { 90 dev_info_t *pf_rpdip; 91 pcie_req_id_t pf_fbdf; /* captured fault bdf to scan */ 92 uint32_t pf_faddr; /* captured fault addr to scan */ 93 ddi_fm_error_t *pf_derr; 94 pf_data_t *pf_dq_p; /* ptr to pcie fault data queue */ 95 int *pf_dq_tail_p; /* last valid index of fault data q */ 96 } pf_impl_t; 97 98 /* Parent Private data of PCI/PCIe devices in a PCIe system */ 99 typedef struct pcie_ppd { 100 dev_info_t *ppd_dip; 101 ddi_acc_handle_t ppd_cfg_hdl; /* error handling acc handle */ 102 kmutex_t ppd_fm_lock; /* error handling lock */ 103 uint_t ppd_fm_flags; 104 105 /* Static PCI/PCIe information */ 106 pcie_req_id_t ppd_bdf; 107 uint32_t ppd_dev_ven_id; /* device/vendor ID */ 108 uint8_t ppd_hdr_type; /* pci header type, see pci.h */ 109 uint8_t ppd_dev_type; /* PCI-E dev type, see pcie.h */ 110 uint8_t ppd_bdg_secbus; /* Bridge secondary bus num */ 111 uint16_t ppd_pcie_off; /* PCIe Capability Offset */ 112 uint16_t ppd_aer_off; /* PCIe Advanced Error Offset */ 113 uint16_t ppd_pcix_off; /* PCIx Capability Offset */ 114 uint8_t ppd_pcie_phfun; /* Phantom funs for pcix/pcie */ 115 pci_bus_range_t ppd_bus_range; /* pci bus-range property */ 116 ppb_ranges_t *ppd_addr_ranges; /* pci range property */ 117 int ppd_addr_entries; /* number of range prop */ 118 pci_regspec_t *ppd_assigned_addr; /* "assigned-address" prop */ 119 int ppd_assigned_entries; /* number of prop entries */ 120 } pcie_ppd_t; 121 122 #define PCI_GET_BDF(dip) \ 123 ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_bdf 124 #define PCI_GET_SEC_BUS(dip) \ 125 ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_bdg_secbus 126 #define PCI_GET_PHFUN(dip) \ 127 ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_pcie_phfun 128 129 /* 130 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 131 * This flag will be used both by px and px_pci nexus drivers. 132 */ 133 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 134 135 /* ppd_fm_flags field */ 136 #define PF_FM_READY (1 << 0) /* ppd_fm_lock initialized */ 137 #define PF_IS_NH (1 << 1) /* known as non-hardened */ 138 139 /* PCIe fabric error handling return codes */ 140 #define PF_NO_ERROR (1 << 0) /* No error seen */ 141 #define PF_CE (1 << 1) /* Correctable Error */ 142 #define PF_NO_PANIC (1 << 2) /* Error should not panic sys */ 143 #define PF_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 144 #define PF_MATCHED_RC (1 << 4) /* Error Handled By RC */ 145 #define PF_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 146 #define PF_PANIC (1 << 6) /* Error should panic system */ 147 148 /* PCIe fabric handle lookup return codes */ 149 #define PF_HDL_FOUND 0 150 #define PF_HDL_NOTFOUND 1 151 152 /* PCIe fabric handle lookup address flags */ 153 #define PF_DMA_ADDR (1 << 0) 154 #define PF_PIO_ADDR (1 << 1) 155 #define PF_CFG_ADDR (1 << 2) 156 157 #define PF_SEND_ERPT_YES 1 158 #define PF_SEND_ERPT_UNKNOWN 0 159 #define PF_SEND_ERPT_NO -1 160 161 #define PF_SUCCESS (1 << 0) 162 #define PF_FAILURE (1 << 1) 163 #define PF_DO_NOT_SCAN (1 << 2) 164 165 /* PCIe helper functions */ 166 extern pcie_ppd_t *pcie_get_ppd(dev_info_t *dip); 167 168 /* PCIe Friendly Functions */ 169 extern int pcie_initchild(dev_info_t *dip); 170 extern void pcie_uninitchild(dev_info_t *dip); 171 extern void pcie_clear_errors(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 172 extern int pcie_postattach_child(dev_info_t *dip); 173 extern void pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 174 extern void pcie_disable_errors(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 175 extern int pcie_enable_ce(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 176 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 177 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 178 179 extern pcie_ppd_t *pcie_init_ppd(dev_info_t *cdip); 180 extern void pcie_uninit_ppd(dev_info_t *cdip); 181 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 182 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 183 184 /* PCIe error handling functions */ 185 extern int pf_en_dq(pf_data_t *pf_data_p, pf_data_t *dq_p, int *dq_tail_p, 186 pcie_req_id_t pbdf); 187 extern int pf_get_dq_size(void); 188 extern int pf_tlp_decode(dev_info_t *rpdip, pf_data_t *pf_data_p, 189 pcie_req_id_t *bdf, uint32_t *addr, uint32_t *trans_type); 190 extern int pf_tlp_hdl_lookup(dev_info_t *rpdip, ddi_fm_error_t *derr, 191 pf_data_t *pf_data_p); 192 extern int pf_hdl_lookup(dev_info_t *rpdip, uint64_t ena, 193 uint32_t flag, uint32_t addr, pcie_req_id_t bdf); 194 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 195 pf_data_t *dq_p, int *dq_tail_p); 196 extern void pf_init(dev_info_t *dip, ddi_iblock_cookie_t ibc); 197 extern void pf_fini(dev_info_t *dip); 198 extern boolean_t pf_ready(dev_info_t *dip); 199 200 201 #ifdef __cplusplus 202 } 203 #endif 204 205 #endif /* _SYS_PCIE_IMPL_H */ 206