1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIE_IMPL_H 27 #define _SYS_PCIE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/pcie.h> 34 35 #define PCI_GET_BDF(dip) \ 36 PCIE_DIP2BUS(dip)->bus_bdf 37 #define PCI_GET_SEC_BUS(dip) \ 38 PCIE_DIP2BUS(dip)->bus_bdg_secbus 39 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 40 PCIE_DIP2BUS(dip)->bus_bdg_secbus 41 42 #define DEVI_PORT_TYPE_PCI \ 43 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \ 44 PCI_BRIDGE_PCI_IF_PCI2PCI) 45 46 #define PCIE_DIP2BUS(dip) \ 47 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \ 48 PCIE_DIP2UPBUS(dip) : \ 49 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \ 50 PCIE_DIP2DOWNBUS(dip) : NULL) 51 52 #define PCIE_DIP2UPBUS(dip) \ 53 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE)) 54 #define PCIE_DIP2DOWNBUS(dip) \ 55 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE)) 56 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 57 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 58 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 59 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 60 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) 61 62 /* 63 * These macros depend on initialization of type related data in bus_p. 64 */ 65 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) 66 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) 67 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) 68 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) 69 /* IS_ROOT = is RC or RP */ 70 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) 71 72 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \ 73 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes) 74 75 #define PCIE_IS_HOTPLUG_ENABLED(dip) \ 76 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \ 77 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) 78 79 /* 80 * This is a pseudo pcie "device type", but it's needed to explain describe 81 * nodes such as PX and NPE, which aren't really PCI devices but do control or 82 * interaction with PCI error handling. 83 */ 84 #define PCIE_IS_RC(bus_p) \ 85 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO) 86 #define PCIE_IS_RP(bus_p) \ 87 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \ 88 PCIE_IS_PCIE(bus_p)) 89 #define PCIE_IS_SWU(bus_p) \ 90 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) 91 #define PCIE_IS_SWD(bus_p) \ 92 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) 93 #define PCIE_IS_SW(bus_p) \ 94 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p)) 95 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE) 96 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p)) 97 #define PCIE_IS_PCIE_BDG(bus_p) \ 98 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) 99 #define PCIE_IS_PCI2PCIE(bus_p) \ 100 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) 101 #define PCIE_IS_PCIE_SEC(bus_p) \ 102 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p)) 103 #define PCIX_ECC_VERSION_CHECK(bus_p) \ 104 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \ 105 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2)) 106 107 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff) 108 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff) 109 110 /* PCIE Cap/AER shortcuts */ 111 #define PCIE_GET(sz, bus_p, off) \ 112 pci_config_get ## sz(bus_p->bus_cfg_hdl, off) 113 #define PCIE_PUT(sz, bus_p, off, val) \ 114 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val) 115 #define PCIE_CAP_GET(sz, bus_p, off) \ 116 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off) 117 #define PCIE_CAP_PUT(sz, bus_p, off, val) \ 118 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off, \ 119 val) 120 #define PCIE_AER_GET(sz, bus_p, off) \ 121 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off) 122 #define PCIE_AER_PUT(sz, bus_p, off, val) \ 123 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off, \ 124 val) 125 #define PCIX_CAP_GET(sz, bus_p, off) \ 126 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off) 127 #define PCIX_CAP_PUT(sz, bus_p, off, val) \ 128 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off, \ 129 val) 130 131 /* Translate PF error return values to DDI_FM values */ 132 #define PF_ERR2DDIFM_ERR(sts) \ 133 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \ 134 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL)) 135 136 /* 137 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 138 * This flag will be used both by px and pcieb nexus drivers. 139 */ 140 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 141 142 /* 143 * PCI(e/-X) structures used to to gather and report errors detected by 144 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data. 145 * Static data such as Capability Offsets and Version #s is saved in the parent 146 * private data. 147 */ 148 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs 149 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs 150 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs 151 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs 152 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs 153 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n] 154 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs 155 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs 156 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault 157 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs 158 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n] 159 #define PCIE_ADV_BDG_REG(pfd_p) \ 160 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs 161 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n] 162 #define PCIE_ADV_RP_REG(pfd_p) \ 163 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs 164 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p)) 165 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p)) 166 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)) 167 168 /* bus_hp_mode field */ 169 typedef enum { 170 PCIE_NONE_HP_MODE = 0x0, 171 PCIE_ACPI_HP_MODE = 0x1, 172 PCIE_PCI_HP_MODE = 0x2, 173 PCIE_NATIVE_HP_MODE = 0x4 174 } pcie_hp_mode_t; 175 176 typedef struct pf_pci_bdg_err_regs { 177 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 178 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 179 } pf_pci_bdg_err_regs_t; 180 181 typedef struct pf_pci_err_regs { 182 uint16_t pci_err_status; /* pci status register */ 183 uint16_t pci_cfg_comm; /* pci command register */ 184 pf_pci_bdg_err_regs_t *pci_bdg_regs; 185 } pf_pci_err_regs_t; 186 187 typedef struct pf_pcix_ecc_regs { 188 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 189 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 190 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 191 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 192 } pf_pcix_ecc_regs_t; 193 194 typedef struct pf_pcix_err_regs { 195 uint16_t pcix_command; /* pcix command register */ 196 uint32_t pcix_status; /* pcix status register */ 197 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 198 } pf_pcix_err_regs_t; 199 200 typedef struct pf_pcix_bdg_err_regs { 201 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 202 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 203 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 204 } pf_pcix_bdg_err_regs_t; 205 206 typedef struct pf_pcie_adv_bdg_err_regs { 207 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 208 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 209 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 210 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 211 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 212 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */ 213 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */ 214 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 215 } pf_pcie_adv_bdg_err_regs_t; 216 217 typedef struct pf_pcie_adv_rp_err_regs { 218 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 219 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 220 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 221 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 222 } pf_pcie_adv_rp_err_regs_t; 223 224 typedef struct pf_pcie_adv_err_regs { 225 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 226 uint32_t pcie_ue_status; /* pcie ue error status reg */ 227 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 228 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 229 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 230 uint32_t pcie_ce_status; /* pcie ce error status reg */ 231 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 232 union { 233 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */ 234 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */ 235 } pcie_ext; 236 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 237 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 238 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */ 239 } pf_pcie_adv_err_regs_t; 240 241 typedef struct pf_pcie_rp_err_regs { 242 uint32_t pcie_rp_status; /* root complex status register */ 243 uint16_t pcie_rp_ctl; /* root complex control register */ 244 } pf_pcie_rp_err_regs_t; 245 246 typedef struct pf_pcie_err_regs { 247 uint16_t pcie_err_status; /* pcie device status register */ 248 uint16_t pcie_err_ctl; /* pcie error control register */ 249 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 250 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */ 251 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */ 252 } pf_pcie_err_regs_t; 253 254 typedef struct pf_root_fault { 255 pcie_req_id_t scan_bdf; /* BDF from error logs */ 256 uint64_t scan_addr; /* Addr from error logs */ 257 boolean_t full_scan; /* Option to do a full scan */ 258 } pf_root_fault_t; 259 260 typedef struct pf_data pf_data_t; 261 262 /* 263 * For hot plugged device, these data are init'ed during during probe 264 * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86), 265 * or in px_attach()(on sparc). 266 * 267 * For root complex the fields are initialized in pcie_rc_init_bus(); 268 * for others part of the fields are initialized in pcie_init_bus(), 269 * and part of fields initialized in pcie_post_init_bus(). See comments 270 * on top of respective functions for details. 271 */ 272 typedef struct pcie_bus { 273 /* Needed for PCI/PCIe fabric error handling */ 274 dev_info_t *bus_dip; 275 dev_info_t *bus_rp_dip; 276 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */ 277 uint_t bus_fm_flags; 278 uint_t bus_soft_state; 279 280 /* Static PCI/PCIe information */ 281 pcie_req_id_t bus_bdf; 282 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */ 283 uint32_t bus_dev_ven_id; /* device/vendor ID */ 284 uint8_t bus_rev_id; /* revision ID */ 285 uint8_t bus_hdr_type; /* pci header type, see pci.h */ 286 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */ 287 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */ 288 uint16_t bus_pcie_off; /* PCIe Capability Offset */ 289 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */ 290 uint16_t bus_pcix_off; /* PCIx Capability Offset */ 291 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */ 292 uint16_t bus_ecc_ver; /* PCIX ecc version */ 293 pci_bus_range_t bus_bus_range; /* pci bus-range property */ 294 ppb_ranges_t *bus_addr_ranges; /* pci range property */ 295 int bus_addr_entries; /* number of range prop */ 296 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */ 297 int bus_assigned_entries; /* number of prop entries */ 298 299 /* Cache of last fault data */ 300 pf_data_t *bus_pfd; 301 302 int bus_mps; /* Maximum Payload Size */ 303 304 void *bus_plat_private; /* Platform specific */ 305 /* Hotplug specific fields */ 306 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */ 307 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */ 308 void *bus_hp_ctrl; /* HP bus ctrl data */ 309 int bus_ari; /* ARI device */ 310 311 uint64_t bus_cfgacc_base; /* config space base address */ 312 } pcie_bus_t; 313 314 struct pf_data { 315 boolean_t pe_lock; 316 boolean_t pe_valid; 317 uint32_t pe_severity_flags; /* Severity of error */ 318 pcie_bus_t *pe_bus_p; 319 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */ 320 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */ 321 union { 322 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */ 323 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */ 324 } pe_ext; 325 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */ 326 pf_data_t *pe_prev; /* Next error in queue */ 327 pf_data_t *pe_next; /* Next error in queue */ 328 boolean_t pe_rber_fatal; 329 }; 330 331 /* Information used while handling errors in the fabric. */ 332 typedef struct pf_impl { 333 ddi_fm_error_t *pf_derr; 334 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */ 335 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */ 336 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */ 337 uint32_t pf_total; /* total non RC pf_datas */ 338 } pf_impl_t; 339 340 /* bus_fm_flags field */ 341 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */ 342 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */ 343 344 /* 345 * PCIe fabric handle lookup address flags. Used to define what type of 346 * transaction the address is for. These same value are defined again in 347 * fabric-xlate FM module. Do not modify these variables, without modifying 348 * those. 349 */ 350 #define PF_ADDR_DMA (1 << 0) 351 #define PF_ADDR_PIO (1 << 1) 352 #define PF_ADDR_CFG (1 << 2) 353 354 /* PCIe fabric error scanning status flags */ 355 #define PF_SCAN_SUCCESS (1 << 0) 356 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */ 357 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */ 358 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */ 359 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */ 360 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */ 361 362 /* PCIe fabric error handling severity return flags */ 363 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */ 364 #define PF_ERR_CE (1 << 1) /* Correctable Error */ 365 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */ 366 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 367 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */ 368 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 369 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */ 370 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */ 371 372 #define PF_ERR_FATAL_FLAGS (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK) 373 374 #define PF_HDL_FOUND 1 375 #define PF_HDL_NOTFOUND 2 376 377 /* 378 * PCIe Capability Device Type Pseudo Definitions. 379 * 380 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the 381 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO 382 * Space access is usually frowned upon now in PCIe, but there for legacy 383 * purposes. 384 */ 385 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100 386 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101 387 388 #define PCIE_INVALID_BDF 0xFFFF 389 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF) 390 391 typedef struct { 392 dev_info_t *dip; 393 int highest_common_mps; 394 } pcie_max_supported_t; 395 396 /* 397 * Default interrupt priority for all PCI and PCIe nexus drivers including 398 * hotplug interrupts. 399 */ 400 #define PCIE_INTR_PRI (LOCK_LEVEL - 1) 401 402 /* 403 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros 404 * for non-standard PCI or PCI Express Hotplug Controllers. 405 */ 406 #define PCIE_ENABLE_ERRORS(dip) \ 407 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 408 pcie_enable_errors(dip); \ 409 (void) pcie_enable_ce(dip); \ 410 } 411 412 #define PCIE_DISABLE_ERRORS(dip) \ 413 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 414 pcie_disable_errors(dip); \ 415 } 416 417 /* 418 * pcie_init_buspcie_fini_bus specific flags 419 */ 420 #define PCIE_BUS_INITIAL 0x0001 421 #define PCIE_BUS_FINAL 0x0002 422 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL) 423 424 #ifdef DEBUG 425 #define PCIE_DBG pcie_dbg 426 /* Common Debugging shortcuts */ 427 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \ 428 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 429 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 430 PCIE_GET(sz, bus_p, off)) 431 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \ 432 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 433 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 434 PCIE_CAP_GET(sz, bus_p, off)) 435 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \ 436 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 437 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 438 PCIE_AER_GET(sz, bus_p, off)) 439 440 #else /* DEBUG */ 441 442 #define PCIE_DBG_CFG 0 && 443 #define PCIE_DBG 0 && 444 #define PCIE_ARI_DBG 0 && 445 #define PCIE_DBG_CAP 0 && 446 #define PCIE_DBG_AER 0 && 447 448 #endif /* DEBUG */ 449 450 /* PCIe Friendly Functions */ 451 extern int pcie_init(dev_info_t *dip, caddr_t arg); 452 extern int pcie_uninit(dev_info_t *dip); 453 extern int pcie_intr(dev_info_t *dip); 454 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, 455 cred_t *credp); 456 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, 457 cred_t *credp); 458 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, 459 int mode, cred_t *credp, int *rvalp); 460 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 461 int flags, char *name, caddr_t valuep, int *lengthp); 462 463 extern void pcie_init_root_port_mps(dev_info_t *dip); 464 extern int pcie_initchild(dev_info_t *dip); 465 extern void pcie_uninitchild(dev_info_t *dip); 466 extern int pcie_init_cfghdl(dev_info_t *dip); 467 extern void pcie_fini_cfghdl(dev_info_t *dip); 468 extern void pcie_clear_errors(dev_info_t *dip); 469 extern int pcie_postattach_child(dev_info_t *dip); 470 extern void pcie_enable_errors(dev_info_t *dip); 471 extern void pcie_disable_errors(dev_info_t *dip); 472 extern int pcie_enable_ce(dev_info_t *dip); 473 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); 474 475 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, 476 uint8_t flags); 477 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags); 478 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags); 479 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags); 480 extern void pcie_rc_init_bus(dev_info_t *dip); 481 extern void pcie_rc_fini_bus(dev_info_t *dip); 482 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd); 483 extern void pcie_rc_fini_pfd(pf_data_t *pfd); 484 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 485 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 486 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 487 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 488 extern int pcie_dev(dev_info_t *dip); 489 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, 490 int *max_supported); 491 extern int pcie_root_port(dev_info_t *dip); 492 extern int pcie_initchild_mps(dev_info_t *dip); 493 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val); 494 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip); 495 496 extern uint32_t pcie_get_aer_uce_mask(); 497 extern uint32_t pcie_get_aer_ce_mask(); 498 extern uint32_t pcie_get_aer_suce_mask(); 499 extern uint32_t pcie_get_serr_mask(); 500 extern void pcie_set_aer_uce_mask(uint32_t mask); 501 extern void pcie_set_aer_ce_mask(uint32_t mask); 502 extern void pcie_set_aer_suce_mask(uint32_t mask); 503 extern void pcie_set_serr_mask(uint32_t mask); 504 extern void pcie_init_plat(dev_info_t *dip); 505 extern void pcie_fini_plat(dev_info_t *dip); 506 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **); 507 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function); 508 extern int pcie_ari_disable(dev_info_t *dip); 509 extern int pcie_ari_enable(dev_info_t *dip); 510 511 #define PCIE_ARI_FORW_NOT_SUPPORTED 0 512 #define PCIE_ARI_FORW_SUPPORTED 1 513 514 extern int pcie_ari_supported(dev_info_t *dip); 515 516 #define PCIE_ARI_FORW_DISABLED 0 517 #define PCIE_ARI_FORW_ENABLED 1 518 519 extern int pcie_ari_is_enabled(dev_info_t *dip); 520 521 #define PCIE_NOT_ARI_DEVICE 0 522 #define PCIE_ARI_DEVICE 1 523 524 extern int pcie_ari_device(dev_info_t *dip); 525 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func); 526 527 /* PCIe error handling functions */ 528 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 529 pf_data_t *root_pfd_p); 530 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t); 531 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t); 532 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t, 533 pcie_req_id_t); 534 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *); 535 extern void pcie_force_fullscan(); 536 537 #ifdef DEBUG 538 extern uint_t pcie_debug_flags; 539 extern void pcie_dbg(char *fmt, ...); 540 #endif /* DEBUG */ 541 542 #ifdef __cplusplus 543 } 544 #endif 545 546 #endif /* _SYS_PCIE_IMPL_H */ 547