1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_HW_H 27 #define _SYS_NXGE_NXGE_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \ 36 !defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) 37 #error Host endianness not defined 38 #endif 39 40 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \ 41 !defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH) 42 #error Bit ordering not defined 43 #endif 44 45 #include <nxge_fflp_hw.h> 46 #include <nxge_ipp_hw.h> 47 #include <nxge_mac_hw.h> 48 #include <nxge_rxdma_hw.h> 49 #include <nxge_txc_hw.h> 50 #include <nxge_txdma_hw.h> 51 #include <nxge_zcp_hw.h> 52 #include <nxge_espc_hw.h> 53 #include <nxge_n2_esr_hw.h> 54 #include <nxge_sr_hw.h> 55 #include <nxge_phy_hw.h> 56 57 58 /* Modes of NXGE core */ 59 typedef enum nxge_mode_e { 60 NXGE_MODE_NE = 1, 61 NXGE_MODE_N2 = 2 62 } nxge_mode_t; 63 64 /* 65 * Function control Register 66 * (bit 31 is reset to 0. Read back 0 then free to use it. 67 * (once done with it, bit 0:15 can be used to store SW status) 68 */ 69 #define DEV_FUNC_SR_REG (PIO + 0x10000) 70 #define DEV_FUNC_SR_SR_SHIFT 0 71 #define DEV_FUNC_SR_SR_MASK 0x000000000000FFFFULL 72 #define DEV_FUNC_SR_FUNCID_SHIFT 16 73 #define DEV_FUNC_SR_FUNCID_MASK 0x0000000000030000ULL 74 #define DEV_FUNC_SR_TAS_SHIFT 31 75 #define DEV_FUNC_SR_TAS_MASK 0x0000000080000000ULL 76 77 typedef union _dev_func_sr_t { 78 uint64_t value; 79 struct { 80 #if defined(_BIG_ENDIAN) 81 uint32_t hdw; 82 #endif 83 struct { 84 #if defined(_BIT_FIELDS_HTOL) 85 uint32_t tas:1; 86 uint32_t res2:13; 87 uint32_t funcid:2; 88 uint32_t sr:16; 89 #elif defined(_BIT_FIELDS_LTOH) 90 uint32_t sr:16; 91 uint32_t funcid:2; 92 uint32_t res2:13; 93 uint32_t tas:1; 94 #endif 95 } ldw; 96 #if !defined(_BIG_ENDIAN) 97 uint32_t hdw; 98 #endif 99 } bits; 100 } dev_func_sr_t, *p_dev_func_sr_t; 101 102 103 /* 104 * Multi Parition Control Register (partitiion manager) 105 */ 106 #define MULTI_PART_CTL_REG (FZC_PIO + 0x00000) 107 #define MULTI_PART_CTL_MPC 0x0000000000000001ULL 108 109 typedef union _multi_part_ctl_t { 110 uint64_t value; 111 struct { 112 #if defined(_BIG_ENDIAN) 113 uint32_t hdw; 114 #endif 115 struct { 116 #if defined(_BIT_FIELDS_HTOL) 117 uint32_t res1:31; 118 uint32_t mpc:1; 119 #elif defined(_BIT_FIELDS_LTOH) 120 uint32_t mpc:1; 121 uint32_t res1:31; 122 #endif 123 } ldw; 124 #if !defined(_BIG_ENDIAN) 125 uint32_t hdw; 126 #endif 127 } bits; 128 } multi_part_ctl_t, *p_multi_part_ctl_t; 129 130 /* 131 * Virtual DMA CSR Address (partition manager) 132 */ 133 #define VADDR_REG (PIO_VADDR + 0x00000) 134 135 /* 136 * DMA Channel Binding Register (partition manager) 137 */ 138 #define DMA_BIND_REG (FZC_PIO + 0x10000) 139 #define DMA_BIND_RX_SHIFT 0 140 #define DMA_BIND_RX_MASK 0x000000000000001FULL 141 #define DMA_BIND_RX_BIND_SHIFT 5 142 #define DMA_BIND_RX_BIND_SET 0x0000000000000020ULL 143 #define DMA_BIND_RX_BIND_MASK 0x0000000000000020ULL 144 #define DMA_BIND_TX_SHIFT 8 145 #define DMA_BIND_TX_MASK 0x0000000000001f00ULL 146 #define DMA_BIND_TX_BIND_SHIFT 13 147 #define DMA_BIND_TX_BIND_SET 0x0000000000002000ULL 148 #define DMA_BIND_TX_BIND_MASK 0x0000000000002000ULL 149 150 typedef union _dma_bind_t { 151 uint64_t value; 152 struct { 153 #if defined(_BIG_ENDIAN) 154 uint32_t hdw; 155 #endif 156 struct { 157 #if defined(_BIT_FIELDS_HTOL) 158 uint32_t res1_1:16; 159 uint32_t tx_bind:1; 160 uint32_t tx:5; 161 uint32_t res2:2; 162 uint32_t rx_bind:1; 163 uint32_t rx:5; 164 #elif defined(_BIT_FIELDS_LTOH) 165 uint32_t rx:5; 166 uint32_t rx_bind:1; 167 uint32_t res2:2; 168 uint32_t tx:5; 169 uint32_t tx_bind:1; 170 uint32_t res1_1:16; 171 #endif 172 } ldw; 173 #if !defined(_BIG_ENDIAN) 174 uint32_t hdw; 175 #endif 176 } bits; 177 } dma_bind_t, *p_dma_bind_t; 178 179 /* 180 * System interrupts: 181 * Logical device and group definitions. 182 */ 183 #define NXGE_INT_MAX_LDS 69 184 #define NXGE_INT_MAX_LDGS 64 185 #define NXGE_LDGRP_PER_NIU_PORT (NXGE_INT_MAX_LDGS/2) 186 #define NXGE_LDGRP_PER_NEP_PORT (NXGE_INT_MAX_LDGS/4) 187 #define NXGE_LDGRP_PER_2PORTS (NXGE_INT_MAX_LDGS/2) 188 #define NXGE_LDGRP_PER_4PORTS (NXGE_INT_MAX_LDGS/4) 189 190 #define NXGE_RDMA_LD_START 0 191 #define NXGE_TDMA_LD_START 32 192 #define NXGE_MIF_LD 63 193 #define NXGE_MAC_LD_START 64 194 #define NXGE_MAC_LD_PORT0 64 195 #define NXGE_MAC_LD_PORT1 65 196 #define NXGE_MAC_LD_PORT2 66 197 #define NXGE_MAC_LD_PORT3 67 198 #define NXGE_SYS_ERROR_LD 68 199 200 /* 201 * Logical Device Group Number 202 */ 203 #define LDG_NUM_REG (FZC_PIO + 0x20000) 204 #define LDG_NUM_NUM_SHIFT 0 205 #define LDG_NUM_NUM_MASK 0x000000000000001FULL 206 207 typedef union _ldg_num_t { 208 uint64_t value; 209 struct { 210 #if defined(_BIG_ENDIAN) 211 uint32_t hdw; 212 #endif 213 struct { 214 #if defined(_BIT_FIELDS_HTOL) 215 uint32_t res1_1:26; 216 uint32_t num:6; 217 #elif defined(_BIT_FIELDS_LTOH) 218 uint32_t num:6; 219 uint32_t res1_1:26; 220 #endif 221 } ldw; 222 #if !defined(_BIG_ENDIAN) 223 uint32_t hdw; 224 #endif 225 } bits; 226 } ldg_num_t, *p_ldg_num_t; 227 228 /* 229 * Logical Device State Vector 230 */ 231 #define LDSV0_REG (PIO_LDSV + 0x00000) 232 #define LDSV0_LDF_SHIFT 0 233 #define LDSV0_LDF_MASK 0x00000000000003FFULL 234 #define LDG_NUM_NUM_MASK 0x000000000000001FULL 235 #define LDSV_MASK_ALL 0x0000000000000001ULL 236 237 /* 238 * Logical Device State Vector 1 239 */ 240 #define LDSV1_REG (PIO_LDSV + 0x00008) 241 242 /* 243 * Logical Device State Vector 2 244 */ 245 #define LDSV2_REG (PIO_LDSV + 0x00010) 246 247 /* For Logical Device State Vector 0 and 1 */ 248 typedef union _ldsv_t { 249 uint64_t value; 250 struct { 251 #if defined(_BIG_ENDIAN) 252 uint32_t hdw; 253 #endif 254 uint32_t ldw; 255 #if !defined(_BIG_ENDIAN) 256 uint32_t hdw; 257 #endif 258 } bits; 259 } ldsv_t, *p_ldsv_t; 260 261 #define LDSV2_LDF0_SHIFT 0 262 #define LDSV2_LDF0_MASK 0x000000000000001FULL 263 #define LDSV2_LDF1_SHIFT 5 264 #define LDSV2_LDF1_MASK 0x00000000000001E0ULL 265 266 typedef union _ldsv2_t { 267 uint64_t value; 268 struct { 269 #if defined(_BIG_ENDIAN) 270 uint32_t hdw; 271 #endif 272 struct { 273 #if defined(_BIT_FIELDS_HTOL) 274 uint32_t res1_1:22; 275 uint32_t ldf1:5; 276 uint32_t ldf0:5; 277 #elif defined(_BIT_FIELDS_LTOH) 278 uint32_t ldf0:5; 279 uint32_t ldf1:5; 280 uint32_t res1_1:22; 281 #endif 282 } ldw; 283 #if !defined(_BIG_ENDIAN) 284 uint32_t hdw; 285 #endif 286 } bits; 287 } ldsv2_t, *p_ldsv2_t; 288 289 /* 290 * Logical Device Interrupt Mask 0 291 */ 292 #define LD_IM0_REG (PIO_IMASK0 + 0x00000) 293 #define LD_IM0_SHIFT 0 294 #define LD_IM0_MASK 0x0000000000000003ULL 295 #define LD_IM_MASK 0x0000000000000003ULL 296 297 /* 298 * Logical Device Interrupt Mask 1 299 */ 300 #define LD_IM1_REG (PIO_IMASK1 + 0x00000) 301 #define LD_IM1_SHIFT 0 302 #define LD_IM1_MASK 0x0000000000000003ULL 303 304 /* For Lofical Device Interrupt Mask 0 and 1 */ 305 typedef union _ld_im_t { 306 uint64_t value; 307 struct { 308 #if defined(_BIG_ENDIAN) 309 uint32_t hdw; 310 #endif 311 struct { 312 313 #if defined(_BIT_FIELDS_HTOL) 314 uint32_t res1_1:30; 315 uint32_t ldf_mask:2; 316 #elif defined(_BIT_FIELDS_LTOH) 317 uint32_t ldf_mask:2; 318 uint32_t res1_1:30; 319 #endif 320 } ldw; 321 #if !defined(_BIG_ENDIAN) 322 uint32_t hdw; 323 #endif 324 } bits; 325 } ld_im_t, *p_ld_im_t; 326 327 /* 328 * Logical Device Group Interrupt Management 329 */ 330 #define LDGIMGN_REG (PIO_LDSV + 0x00018) 331 #define LDGIMGN_TIMER_SHIFT 0 332 #define LDGIMGM_TIMER_MASK 0x000000000000003FULL 333 #define LDGIMGN_ARM_SHIFT 31 334 #define LDGIMGM_ARM 0x0000000080000000ULL 335 #define LDGIMGM_ARM_MASK 0x0000000080000000ULL 336 337 typedef union _ldgimgm_t { 338 uint64_t value; 339 struct { 340 #if defined(_BIG_ENDIAN) 341 uint32_t hdw; 342 #endif 343 struct { 344 #if defined(_BIT_FIELDS_HTOL) 345 uint32_t arm:1; 346 uint32_t res2:25; 347 uint32_t timer:6; 348 #elif defined(_BIT_FIELDS_LTOH) 349 uint32_t timer:6; 350 uint32_t res2:25; 351 uint32_t arm:1; 352 #endif 353 } ldw; 354 #if !defined(_BIG_ENDIAN) 355 uint32_t hdw; 356 #endif 357 } bits; 358 } ldgimgm_t, *p_ldgimgm_t; 359 360 /* 361 * Logical Device Group Interrupt Timer Resolution 362 */ 363 #define LDGITMRES_REG (FZC_PIO + 0x00008) 364 #define LDGTITMRES_RES_SHIFT 0 /* bits 19:0 */ 365 #define LDGTITMRES_RES_MASK 0x00000000000FFFFFULL 366 typedef union _ldgitmres_t { 367 uint64_t value; 368 struct { 369 #if defined(_BIG_ENDIAN) 370 uint32_t hdw; 371 #endif 372 struct { 373 #if defined(_BIT_FIELDS_HTOL) 374 uint32_t res1_1:12; 375 uint32_t res:20; 376 #elif defined(_BIT_FIELDS_LTOH) 377 uint32_t res:20; 378 uint32_t res1_1:12; 379 #endif 380 } ldw; 381 #if !defined(_BIG_ENDIAN) 382 uint32_t hdw; 383 #endif 384 } bits; 385 } ldgitmres_t, *p_ldgitmres_t; 386 387 /* 388 * System Interrupt Data 389 */ 390 #define SID_REG (FZC_PIO + 0x10200) 391 #define SID_DATA_SHIFT 0 /* bits 6:0 */ 392 #define SID_DATA_MASK 0x000000000000007FULL 393 #define SID_DATA_INTNUM_SHIFT 0 /* bits 4:0 */ 394 #define SID_DATA_INTNUM_MASK 0x000000000000001FULL 395 #define SID_DATA_FUNCNUM_SHIFT 5 /* bits 6:5 */ 396 #define SID_DATA_FUNCNUM_MASK 0x0000000000000060ULL 397 #define SID_PCI_FUNCTION_SHIFT (1 << 5) 398 #define SID_N2_INDEX (1 << 6) 399 400 #define SID_DATA(f, v) ((f << SID_DATA_FUNCNUM_SHIFT) | \ 401 ((v << SID_DATA_SHIFT) & SID_DATA_INTNUM_MASK)) 402 403 #define SID_DATA_N2(v) (v | SID_N2_INDEX) 404 405 typedef union _sid_t { 406 uint64_t value; 407 struct { 408 #if defined(_BIG_ENDIAN) 409 uint32_t hdw; 410 #endif 411 struct { 412 #if defined(_BIT_FIELDS_HTOL) 413 uint32_t res1_1:25; 414 uint32_t data:7; 415 #elif defined(_BIT_FIELDS_LTOH) 416 uint32_t data:7; 417 uint32_t res1_1:25; 418 #endif 419 } ldw; 420 #if !defined(_BIG_ENDIAN) 421 uint32_t hdw; 422 #endif 423 } bits; 424 } sid_t, *p_sid_t; 425 426 /* 427 * Reset Control 428 */ 429 #define RST_CTL_REG (FZC_PIO + 0x00038) 430 #define RST_CTL_MAC_RST3 0x0000000000400000ULL 431 #define RST_CTL_MAC_RST3_SHIFT 22 432 #define RST_CTL_MAC_RST2 0x0000000000200000ULL 433 #define RST_CTL_MAC_RST2_SHIFT 21 434 #define RST_CTL_MAC_RST1 0x0000000000100000ULL 435 #define RST_CTL_MAC_RST1_SHIFT 20 436 #define RST_CTL_MAC_RST0 0x0000000000080000ULL 437 #define RST_CTL_MAC_RST0_SHIFT 19 438 #define RST_CTL_EN_ACK_TO 0x0000000000000800ULL 439 #define RST_CTL_EN_ACK_TO_SHIFT 11 440 #define RST_CTL_ACK_TO_MASK 0x00000000000007FEULL 441 #define RST_CTL_ACK_TO_SHIFT 1 442 443 444 typedef union _rst_ctl_t { 445 uint64_t value; 446 struct { 447 #if defined(_BIG_ENDIAN) 448 uint32_t hdw; 449 #endif 450 struct { 451 #if defined(_BIT_FIELDS_HTOL) 452 uint32_t res1:9; 453 uint32_t mac_rst3:1; 454 uint32_t mac_rst2:1; 455 uint32_t mac_rst1:1; 456 uint32_t mac_rst0:1; 457 uint32_t res2:7; 458 uint32_t ack_to_en:1; 459 uint32_t ack_to_val:10; 460 uint32_t res3:1; 461 #elif defined(_BIT_FIELDS_LTOH) 462 uint32_t res3:1; 463 uint32_t ack_to_val:10; 464 uint32_t ack_to_en:1; 465 uint32_t res2:7; 466 uint32_t mac_rst0:1; 467 uint32_t mac_rst1:1; 468 uint32_t mac_rst2:1; 469 uint32_t mac_rst3:1; 470 uint32_t res1:9; 471 #endif 472 } ldw; 473 #if !defined(_BIG_ENDIAN) 474 uint32_t hdw; 475 #endif 476 } bits; 477 } rst_ctl_t, *p_rst_ctl_t; 478 479 /* 480 * System Error Mask 481 */ 482 #define SYS_ERR_MASK_REG (FZC_PIO + 0x00090) 483 484 /* 485 * System Error Status 486 */ 487 #define SYS_ERR_STAT_REG (FZC_PIO + 0x00098) 488 489 490 #define SYS_ERR_META2_MASK 0x0000000000000400ULL 491 #define SYS_ERR_META2_SHIFT 10 492 #define SYS_ERR_META1_MASK 0x0000000000000200ULL 493 #define SYS_ERR_META1_SHIFT 9 494 #define SYS_ERR_PEU_MASK 0x0000000000000100ULL 495 #define SYS_ERR_PEU_SHIFT 8 496 #define SYS_ERR_TXC_MASK 0x0000000000000080ULL 497 #define SYS_ERR_TXC_SHIFT 7 498 #define SYS_ERR_RDMC_MASK 0x0000000000000040ULL 499 #define SYS_ERR_RDMC_SHIFT 6 500 #define SYS_ERR_TDMC_MASK 0x0000000000000020ULL 501 #define SYS_ERR_TDMC_SHIFT 5 502 #define SYS_ERR_ZCP_MASK 0x0000000000000010ULL 503 #define SYS_ERR_ZCP_SHIFT 4 504 #define SYS_ERR_FFLP_MASK 0x0000000000000008ULL 505 #define SYS_ERR_FFLP_SHIFT 3 506 #define SYS_ERR_IPP_MASK 0x0000000000000004ULL 507 #define SYS_ERR_IPP_SHIFT 2 508 #define SYS_ERR_MAC_MASK 0x0000000000000002ULL 509 #define SYS_ERR_MAC_SHIFT 1 510 #define SYS_ERR_SMX_MASK 0x0000000000000001ULL 511 #define SYS_ERR_SMX_SHIFT 0 512 #define SYS_ERR_MASK_ALL (SYS_ERR_SMX_MASK | SYS_ERR_MAC_MASK | \ 513 SYS_ERR_IPP_MASK | SYS_ERR_FFLP_MASK | \ 514 SYS_ERR_ZCP_MASK | SYS_ERR_TDMC_MASK | \ 515 SYS_ERR_RDMC_MASK | SYS_ERR_TXC_MASK | \ 516 SYS_ERR_PEU_MASK | SYS_ERR_META1_MASK | \ 517 SYS_ERR_META2_MASK) 518 519 520 typedef union _sys_err_mask_t { 521 uint64_t value; 522 struct { 523 #if defined(_BIG_ENDIAN) 524 uint32_t hdw; 525 #endif 526 struct { 527 #if defined(_BIT_FIELDS_HTOL) 528 uint32_t res:21; 529 uint32_t meta2:1; 530 uint32_t meta1:1; 531 uint32_t peu:1; 532 uint32_t txc:1; 533 uint32_t rdmc:1; 534 uint32_t tdmc:1; 535 uint32_t zcp:1; 536 uint32_t fflp:1; 537 uint32_t ipp:1; 538 uint32_t mac:1; 539 uint32_t smx:1; 540 #elif defined(_BIT_FIELDS_LTOH) 541 uint32_t smx:1; 542 uint32_t mac:1; 543 uint32_t ipp:1; 544 uint32_t fflp:1; 545 uint32_t zcp:1; 546 uint32_t tdmc:1; 547 uint32_t rdmc:1; 548 uint32_t txc:1; 549 uint32_t peu:1; 550 uint32_t meta1:1; 551 uint32_t meta2:1; 552 uint32_t res:21; 553 #endif 554 } ldw; 555 #if !defined(_BIG_ENDIAN) 556 uint32_t hdw; 557 #endif 558 } bits; 559 } sys_err_mask_t, sys_err_stat_t, *p_sys_err_mask_t, *p_sys_err_stat_t; 560 561 562 /* 563 * Meta Arbiter Dirty Transaction ID Control 564 */ 565 566 #define DIRTY_TID_CTL_REG (FZC_PIO + 0x0010) 567 #define DIRTY_TID_CTL_WR_THRES_MASK 0x00000000003F0000ULL 568 #define DIRTY_TID_CTL_WR_THRES_SHIFT 16 569 #define DIRTY_TID_CTL_RD_THRES_MASK 0x00000000000003F0ULL 570 #define DIRTY_TID_CTL_RD_THRES_SHIFT 4 571 #define DIRTY_TID_CTL_DTID_CLR 0x0000000000000002ULL 572 #define DIRTY_TID_CTL_DTID_CLR_SHIFT 1 573 #define DIRTY_TID_CTL_DTID_EN 0x0000000000000001ULL 574 #define DIRTY_TID_CTL_DTID_EN_SHIFT 0 575 576 typedef union _dty_tid_ctl_t { 577 uint64_t value; 578 struct { 579 #if defined(_BIG_ENDIAN) 580 uint32_t hdw; 581 #endif 582 struct { 583 #if defined(_BIT_FIELDS_HTOL) 584 uint32_t res1:10; 585 uint32_t np_wr_thres_val:6; 586 uint32_t res2:6; 587 uint32_t np_rd_thres_val:6; 588 uint32_t res3:2; 589 uint32_t dty_tid_clr:1; 590 uint32_t dty_tid_en:1; 591 #elif defined(_BIT_FIELDS_LTOH) 592 uint32_t dty_tid_en:1; 593 uint32_t dty_tid_clr:1; 594 uint32_t res3:2; 595 uint32_t np_rd_thres_val:6; 596 uint32_t res2:6; 597 uint32_t np_wr_thres_val:6; 598 uint32_t res1:10; 599 #endif 600 } ldw; 601 #if !defined(_BIG_ENDIAN) 602 uint32_t hdw; 603 #endif 604 } bits; 605 } dty_tid_ctl_t, *p_dty_tid_ctl_t; 606 607 608 /* 609 * Meta Arbiter Dirty Transaction ID Status 610 */ 611 #define DIRTY_TID_STAT_REG (FZC_PIO + 0x0018) 612 #define DIRTY_TID_STAT_WR_TID_DTY_CNT_MASK 0x0000000000003F00ULL 613 #define DIRTY_TID_STAT_WR_TID_DTY_CNT_SHIFT 8 614 #define DIRTY_TID_STAT_RD_TID_DTY_CNT_MASK 0x000000000000003FULL 615 #define DIRTY_TID_STAT_RD_TID_DTY_CNT_SHIFT 0 616 617 typedef union _dty_tid_stat_t { 618 uint64_t value; 619 struct { 620 #if defined(_BIG_ENDIAN) 621 uint32_t hdw; 622 #endif 623 struct { 624 #if defined(_BIT_FIELDS_HTOL) 625 uint32_t res1:18; 626 uint32_t wr_tid_dirty_cnt:6; 627 uint32_t res2:2; 628 uint32_t rd_tid_dirty_cnt:6; 629 #elif defined(_BIT_FIELDS_LTOH) 630 uint32_t rd_tid_dirty_cnt:6; 631 uint32_t res2:2; 632 uint32_t wr_tid_dirty_cnt:6; 633 uint32_t res1:18; 634 #endif 635 } ldw; 636 #if !defined(_BIG_ENDIAN) 637 uint32_t hdw; 638 #endif 639 } bits; 640 } dty_tid_stat_t, *p_dty_tid_stat_t; 641 642 643 /* 644 * SMX Registers 645 */ 646 #define SMX_CFIG_DAT_REG (FZC_PIO + 0x00040) 647 #define SMX_CFIG_DAT_RAS_DET_EN_MASK 0x0000000080000000ULL 648 #define SMX_CFIG_DAT_RAS_DET_EN_SHIFT 31 649 #define SMX_CFIG_DAT_RAS_INJ_EN_MASK 0x0000000040000000ULL 650 #define SMX_CFIG_DAT_RAS_INJ_EN_SHIFT 30 651 #define SMX_CFIG_DAT_TRANS_TO_MASK 0x000000000FFFFFFFULL 652 #define SMX_CFIG_DAT_TRANS_TO_SHIFT 0 653 654 typedef union _smx_cfg_dat_t { 655 uint64_t value; 656 struct { 657 #if defined(_BIG_ENDIAN) 658 uint32_t hdw; 659 #endif 660 struct { 661 #if defined(_BIT_FIELDS_HTOL) 662 uint32_t res_err_det:1; 663 uint32_t ras_err_inj_en:1; 664 uint32_t res:2; 665 uint32_t trans_to_val:28; 666 #elif defined(_BIT_FIELDS_LTOH) 667 uint32_t trans_to_val:28; 668 uint32_t res:2; 669 uint32_t ras_err_inj_en:1; 670 uint32_t res_err_det:1; 671 #endif 672 } ldw; 673 #if !defined(_BIG_ENDIAN) 674 uint32_t hdw; 675 #endif 676 } bits; 677 } smx_cfg_dat_t, *p_smx_cfg_dat_t; 678 679 680 #define SMX_INT_STAT_REG (FZC_PIO + 0x00048) 681 #define SMX_INT_STAT_SM_MASK 0x00000000FFFFFFC0ULL 682 #define SMX_INT_STAT_SM_SHIFT 6 683 684 typedef union _smx_int_stat_t { 685 uint64_t value; 686 struct { 687 #if defined(_BIG_ENDIAN) 688 uint32_t hdw; 689 #endif 690 struct { 691 #if defined(_BIT_FIELDS_HTOL) 692 uint32_t st_mc_stat:26; 693 uint32_t res:6; 694 #elif defined(_BIT_FIELDS_LTOH) 695 uint32_t res:6; 696 uint32_t st_mc_stat:26; 697 #endif 698 } ldw; 699 #if !defined(_BIG_ENDIAN) 700 uint32_t hdw; 701 #endif 702 } bits; 703 } smx_int_stat_t, *p_smx_int_stat_t; 704 705 706 #define SMX_CTL_REG (FZC_PIO + 0x00050) 707 708 typedef union _smx_ctl_t { 709 uint64_t value; 710 struct { 711 #if defined(_BIG_ENDIAN) 712 uint32_t hdw; 713 #endif 714 struct { 715 #if defined(_BIT_FIELDS_HTOL) 716 uint32_t res1:21; 717 uint32_t resp_err_inj:3; 718 uint32_t res2:1; 719 uint32_t xtb_err_inj:3; 720 uint32_t res3:1; 721 uint32_t dbg_sel:3; 722 #elif defined(_BIT_FIELDS_LTOH) 723 uint32_t dbg_sel:3; 724 uint32_t res3:1; 725 uint32_t xtb_err_inj:3; 726 uint32_t res2:1; 727 uint32_t resp_err_inj:3; 728 uint32_t res1:21; 729 #endif 730 } ldw; 731 #if !defined(_BIG_ENDIAN) 732 uint32_t hdw; 733 #endif 734 } bits; 735 } smx_ctl_t, *p_smx_ctl_t; 736 737 738 #define SMX_DBG_VEC_REG (FZC_PIO + 0x00058) 739 740 typedef union _smx_dbg_vec_t { 741 uint64_t value; 742 struct { 743 #if defined(_BIG_ENDIAN) 744 uint32_t hdw; 745 #endif 746 struct { 747 uint32_t dbg_tng_vec; 748 } ldw; 749 #if !defined(_BIG_ENDIAN) 750 uint32_t hdw; 751 #endif 752 } bits; 753 } smx_dbg_vec_t, *p_smx_dbg_vec_t; 754 755 756 /* 757 * Debug registers 758 */ 759 760 #define PIO_DBG_SEL_REG (FZC_PIO + 0x00060) 761 762 typedef union _pio_dbg_sel_t { 763 uint64_t value; 764 struct { 765 #if defined(_BIG_ENDIAN) 766 uint32_t hdw; 767 #endif 768 struct { 769 uint32_t sel; 770 } ldw; 771 #if !defined(_BIG_ENDIAN) 772 uint32_t hdw; 773 #endif 774 } bits; 775 } pio_dbg_sel_t, *p_pio_dbg_sel_t; 776 777 778 #define PIO_TRAIN_VEC_REG (FZC_PIO + 0x00068) 779 780 typedef union _pio_tng_vec_t { 781 uint64_t value; 782 struct { 783 #if defined(_BIG_ENDIAN) 784 uint32_t hdw; 785 #endif 786 struct { 787 uint32_t training_vec; 788 } ldw; 789 #if !defined(_BIG_ENDIAN) 790 uint32_t hdw; 791 #endif 792 } bits; 793 } pio_tng_vec_t, *p_pio_tng_vec_t; 794 795 #define PIO_ARB_CTL_REG (FZC_PIO + 0x00070) 796 797 typedef union _pio_arb_ctl_t { 798 uint64_t value; 799 struct { 800 #if defined(_BIG_ENDIAN) 801 uint32_t hdw; 802 #endif 803 struct { 804 uint32_t ctl; 805 } ldw; 806 #if !defined(_BIG_ENDIAN) 807 uint32_t hdw; 808 #endif 809 } bits; 810 } pio_arb_ctl_t, *p_pio_arb_ctl_t; 811 812 #define PIO_ARB_DBG_VEC_REG (FZC_PIO + 0x00078) 813 814 typedef union _pio_arb_dbg_vec_t { 815 uint64_t value; 816 struct { 817 #if defined(_BIG_ENDIAN) 818 uint32_t hdw; 819 #endif 820 struct { 821 uint32_t dbg_vector; 822 } ldw; 823 #if !defined(_BIG_ENDIAN) 824 uint32_t hdw; 825 #endif 826 } bits; 827 } pio_arb_dbg_vec_t, *p_pio_arb_dbg_vec_t; 828 829 830 /* 831 * GPIO Registers 832 */ 833 834 #define GPIO_EN_REG (FZC_PIO + 0x00028) 835 #define GPIO_EN_ENABLE_MASK 0x000000000000FFFFULL 836 #define GPIO_EN_ENABLE_SHIFT 0 837 typedef union _gpio_en_t { 838 uint64_t value; 839 struct { 840 #if defined(_BIG_ENDIAN) 841 uint32_t hdw; 842 #endif 843 struct { 844 #if defined(_BIT_FIELDS_HTOL) 845 uint32_t res:16; 846 uint32_t enable:16; 847 #elif defined(_BIT_FIELDS_LTOH) 848 uint32_t enable:16; 849 uint32_t res:16; 850 #endif 851 } ldw; 852 #if !defined(_BIG_ENDIAN) 853 uint32_t hdw; 854 #endif 855 } bits; 856 } gpio_en_t, *p_gpio_en_t; 857 858 #define GPIO_DATA_IN_REG (FZC_PIO + 0x00030) 859 #define GPIO_DATA_IN_MASK 0x000000000000FFFFULL 860 #define GPIO_DATA_IN_SHIFT 0 861 typedef union _gpio_data_in_t { 862 uint64_t value; 863 struct { 864 #if defined(_BIG_ENDIAN) 865 uint32_t hdw; 866 #endif 867 struct { 868 #if defined(_BIT_FIELDS_HTOL) 869 uint32_t res:16; 870 uint32_t data_in:16; 871 #elif defined(_BIT_FIELDS_LTOH) 872 uint32_t data_in:16; 873 uint32_t res:16; 874 #endif 875 } ldw; 876 #if !defined(_BIG_ENDIAN) 877 uint32_t hdw; 878 #endif 879 } bits; 880 } gpio_data_in_t, *p_gpio_data_in_t; 881 882 883 /* 884 * PCI Express Interface Module (PIM) registers 885 */ 886 #define PIM_CONTROL_REG (FZC_PIM + 0x0) 887 #define PIM_CONTROL_DBG_SEL_MASK 0x000000000000000FULL 888 #define PIM_CONTROL_DBG_SEL_SHIFT 0 889 typedef union _pim_ctl_t { 890 uint64_t value; 891 struct { 892 #if defined(_BIG_ENDIAN) 893 uint32_t hdw; 894 #endif 895 struct { 896 #if defined(_BIT_FIELDS_HTOL) 897 uint32_t res:28; 898 uint32_t dbg_sel:4; 899 #elif defined(_BIT_FIELDS_LTOH) 900 uint32_t dbg_sel:4; 901 uint32_t res:28; 902 #endif 903 } ldw; 904 #if !defined(_BIG_ENDIAN) 905 uint32_t hdw; 906 #endif 907 } bits; 908 } pim_ctl_t, *p_pim_ctl_t; 909 910 #define PIM_DBG_TRAINING_VEC_REG (FZC_PIM + 0x00008) 911 #define PIM_DBG_TRAINING_VEC_MASK 0x00000000FFFFFFFFULL 912 913 #define PIM_INTR_STATUS_REG (FZC_PIM + 0x00010) 914 #define PIM_INTR_STATUS_MASK 0x00000000FFFFFFFFULL 915 916 #define PIM_INTERNAL_STATUS_REG (FZC_PIM + 0x00018) 917 #define PIM_INTERNAL_STATUS_MASK 0x00000000FFFFFFFFULL 918 919 #define PIM_INTR_MASK_REG (FZC_PIM + 0x00020) 920 #define PIM_INTR_MASK_MASK 0x00000000FFFFFFFFULL 921 922 /* 923 * Partitioning Logical pages Definition registers. 924 * (used by both receive and transmit DMA channels) 925 */ 926 927 /* Logical page definitions */ 928 typedef union _log_page_vld_t { 929 uint64_t value; 930 struct { 931 #if defined(_BIG_ENDIAN) 932 uint32_t hdw; 933 #endif 934 struct { 935 #if defined(_BIT_FIELDS_HTOL) 936 uint32_t res1_1:28; 937 uint32_t func:2; 938 uint32_t page1:1; 939 uint32_t page0:1; 940 #elif defined(_BIT_FIELDS_LTOH) 941 uint32_t page0:1; 942 uint32_t page1:1; 943 uint32_t func:2; 944 uint32_t res1_1:28; 945 #endif 946 } ldw; 947 #if !defined(_BIG_ENDIAN) 948 uint32_t hdw; 949 #endif 950 } bits; 951 } log_page_vld_t, *p_log_page_vld_t; 952 953 954 #define DMA_LOG_PAGE_MASK_SHIFT 0 955 #define DMA_LOG_PAGE_MASK_MASK 0x00000000ffffffffULL 956 957 /* Receive Logical Page Mask */ 958 typedef union _log_page_mask_t { 959 uint64_t value; 960 struct { 961 #if defined(_BIG_ENDIAN) 962 uint32_t hdw; 963 #endif 964 struct { 965 #if defined(_BIT_FIELDS_HTOL) 966 uint32_t mask:32; 967 #elif defined(_BIT_FIELDS_LTOH) 968 uint32_t mask:32; 969 #endif 970 } ldw; 971 #if !defined(_BIG_ENDIAN) 972 uint32_t hdw; 973 #endif 974 } bits; 975 } log_page_mask_t, *p_log_page_mask_t; 976 977 978 /* Receive Logical Page Value */ 979 #define DMA_LOG_PAGE_VALUE_SHIFT 0 980 #define DMA_LOG_PAGE_VALUE_MASK 0x00000000ffffffffULL 981 982 /* Receive Logical Page Value */ 983 typedef union _log_page_value_t { 984 uint64_t value; 985 struct { 986 #if defined(_BIG_ENDIAN) 987 uint32_t hdw; 988 #endif 989 struct { 990 #if defined(_BIT_FIELDS_HTOL) 991 uint32_t value:32; 992 #elif defined(_BIT_FIELDS_LTOH) 993 uint32_t value:32; 994 #endif 995 } ldw; 996 #if !defined(_BIG_ENDIAN) 997 uint32_t hdw; 998 #endif 999 } bits; 1000 } log_page_value_t, *p_log_page_value_t; 1001 1002 /* Receive Logical Page Relocation */ 1003 #define DMA_LOG_PAGE_RELO_SHIFT 0 /* bits 31:0 */ 1004 #define DMA_LOG_PAGE_RELO_MASK 0x00000000ffffffffULL 1005 1006 /* Receive Logical Page Relocation */ 1007 typedef union _log_page_relo_t { 1008 uint64_t value; 1009 struct { 1010 #if defined(_BIG_ENDIAN) 1011 uint32_t hdw; 1012 #endif 1013 struct { 1014 #if defined(_BIT_FIELDS_HTOL) 1015 uint32_t relo:32; 1016 #elif defined(_BIT_FIELDS_LTOH) 1017 uint32_t relo:32; 1018 #endif 1019 } ldw; 1020 #if !defined(_BIG_ENDIAN) 1021 uint32_t hdw; 1022 #endif 1023 } bits; 1024 } log_page_relo_t, *p_log_page_relo_t; 1025 1026 1027 /* Receive Logical Page Handle */ 1028 #define DMA_LOG_PAGE_HANDLE_SHIFT 0 /* bits 19:0 */ 1029 #define DMA_LOG_PAGE_HANDLE_MASK 0x00000000ffffffffULL 1030 1031 /* Receive Logical Page Handle */ 1032 typedef union _log_page_hdl_t { 1033 uint64_t value; 1034 struct { 1035 #if defined(_BIG_ENDIAN) 1036 uint32_t hdw; 1037 #endif 1038 struct { 1039 #if defined(_BIT_FIELDS_HTOL) 1040 uint32_t res1_1:12; 1041 uint32_t handle:20; 1042 #elif defined(_BIT_FIELDS_LTOH) 1043 uint32_t handle:20; 1044 uint32_t res1_1:12; 1045 #endif 1046 } ldw; 1047 #if !defined(_BIG_ENDIAN) 1048 uint32_t hdw; 1049 #endif 1050 } bits; 1051 } log_page_hdl_t, *p_log_page_hdl_t; 1052 1053 #ifdef __cplusplus 1054 } 1055 #endif 1056 1057 #endif /* _SYS_NXGE_NXGE_HW_H */ 1058