1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_mac.h> 34 #include <nxge_ipp.h> 35 #include <nxge_fflp.h> 36 37 /* 38 * NXGE diagnostics IOCTLS. 39 */ 40 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 41 42 #define NXGE_GET64 (NXGE_IOC|1) 43 #define NXGE_PUT64 (NXGE_IOC|2) 44 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 45 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 46 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 47 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 48 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 49 #define NXGE_RESET_MAC (NXGE_IOC|8) 50 51 #define NXGE_GET_MII (NXGE_IOC|11) 52 #define NXGE_PUT_MII (NXGE_IOC|12) 53 #define NXGE_RTRACE (NXGE_IOC|13) 54 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 55 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 56 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 57 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 58 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 59 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 60 #define NXGE_RDUMP (NXGE_IOC|26) 61 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 62 #define NXGE_PIO_TEST (NXGE_IOC|28) 63 64 #define NXGE_GET_TCAM (NXGE_IOC|29) 65 #define NXGE_PUT_TCAM (NXGE_IOC|30) 66 #define NXGE_INJECT_ERR (NXGE_IOC|40) 67 68 #define NXGE_OK 0 69 #define NXGE_ERROR 0x40000000 70 #define NXGE_DDI_FAILED 0x20000000 71 #define NXGE_GET_PORT_NUM(n) n 72 73 /* 74 * Definitions for module_info. 75 */ 76 #define NXGE_IDNUM (0) /* module ID number */ 77 #define NXGE_DRIVER_NAME "nxge" /* module name */ 78 79 #define NXGE_MINPSZ (0) /* min packet size */ 80 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 81 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 82 #define NXGE_LOWAT (1) /* lo-water mark */ 83 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 84 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 85 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 86 #define NXGE_LOWAT_MIN (1) 87 88 #ifndef D_HOTPLUG 89 #define D_HOTPLUG 0x00 90 #endif 91 92 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 93 94 #define NXGE_CHECK_TIMER (5000) 95 96 typedef enum { 97 param_instance, 98 param_main_instance, 99 param_function_number, 100 param_partition_id, 101 param_read_write_mode, 102 param_fw_version, 103 param_port_mode, 104 param_niu_cfg_type, 105 param_tx_quick_cfg, 106 param_rx_quick_cfg, 107 param_master_cfg_enable, 108 param_master_cfg_value, 109 110 param_autoneg, 111 param_anar_10gfdx, 112 param_anar_10ghdx, 113 param_anar_1000fdx, 114 param_anar_1000hdx, 115 param_anar_100T4, 116 param_anar_100fdx, 117 param_anar_100hdx, 118 param_anar_10fdx, 119 param_anar_10hdx, 120 121 param_anar_asmpause, 122 param_anar_pause, 123 param_use_int_xcvr, 124 param_enable_ipg0, 125 param_ipg0, 126 param_ipg1, 127 param_ipg2, 128 param_txdma_weight, 129 param_txdma_channels_begin, 130 131 param_txdma_channels, 132 param_txdma_info, 133 param_rxdma_channels_begin, 134 param_rxdma_channels, 135 param_rxdma_drr_weight, 136 param_rxdma_full_header, 137 param_rxdma_info, 138 param_rxdma_rbr_size, 139 param_rxdma_rcr_size, 140 param_default_port_rdc, 141 param_rxdma_intr_time, 142 param_rxdma_intr_pkts, 143 144 param_rdc_grps_start, 145 param_rx_rdc_grps, 146 param_default_grp0_rdc, 147 param_default_grp1_rdc, 148 param_default_grp2_rdc, 149 param_default_grp3_rdc, 150 param_default_grp4_rdc, 151 param_default_grp5_rdc, 152 param_default_grp6_rdc, 153 param_default_grp7_rdc, 154 155 param_info_rdc_groups, 156 param_start_ldg, 157 param_max_ldg, 158 param_mac_2rdc_grp, 159 param_vlan_2rdc_grp, 160 param_fcram_part_cfg, 161 param_fcram_access_ratio, 162 param_tcam_access_ratio, 163 param_tcam_enable, 164 param_hash_lookup_enable, 165 param_llc_snap_enable, 166 167 param_h1_init_value, 168 param_h2_init_value, 169 param_class_cfg_ether_usr1, 170 param_class_cfg_ether_usr2, 171 param_class_cfg_ip_usr4, 172 param_class_cfg_ip_usr5, 173 param_class_cfg_ip_usr6, 174 param_class_cfg_ip_usr7, 175 param_class_opt_ip_usr4, 176 param_class_opt_ip_usr5, 177 param_class_opt_ip_usr6, 178 param_class_opt_ip_usr7, 179 param_class_opt_ipv4_tcp, 180 param_class_opt_ipv4_udp, 181 param_class_opt_ipv4_ah, 182 param_class_opt_ipv4_sctp, 183 param_class_opt_ipv6_tcp, 184 param_class_opt_ipv6_udp, 185 param_class_opt_ipv6_ah, 186 param_class_opt_ipv6_sctp, 187 param_nxge_debug_flag, 188 param_npi_debug_flag, 189 param_dump_rdc, 190 param_dump_tdc, 191 param_dump_mac_regs, 192 param_dump_ipp_regs, 193 param_dump_fflp_regs, 194 param_dump_vlan_table, 195 param_dump_rdc_table, 196 param_dump_ptrs, 197 param_end 198 } nxge_param_index_t; 199 200 typedef enum { 201 SOLARIS_DOMAIN, 202 SOLARIS_SERVICE_DOMAIN, 203 SOLARIS_GUEST_DOMAIN, 204 LINUX_SERVICE_DOMAIN, 205 LINUX_GUEST_DOMAIN 206 } nxge_environs_t; 207 208 /* 209 * Named Dispatch Parameter Management Structure 210 */ 211 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 212 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 213 MBLKP, char *, caddr_t, cred_t *); 214 215 #define NXGE_PARAM_READ 0x00000001ULL 216 #define NXGE_PARAM_WRITE 0x00000002ULL 217 #define NXGE_PARAM_SHARED 0x00000004ULL 218 #define NXGE_PARAM_PRIV 0x00000008ULL 219 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 220 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 221 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 222 223 #define NXGE_PARAM_RXDMA 0x00000010ULL 224 #define NXGE_PARAM_TXDMA 0x00000020ULL 225 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 226 #define NXGE_PARAM_MAC 0x00000080ULL 227 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 228 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 229 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 230 231 #define NXGE_PARAM_CMPLX 0x00010000ULL 232 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 233 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 234 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 235 236 #define NXGE_PARAM_READ_PROP 0x00100000ULL 237 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 238 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 239 #define NXGE_PARAM_PROP_STR 0x00800000ULL 240 241 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 242 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 243 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 244 #define NXGE_PARAM_BASE_STR 0x40000000ULL 245 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 246 247 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 248 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 249 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 250 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 251 252 typedef struct _nxge_param_t { 253 int (*getf)(); 254 int (*setf)(); /* null for read only */ 255 uint64_t type; /* R/W/ Common/Port/ .... */ 256 uint64_t minimum; 257 uint64_t maximum; 258 uint64_t value; /* for array params, pointer to value array */ 259 uint64_t old_value; /* for array params, pointer to old_value array */ 260 char *fcode_name; 261 char *name; 262 } nxge_param_t, *p_nxge_param_t; 263 264 265 /* 266 * Do not change the order of the elements of this enum as that will 267 * break the driver code. 268 */ 269 typedef enum { 270 nxge_lb_normal, 271 nxge_lb_ext10g, 272 nxge_lb_ext1000, 273 nxge_lb_ext100, 274 nxge_lb_ext10, 275 nxge_lb_phy10g, 276 nxge_lb_phy1000, 277 nxge_lb_phy, 278 nxge_lb_serdes10g, 279 nxge_lb_serdes1000, 280 nxge_lb_serdes, 281 nxge_lb_mac10g, 282 nxge_lb_mac1000, 283 nxge_lb_mac 284 } nxge_lb_t; 285 286 enum nxge_mac_state { 287 NXGE_MAC_STOPPED = 0, 288 NXGE_MAC_STARTED, 289 NXGE_MAC_STOPPING 290 }; 291 292 /* 293 * Private DLPI full dlsap address format. 294 */ 295 typedef struct _nxge_dladdr_t { 296 ether_addr_st dl_phys; 297 uint16_t dl_sap; 298 } nxge_dladdr_t, *p_nxge_dladdr_t; 299 300 typedef struct _mc_addr_t { 301 ether_addr_st multcast_addr; 302 uint_t mc_addr_cnt; 303 } mc_addr_t, *p_mc_addr_t; 304 305 typedef struct _mc_bucket_t { 306 p_mc_addr_t addr_list; 307 uint_t list_size; 308 } mc_bucket_t, *p_mc_bucket_t; 309 310 typedef struct _mc_table_t { 311 p_mc_bucket_t bucket_list; 312 uint_t buckets_used; 313 } mc_table_t, *p_mc_table_t; 314 315 typedef struct _filter_t { 316 uint32_t all_phys_cnt; 317 uint32_t all_multicast_cnt; 318 uint32_t all_sap_cnt; 319 } filter_t, *p_filter_t; 320 321 322 typedef struct _nxge_port_stats_t { 323 /* 324 * Overall structure size 325 */ 326 size_t stats_size; 327 328 /* 329 * Link Input/Output stats 330 */ 331 uint64_t ipackets; 332 uint64_t ierrors; 333 uint64_t opackets; 334 uint64_t oerrors; 335 uint64_t collisions; 336 337 /* 338 * MIB II variables 339 */ 340 uint64_t rbytes; /* # bytes received */ 341 uint64_t obytes; /* # bytes transmitted */ 342 uint32_t multircv; /* # multicast packets received */ 343 uint32_t multixmt; /* # multicast packets for xmit */ 344 uint32_t brdcstrcv; /* # broadcast packets received */ 345 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 346 uint32_t norcvbuf; /* # rcv packets discarded */ 347 uint32_t noxmtbuf; /* # xmit packets discarded */ 348 349 /* 350 * Lets the user know the MTU currently in use by 351 * the physical MAC port. 352 */ 353 nxge_lb_t lb_mode; 354 uint32_t qos_mode; 355 uint32_t trunk_mode; 356 uint32_t poll_mode; 357 358 /* 359 * Tx Statistics. 360 */ 361 uint32_t tx_inits; 362 uint32_t tx_starts; 363 uint32_t tx_nocanput; 364 uint32_t tx_msgdup_fail; 365 uint32_t tx_allocb_fail; 366 uint32_t tx_no_desc; 367 uint32_t tx_dma_bind_fail; 368 uint32_t tx_uflo; 369 uint32_t tx_hdr_pkts; 370 uint32_t tx_ddi_pkts; 371 uint32_t tx_dvma_pkts; 372 373 uint32_t tx_max_pend; 374 375 /* 376 * Rx Statistics. 377 */ 378 uint32_t rx_inits; 379 uint32_t rx_hdr_pkts; 380 uint32_t rx_mtu_pkts; 381 uint32_t rx_split_pkts; 382 uint32_t rx_no_buf; 383 uint32_t rx_no_comp_wb; 384 uint32_t rx_ov_flow; 385 uint32_t rx_len_mm; 386 uint32_t rx_tag_err; 387 uint32_t rx_nocanput; 388 uint32_t rx_msgdup_fail; 389 uint32_t rx_allocb_fail; 390 391 /* 392 * Receive buffer management statistics. 393 */ 394 uint32_t rx_new_pages; 395 uint32_t rx_new_hdr_pgs; 396 uint32_t rx_new_mtu_pgs; 397 uint32_t rx_new_nxt_pgs; 398 uint32_t rx_reused_pgs; 399 uint32_t rx_hdr_drops; 400 uint32_t rx_mtu_drops; 401 uint32_t rx_nxt_drops; 402 403 /* 404 * Receive flow statistics 405 */ 406 uint32_t rx_rel_flow; 407 uint32_t rx_rel_bit; 408 409 uint32_t rx_pkts_dropped; 410 411 /* 412 * PCI-E Bus Statistics. 413 */ 414 uint32_t pci_bus_speed; 415 uint32_t pci_err; 416 uint32_t pci_rta_err; 417 uint32_t pci_rma_err; 418 uint32_t pci_parity_err; 419 uint32_t pci_bad_ack_err; 420 uint32_t pci_drto_err; 421 uint32_t pci_dmawz_err; 422 uint32_t pci_dmarz_err; 423 424 uint32_t rx_taskq_waits; 425 426 uint32_t tx_jumbo_pkts; 427 428 /* 429 * Some statistics added to support bringup, these 430 * should be removed. 431 */ 432 uint32_t user_defined; 433 } nxge_port_stats_t, *p_nxge_port_stats_t; 434 435 436 typedef struct _nxge_stats_t { 437 /* 438 * Overall structure size 439 */ 440 size_t stats_size; 441 442 kstat_t *ksp; 443 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 444 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 445 kstat_t *rdc_sys_ksp; 446 kstat_t *fflp_ksp[1]; 447 kstat_t *ipp_ksp; 448 kstat_t *txc_ksp; 449 kstat_t *mac_ksp; 450 kstat_t *zcp_ksp; 451 kstat_t *port_ksp; 452 kstat_t *mmac_ksp; 453 454 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 455 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 456 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 457 458 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 459 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 460 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 461 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 462 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 463 464 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 465 nxge_txc_stats_t txc_stats; /* per port TX stats */ 466 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 467 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 468 nxge_port_stats_t port_stats; /* fflp stats */ 469 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 470 471 } nxge_stats_t, *p_nxge_stats_t; 472 473 474 475 typedef struct _nxge_intr_t { 476 boolean_t intr_registered; /* interrupts are registered */ 477 boolean_t intr_enabled; /* interrupts are enabled */ 478 boolean_t niu_msi_enable; /* debug or configurable? */ 479 int intr_types; /* interrupt types supported */ 480 int intr_type; /* interrupt type to add */ 481 int max_int_cnt; /* max MSIX/INT HW supports */ 482 int start_inum; /* start inum (in sequence?) */ 483 int msi_intx_cnt; /* # msi/intx ints returned */ 484 int intr_added; /* # ints actually needed */ 485 int intr_cap; /* interrupt capabilities */ 486 size_t intr_size; /* size of array to allocate */ 487 ddi_intr_handle_t *htable; /* For array of interrupts */ 488 /* Add interrupt number for each interrupt vector */ 489 int pri; 490 } nxge_intr_t, *p_nxge_intr_t; 491 492 typedef struct _nxge_ldgv_t { 493 uint8_t ndma_ldvs; 494 uint8_t nldvs; 495 uint8_t maxldgs; 496 uint8_t maxldvs; 497 uint8_t ldg_intrs; 498 uint32_t tmres; 499 p_nxge_ldg_t ldgp; 500 p_nxge_ldv_t ldvp; 501 p_nxge_ldv_t ldvp_syserr; 502 boolean_t ldvp_syserr_alloced; 503 } nxge_ldgv_t, *p_nxge_ldgv_t; 504 505 typedef enum { 506 NXGE_TRANSMIT_GROUP, /* Legacy transmit group */ 507 NXGE_RECEIVE_GROUP, /* Legacy receive group */ 508 NXGE_VR_GROUP, /* Virtualization Region group */ 509 EXT_TRANSMIT_GROUP, /* External (Crossbow) transmit group */ 510 EXT_RECEIVE_GROUP /* External (Crossbow) receive group */ 511 } nxge_grp_type_t; 512 513 #define NXGE_ILLEGAL_CHANNEL (NXGE_MAX_TDCS + 1) 514 515 typedef uint8_t nxge_channel_t; 516 517 typedef struct nxge_grp { 518 nxge_t *nxge; 519 nxge_grp_type_t type; /* Tx or Rx */ 520 521 int sequence; /* When it was created. */ 522 int index; /* nxge_grp_set_t.group[index] */ 523 524 struct nx_dc *dc; /* Linked list of DMA channels. */ 525 size_t count; /* A count of <dc> above. */ 526 527 boolean_t active; /* Is it being used? */ 528 529 dc_map_t map; /* A bitmap of the channels in <dc>. */ 530 nxge_channel_t legend[NXGE_MAX_TDCS]; 531 532 } nxge_grp_t; 533 534 typedef struct { 535 lg_map_t map; 536 size_t count; 537 } lg_data_t; 538 539 typedef struct { 540 dc_map_t map; 541 size_t count; 542 } dc_data_t; 543 544 #define NXGE_DC_SET(map, channel) map |= (1 << channel) 545 #define NXGE_DC_RESET(map, channel) map &= (~(1 << channel)) 546 547 /* For now, we only support up to 8 RDC/TDC groups */ 548 #define NXGE_LOGICAL_GROUP_MAX NXGE_MAX_RDC_GROUPS 549 550 typedef struct { 551 int sequence; /* To order groups in time. */ 552 553 /* These are this instance's logical groups. */ 554 nxge_grp_t *group[NXGE_LOGICAL_GROUP_MAX]; 555 lg_data_t lg; 556 557 dc_data_t shared; /* These DCs are being shared. */ 558 dc_data_t owned; /* These DCs belong to me. */ 559 dc_data_t dead; /* These DCs are in an error state. */ 560 561 } nxge_grp_set_t; 562 563 /* 564 * Transmit Ring Group 565 * TX groups will be used exclusively for the purpose of Hybrid I/O. From 566 * the point of view of the nxge driver, the groups will be software 567 * constructs which will be used to establish the relationship between TX 568 * rings and shares. 569 * 570 * Receive Ring Group 571 * One of the advanced virtualization features is the ability to bundle 572 * multiple Receive Rings in a single group. One or more MAC addresses may 573 * be assigned to a group. Incoming packets destined to the group's MAC 574 * address(es) are delivered to any ring member, according to a programmable 575 * or predefined RTS policy. Member rings can be polled individually. 576 * RX ring groups can come with a predefined set of member rings, or they 577 * are programmable by adding and removing rings to/from them. 578 */ 579 typedef struct _nxge_ring_group_t { 580 mac_group_handle_t ghandle; 581 p_nxge_t nxgep; 582 boolean_t started; 583 boolean_t port_default_grp; 584 mac_ring_type_t type; 585 int gindex; 586 int sindex; 587 int rdctbl; 588 int n_mac_addrs; 589 } nxge_ring_group_t; 590 591 /* 592 * Ring Handle 593 */ 594 typedef struct _nxge_ring_handle_t { 595 p_nxge_t nxgep; 596 int index; /* port-wise */ 597 mac_ring_handle_t ring_handle; 598 } nxge_ring_handle_t, *p_nxge_ring_handle_t; 599 600 /* 601 * Share Handle 602 */ 603 typedef struct _nxge_share_handle_t { 604 p_nxge_t nxgep; /* Driver Handle */ 605 int index; 606 void *vrp; 607 uint64_t tmap; 608 uint64_t rmap; 609 int rxgroup; 610 boolean_t active; 611 } nxge_share_handle_t; 612 613 /* 614 * Neptune Device instance state information. 615 * 616 * Each instance is dynamically allocated on first attach. 617 */ 618 struct _nxge_t { 619 dev_info_t *dip; /* device instance */ 620 dev_info_t *p_dip; /* Parent's device instance */ 621 int instance; /* instance number */ 622 int function_num; /* device function number */ 623 int nports; /* # of ports on this device */ 624 int board_ver; /* Board Version */ 625 int use_partition; /* partition is enabled */ 626 uint32_t drv_state; /* driver state bit flags */ 627 uint64_t nxge_debug_level; /* driver state bit flags */ 628 kmutex_t genlock[1]; 629 enum nxge_mac_state nxge_mac_state; 630 631 p_dev_regs_t dev_regs; 632 npi_handle_t npi_handle; 633 npi_handle_t npi_pci_handle; 634 npi_handle_t npi_reg_handle; 635 npi_handle_t npi_msi_handle; 636 npi_handle_t npi_vreg_handle; 637 npi_handle_t npi_v2reg_handle; 638 639 nxge_xcvr_table_t xcvr; 640 boolean_t hot_swappable_phy; 641 boolean_t phy_absent; 642 uint32_t xcvr_addr; 643 uint16_t chip_id; 644 nxge_mac_t mac; 645 nxge_ipp_t ipp; 646 nxge_txc_t txc; 647 nxge_classify_t classifier; 648 649 mac_handle_t mach; /* mac module handle */ 650 p_nxge_stats_t statsp; 651 uint32_t param_count; 652 p_nxge_param_t param_arr; 653 654 uint32_t param_en_pause:1, 655 param_en_asym_pause:1, 656 param_en_1000fdx:1, 657 param_en_100fdx:1, 658 param_en_10fdx:1, 659 param_pad_to_32:27; 660 661 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 662 niu_type_t niu_type; 663 platform_type_t platform_type; 664 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 665 666 uint8_t def_rdc; 667 668 nxge_intr_t nxge_intr_type; 669 nxge_dma_pt_cfg_t pt_config; 670 nxge_class_pt_cfg_t class_config; 671 672 /* Logical device and group data structures. */ 673 p_nxge_ldgv_t ldgvp; 674 675 npi_vpd_info_t vpd_info; 676 677 ether_addr_st factaddr; /* factory mac address */ 678 ether_addr_st ouraddr; /* individual address */ 679 boolean_t primary; /* primary addr set?. */ 680 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 681 682 ddi_iblock_cookie_t interrupt_cookie; 683 684 /* 685 * Blocks of memory may be pre-allocated by the 686 * partition manager or the driver. They may include 687 * blocks for configuration and buffers. The idea is 688 * to preallocate big blocks of contiguous areas in 689 * system memory (i.e. with IOMMU). These blocks then 690 * will be broken up to a fixed number of blocks with 691 * each block having the same block size (4K, 8K, 16K or 692 * 32K) in the case of buffer blocks. For systems that 693 * do not support DVMA, more than one big block will be 694 * allocated. 695 */ 696 uint32_t rx_default_block_size; 697 nxge_rx_block_size_t rx_bksize_code; 698 699 p_nxge_dma_pool_t rx_buf_pool_p; 700 p_nxge_dma_pool_t rx_cntl_pool_p; 701 702 p_nxge_dma_pool_t tx_buf_pool_p; 703 p_nxge_dma_pool_t tx_cntl_pool_p; 704 705 /* Receive buffer block ring and completion ring. */ 706 p_rx_rbr_rings_t rx_rbr_rings; 707 p_rx_rcr_rings_t rx_rcr_rings; 708 p_rx_mbox_areas_t rx_mbox_areas_p; 709 710 uint32_t rdc_mask; 711 712 /* Transmit descriptors rings */ 713 p_tx_rings_t tx_rings; 714 p_tx_mbox_areas_t tx_mbox_areas_p; 715 716 ddi_dma_handle_t dmasparehandle; 717 718 ulong_t sys_page_sz; 719 ulong_t sys_page_mask; 720 int suspended; 721 722 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 723 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 724 725 kmutex_t mif_lock; /* Lock to protect the list. */ 726 727 void (*mii_read)(); 728 void (*mii_write)(); 729 void (*mii_poll)(); 730 filter_t filter; /* Current instance filter */ 731 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 732 krwlock_t filter_lock; /* Lock to protect filters. */ 733 734 ulong_t sys_burst_sz; 735 736 uint8_t cache_line; 737 738 timeout_id_t nxge_link_poll_timerid; 739 timeout_id_t nxge_timerid; 740 741 uint_t need_periodic_reclaim; 742 timeout_id_t reclaim_timer; 743 744 uint8_t msg_min; 745 uint8_t crc_size; 746 747 boolean_t hard_props_read; 748 749 uint32_t nxge_ncpus; 750 uint16_t intr_timeout; 751 uint16_t intr_threshold; 752 753 int fm_capabilities; /* FMA capabilities */ 754 755 uint32_t nxge_port_rbr_size; 756 uint32_t nxge_port_rbr_spare_size; 757 uint32_t nxge_port_rcr_size; 758 uint32_t nxge_port_rx_cntl_alloc_size; 759 uint32_t nxge_port_tx_ring_size; 760 nxge_mmac_t nxge_mmac_info; 761 #if defined(sun4v) 762 boolean_t niu_hsvc_available; 763 hsvc_info_t niu_hsvc; 764 uint64_t niu_min_ver; 765 #endif 766 boolean_t link_notify; 767 768 kmutex_t poll_lock; 769 kcondvar_t poll_cv; 770 link_mon_enable_t poll_state; 771 #define NXGE_MAGIC 0x3ab434e3 772 uint32_t nxge_magic; 773 774 int soft_lso_enable; 775 /* The following fields are LDOMs-specific additions. */ 776 nxge_environs_t environs; 777 ether_addr_t hio_mac_addr; 778 uint32_t niu_cfg_hdl; 779 kmutex_t group_lock; 780 781 struct nxge_hio_vr *hio_vr; 782 783 nxge_grp_set_t rx_set; 784 nxge_grp_set_t tx_set; 785 boolean_t tdc_is_shared[NXGE_MAX_TDCS]; 786 787 boolean_t rx_channel_started[NXGE_MAX_RDCS]; 788 789 /* Ring Handles */ 790 nxge_ring_handle_t tx_ring_handles[NXGE_MAX_TDCS]; 791 nxge_ring_handle_t rx_ring_handles[NXGE_MAX_RDCS]; 792 793 nxge_ring_group_t tx_hio_groups[NXGE_MAX_TDC_GROUPS]; 794 nxge_ring_group_t rx_hio_groups[NXGE_MAX_RDC_GROUPS]; 795 796 nxge_share_handle_t shares[NXGE_MAX_VRS]; 797 }; 798 799 /* 800 * Driver state flags. 801 */ 802 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 803 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 804 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 805 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 806 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 807 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 808 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 809 810 #define STOP_POLL_THRESH 9 811 #define START_POLL_THRESH 2 812 813 typedef struct _nxge_port_kstat_t { 814 /* 815 * Transciever state informations. 816 */ 817 kstat_named_t xcvr_inits; 818 kstat_named_t xcvr_inuse; 819 kstat_named_t xcvr_addr; 820 kstat_named_t xcvr_id; 821 kstat_named_t cap_autoneg; 822 kstat_named_t cap_10gfdx; 823 kstat_named_t cap_10ghdx; 824 kstat_named_t cap_1000fdx; 825 kstat_named_t cap_1000hdx; 826 kstat_named_t cap_100T4; 827 kstat_named_t cap_100fdx; 828 kstat_named_t cap_100hdx; 829 kstat_named_t cap_10fdx; 830 kstat_named_t cap_10hdx; 831 kstat_named_t cap_asmpause; 832 kstat_named_t cap_pause; 833 834 /* 835 * Link partner capabilities. 836 */ 837 kstat_named_t lp_cap_autoneg; 838 kstat_named_t lp_cap_10gfdx; 839 kstat_named_t lp_cap_10ghdx; 840 kstat_named_t lp_cap_1000fdx; 841 kstat_named_t lp_cap_1000hdx; 842 kstat_named_t lp_cap_100T4; 843 kstat_named_t lp_cap_100fdx; 844 kstat_named_t lp_cap_100hdx; 845 kstat_named_t lp_cap_10fdx; 846 kstat_named_t lp_cap_10hdx; 847 kstat_named_t lp_cap_asmpause; 848 kstat_named_t lp_cap_pause; 849 850 /* 851 * Shared link setup. 852 */ 853 kstat_named_t link_T4; 854 kstat_named_t link_speed; 855 kstat_named_t link_duplex; 856 kstat_named_t link_asmpause; 857 kstat_named_t link_pause; 858 kstat_named_t link_up; 859 860 /* 861 * Lets the user know the MTU currently in use by 862 * the physical MAC port. 863 */ 864 kstat_named_t mac_mtu; 865 kstat_named_t lb_mode; 866 kstat_named_t qos_mode; 867 kstat_named_t trunk_mode; 868 869 /* 870 * Misc MAC statistics. 871 */ 872 kstat_named_t ifspeed; 873 kstat_named_t promisc; 874 kstat_named_t rev_id; 875 876 /* 877 * Some statistics added to support bringup, these 878 * should be removed. 879 */ 880 kstat_named_t user_defined; 881 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 882 883 typedef struct _nxge_rdc_kstat { 884 /* 885 * Receive DMA channel statistics. 886 */ 887 kstat_named_t ipackets; 888 kstat_named_t rbytes; 889 kstat_named_t errors; 890 kstat_named_t dcf_err; 891 kstat_named_t rcr_ack_err; 892 893 kstat_named_t dc_fifoflow_err; 894 kstat_named_t rcr_sha_par_err; 895 kstat_named_t rbr_pre_par_err; 896 kstat_named_t wred_drop; 897 kstat_named_t rbr_pre_emty; 898 899 kstat_named_t rcr_shadow_full; 900 kstat_named_t rbr_tmout; 901 kstat_named_t rsp_cnt_err; 902 kstat_named_t byte_en_bus; 903 kstat_named_t rsp_dat_err; 904 905 kstat_named_t pkt_too_long_err; 906 kstat_named_t compl_l2_err; 907 kstat_named_t compl_l4_cksum_err; 908 kstat_named_t compl_zcp_soft_err; 909 kstat_named_t compl_fflp_soft_err; 910 kstat_named_t config_err; 911 912 kstat_named_t rcrincon; 913 kstat_named_t rcrfull; 914 kstat_named_t rbr_empty; 915 kstat_named_t rbrfull; 916 kstat_named_t rbrlogpage; 917 918 kstat_named_t cfiglogpage; 919 kstat_named_t port_drop_pkt; 920 kstat_named_t rcr_to; 921 kstat_named_t rcr_thresh; 922 kstat_named_t rcr_mex; 923 kstat_named_t id_mismatch; 924 kstat_named_t zcp_eop_err; 925 kstat_named_t ipp_eop_err; 926 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 927 928 typedef struct _nxge_rdc_sys_kstat { 929 /* 930 * Receive DMA system statistics. 931 */ 932 kstat_named_t pre_par; 933 kstat_named_t sha_par; 934 kstat_named_t id_mismatch; 935 kstat_named_t ipp_eop_err; 936 kstat_named_t zcp_eop_err; 937 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 938 939 typedef struct _nxge_tdc_kstat { 940 /* 941 * Transmit DMA channel statistics. 942 */ 943 kstat_named_t opackets; 944 kstat_named_t obytes; 945 kstat_named_t oerrors; 946 kstat_named_t tx_inits; 947 kstat_named_t tx_no_buf; 948 949 kstat_named_t mbox_err; 950 kstat_named_t pkt_size_err; 951 kstat_named_t tx_ring_oflow; 952 kstat_named_t pref_buf_ecc_err; 953 kstat_named_t nack_pref; 954 kstat_named_t nack_pkt_rd; 955 kstat_named_t conf_part_err; 956 kstat_named_t pkt_prt_err; 957 kstat_named_t reset_fail; 958 /* used to in the common (per port) counter */ 959 960 kstat_named_t tx_starts; 961 kstat_named_t tx_nocanput; 962 kstat_named_t tx_msgdup_fail; 963 kstat_named_t tx_allocb_fail; 964 kstat_named_t tx_no_desc; 965 kstat_named_t tx_dma_bind_fail; 966 kstat_named_t tx_uflo; 967 kstat_named_t tx_hdr_pkts; 968 kstat_named_t tx_ddi_pkts; 969 kstat_named_t tx_dvma_pkts; 970 kstat_named_t tx_max_pend; 971 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 972 973 typedef struct _nxge_txc_kstat { 974 /* 975 * Transmit port TXC block statistics. 976 */ 977 kstat_named_t pkt_stuffed; 978 kstat_named_t pkt_xmit; 979 kstat_named_t ro_correct_err; 980 kstat_named_t ro_uncorrect_err; 981 kstat_named_t sf_correct_err; 982 kstat_named_t sf_uncorrect_err; 983 kstat_named_t address_failed; 984 kstat_named_t dma_failed; 985 kstat_named_t length_failed; 986 kstat_named_t pkt_assy_dead; 987 kstat_named_t reorder_err; 988 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 989 990 typedef struct _nxge_ipp_kstat { 991 /* 992 * Receive port IPP block statistics. 993 */ 994 kstat_named_t eop_miss; 995 kstat_named_t sop_miss; 996 kstat_named_t dfifo_ue; 997 kstat_named_t ecc_err_cnt; 998 kstat_named_t pfifo_perr; 999 kstat_named_t pfifo_over; 1000 kstat_named_t pfifo_und; 1001 kstat_named_t bad_cs_cnt; 1002 kstat_named_t pkt_dis_cnt; 1003 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 1004 1005 typedef struct _nxge_zcp_kstat { 1006 /* 1007 * ZCP statistics. 1008 */ 1009 kstat_named_t errors; 1010 kstat_named_t inits; 1011 kstat_named_t rrfifo_underrun; 1012 kstat_named_t rrfifo_overrun; 1013 kstat_named_t rspfifo_uncorr_err; 1014 kstat_named_t buffer_overflow; 1015 kstat_named_t stat_tbl_perr; 1016 kstat_named_t dyn_tbl_perr; 1017 kstat_named_t buf_tbl_perr; 1018 kstat_named_t tt_program_err; 1019 kstat_named_t rsp_tt_index_err; 1020 kstat_named_t slv_tt_index_err; 1021 kstat_named_t zcp_tt_index_err; 1022 kstat_named_t access_fail; 1023 kstat_named_t cfifo_ecc; 1024 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 1025 1026 typedef struct _nxge_mac_kstat { 1027 /* 1028 * Transmit MAC statistics. 1029 */ 1030 kstat_named_t tx_frame_cnt; 1031 kstat_named_t tx_underflow_err; 1032 kstat_named_t tx_overflow_err; 1033 kstat_named_t tx_maxpktsize_err; 1034 kstat_named_t tx_fifo_xfr_err; 1035 kstat_named_t tx_byte_cnt; 1036 1037 /* 1038 * Receive MAC statistics. 1039 */ 1040 kstat_named_t rx_frame_cnt; 1041 kstat_named_t rx_underflow_err; 1042 kstat_named_t rx_overflow_err; 1043 kstat_named_t rx_len_err_cnt; 1044 kstat_named_t rx_crc_err_cnt; 1045 kstat_named_t rx_viol_err_cnt; 1046 kstat_named_t rx_byte_cnt; 1047 kstat_named_t rx_hist1_cnt; 1048 kstat_named_t rx_hist2_cnt; 1049 kstat_named_t rx_hist3_cnt; 1050 kstat_named_t rx_hist4_cnt; 1051 kstat_named_t rx_hist5_cnt; 1052 kstat_named_t rx_hist6_cnt; 1053 kstat_named_t rx_hist7_cnt; 1054 kstat_named_t rx_broadcast_cnt; 1055 kstat_named_t rx_mult_cnt; 1056 kstat_named_t rx_frag_cnt; 1057 kstat_named_t rx_frame_align_err_cnt; 1058 kstat_named_t rx_linkfault_err_cnt; 1059 kstat_named_t rx_local_fault_err_cnt; 1060 kstat_named_t rx_remote_fault_err_cnt; 1061 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 1062 1063 typedef struct _nxge_xmac_kstat { 1064 /* 1065 * XMAC statistics. 1066 */ 1067 kstat_named_t tx_frame_cnt; 1068 kstat_named_t tx_underflow_err; 1069 kstat_named_t tx_maxpktsize_err; 1070 kstat_named_t tx_overflow_err; 1071 kstat_named_t tx_fifo_xfr_err; 1072 kstat_named_t tx_byte_cnt; 1073 kstat_named_t rx_frame_cnt; 1074 kstat_named_t rx_underflow_err; 1075 kstat_named_t rx_overflow_err; 1076 kstat_named_t rx_crc_err_cnt; 1077 kstat_named_t rx_len_err_cnt; 1078 kstat_named_t rx_viol_err_cnt; 1079 kstat_named_t rx_byte_cnt; 1080 kstat_named_t rx_hist1_cnt; 1081 kstat_named_t rx_hist2_cnt; 1082 kstat_named_t rx_hist3_cnt; 1083 kstat_named_t rx_hist4_cnt; 1084 kstat_named_t rx_hist5_cnt; 1085 kstat_named_t rx_hist6_cnt; 1086 kstat_named_t rx_hist7_cnt; 1087 kstat_named_t rx_broadcast_cnt; 1088 kstat_named_t rx_mult_cnt; 1089 kstat_named_t rx_frag_cnt; 1090 kstat_named_t rx_frame_align_err_cnt; 1091 kstat_named_t rx_linkfault_err_cnt; 1092 kstat_named_t rx_remote_fault_err_cnt; 1093 kstat_named_t rx_local_fault_err_cnt; 1094 kstat_named_t rx_pause_cnt; 1095 kstat_named_t xpcs_deskew_err_cnt; 1096 kstat_named_t xpcs_ln0_symbol_err_cnt; 1097 kstat_named_t xpcs_ln1_symbol_err_cnt; 1098 kstat_named_t xpcs_ln2_symbol_err_cnt; 1099 kstat_named_t xpcs_ln3_symbol_err_cnt; 1100 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 1101 1102 typedef struct _nxge_bmac_kstat { 1103 /* 1104 * BMAC statistics. 1105 */ 1106 kstat_named_t tx_frame_cnt; 1107 kstat_named_t tx_underrun_err; 1108 kstat_named_t tx_max_pkt_err; 1109 kstat_named_t tx_byte_cnt; 1110 kstat_named_t rx_frame_cnt; 1111 kstat_named_t rx_byte_cnt; 1112 kstat_named_t rx_overflow_err; 1113 kstat_named_t rx_align_err_cnt; 1114 kstat_named_t rx_crc_err_cnt; 1115 kstat_named_t rx_len_err_cnt; 1116 kstat_named_t rx_viol_err_cnt; 1117 kstat_named_t rx_pause_cnt; 1118 kstat_named_t tx_pause_state; 1119 kstat_named_t tx_nopause_state; 1120 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1121 1122 1123 typedef struct _nxge_fflp_kstat { 1124 /* 1125 * FFLP statistics. 1126 */ 1127 1128 kstat_named_t fflp_tcam_perr; 1129 kstat_named_t fflp_tcam_ecc_err; 1130 kstat_named_t fflp_vlan_perr; 1131 kstat_named_t fflp_hasht_lookup_err; 1132 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1133 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1134 1135 typedef struct _nxge_mmac_kstat { 1136 kstat_named_t mmac_max_addr_cnt; 1137 kstat_named_t mmac_avail_addr_cnt; 1138 kstat_named_t mmac_addr1; 1139 kstat_named_t mmac_addr2; 1140 kstat_named_t mmac_addr3; 1141 kstat_named_t mmac_addr4; 1142 kstat_named_t mmac_addr5; 1143 kstat_named_t mmac_addr6; 1144 kstat_named_t mmac_addr7; 1145 kstat_named_t mmac_addr8; 1146 kstat_named_t mmac_addr9; 1147 kstat_named_t mmac_addr10; 1148 kstat_named_t mmac_addr11; 1149 kstat_named_t mmac_addr12; 1150 kstat_named_t mmac_addr13; 1151 kstat_named_t mmac_addr14; 1152 kstat_named_t mmac_addr15; 1153 kstat_named_t mmac_addr16; 1154 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1155 1156 /* 1157 * Prototype definitions. 1158 */ 1159 nxge_status_t nxge_init(p_nxge_t); 1160 void nxge_uninit(p_nxge_t); 1161 void nxge_get64(p_nxge_t, p_mblk_t); 1162 void nxge_put64(p_nxge_t, p_mblk_t); 1163 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1164 1165 typedef void (*fptrv_t)(); 1166 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1167 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1168 1169 #ifdef __cplusplus 1170 } 1171 #endif 1172 1173 #endif /* _SYS_NXGE_NXGE_H */ 1174