1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_CRYPTO_DCA_H 28 #define _SYS_CRYPTO_DCA_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/varargs.h> 38 39 #include <sys/crypto/spi.h> 40 41 /* 42 * Deimos - cryptographic acceleration based upon Broadcom 582x. 43 * 44 * Note: Everything in this file is private to the Deimos device 45 * driver! Do not include this in any other file. 46 */ 47 48 #define DRIVER "dca" 49 #define DCA_MANUFACTURER_ID "SUNWdca" 50 51 #ifdef _KERNEL 52 53 /* 54 * Tunables. 55 */ 56 #define MCR1LOWATER 16 /* these numbers favor overall throughput */ 57 #define MCR1HIWATER 24 58 #define MCR1MAXREQS 8 59 #define MCR2LOWATER 16 60 #define MCR2HIWATER 24 61 #define MCR2MAXREQS 4 62 #define MAXMCR 2 /* there are 2 mcrs */ 63 #define MAXREQSPERMCR 16 /* there are 4 subunits serviced by MCR2 */ 64 #define MAXFRAGS 6 /* Limit on the number of fragments */ 65 #define MAXWORK 6 /* How many work structures to preallocate */ 66 67 /* 68 * These are constants. Do not change them. 69 */ 70 #if defined(i386) || defined(__i386) || defined(__amd64) 71 #define MAXPACKET 0xefff /* rootnex INT_MAX_BUF hack. */ 72 #else 73 #define MAXPACKET 0xffff /* Max size of a packet or fragment */ 74 #endif 75 #define DESBLOCK 8 /* Size of a DES or 3DES block */ 76 #define DSAPARTLEN 20 /* Size of fixed DSA parts (r, s, q, x, v) */ 77 #define DSASIGLEN 40 /* Size of a DSA signature */ 78 #define SHA1LEN 20 /* Size of a SHA1 hash */ 79 #define SECOND 1000000 /* One second in usec */ 80 #define MSEC 1000 /* One millisecond in usec */ 81 #define DES_KEYSIZE 8 82 #define DES_IV_LEN 8 83 #define DES3_KEYSIZE (3 * DES_KEYSIZE) 84 85 /* 86 * Mechanism info structure passed to KCF during registration. 87 */ 88 89 #define MD5_HMAC_BLOCK_SIZE 64 /* MD5-HMAC block size */ 90 #define MD5_HMAC_MIN_KEY_LEN 1 /* MD5-HMAC min key length in bytes */ 91 #define MD5_HMAC_MAX_KEY_LEN 64 /* MD5-HMAC max key length in bytes */ 92 93 #define SHA1_HMAC_BLOCK_SIZE 64 /* SHA1-HMAC block size */ 94 #define SHA1_HMAC_MIN_KEY_LEN 1 /* SHA1-HMAC min key length in bytes */ 95 #define SHA1_HMAC_MAX_KEY_LEN 64 /* SHA1-HMAC max key length in bytes */ 96 97 #define DES_KEY_LEN 8 /* DES key length in bytes */ 98 #define DES3_KEY_LEN 24 /* 3DES key length in bytes */ 99 100 #define DSA_MIN_KEY_LEN 64 /* DSA min key length in bytes */ 101 #define DSA_MAX_KEY_LEN 128 /* DSA max key length in bytes */ 102 103 #define RSA_MIN_KEY_LEN 32 /* RSA min key length in bytes */ 104 #define RSA_MAX_KEY_LEN 256 /* RSA max key length in bytes */ 105 106 /* 107 * RSA implementation. 108 */ 109 110 #define DCA_RSA_ENC 0 111 #define DCA_RSA_DEC 1 112 #define DCA_RSA_SIGN 2 113 #define DCA_RSA_VRFY 3 114 #define DCA_RSA_SIGNR 4 115 #define DCA_RSA_VRFYR 5 116 117 /* 118 * DSA implementation. 119 */ 120 121 #define DCA_DSA_SIGN 0 122 #define DCA_DSA_VRFY 1 123 124 /* 125 * FMA eclass index definitions. Note that this enum must be consistent 126 * with the dca_fma_eclass_sca1000 and dca_fma_eclass_sca500 string arrays. 127 */ 128 typedef enum dca_fma_eclass { 129 DCA_FM_ECLASS_HW_DEVICE = 0, 130 DCA_FM_ECLASS_HW_TIMEOUT, 131 DCA_FM_ECLASS_NONE 132 } dca_fma_eclass_t; 133 134 /* 135 * Forward typedefs. 136 */ 137 typedef struct dca dca_t; 138 typedef struct dca_chain dca_chain_t; 139 typedef struct dca_listnode dca_listnode_t; 140 typedef struct dca_worklist dca_worklist_t; 141 typedef struct dca_work dca_work_t; 142 typedef struct dca_request dca_request_t; 143 typedef struct dca_stat dca_stat_t; 144 typedef struct dca_cookie dca_cookie_t; 145 typedef struct dca_device dca_device_t; 146 147 /* 148 * This structure is used to identify a specific board. 149 */ 150 struct dca_device { 151 ushort_t dd_vendor_id; 152 ushort_t dd_device_id; 153 char *dd_model; 154 }; 155 156 /* 157 * Structure representing a node in a DMA chain. (Broadcom calls 158 * these "Data Buffer Chain Entries".) 159 * 160 * note, this structure must be a multiple of sizeof (intptr_t) 161 */ 162 struct dca_chain { 163 /* the descriptor */ 164 caddr_t dc_desc_kaddr; 165 /* and the buffer to which it points */ 166 size_t dc_buffer_length; 167 ddi_dma_handle_t dc_buffer_dmah; 168 caddr_t dc_buffer_kaddr; 169 /* physical addresses */ 170 uint32_t dc_desc_paddr; 171 uint32_t dc_buffer_paddr; 172 uint32_t dc_next_paddr; 173 }; 174 175 /* 176 * Linked-list linkage. 177 */ 178 struct dca_listnode { 179 dca_listnode_t *dl_next; 180 dca_listnode_t *dl_prev; 181 dca_listnode_t *dl_next2; 182 dca_listnode_t *dl_prev2; 183 }; 184 185 typedef enum dca_mech_type { 186 DES_CBC_MECH_INFO_TYPE, /* SUN_CKM_DES_CBC */ 187 DES3_CBC_MECH_INFO_TYPE, /* SUN_CKM_DES3_CBC */ 188 DSA_MECH_INFO_TYPE, /* SUN_CKM_DSA */ 189 RSA_X_509_MECH_INFO_TYPE, /* SUN_CKM_RSA_X_509 */ 190 RSA_PKCS_MECH_INFO_TYPE /* SUN_CKM_RSA_PKCS */ 191 } dca_mech_type_t; 192 193 #define SUN_CKM_DSA "CKM_DSA" 194 195 struct dca_rng { 196 uint32_t dr_chunklen; 197 }; 198 199 union dca_parameters { 200 struct dca_rng dp_rng; 201 }; 202 203 typedef struct dca_ctx { 204 /* 205 * The following are context fields for Deimos 2.0. 206 */ 207 crypto_mech_type_t ctx_cm_type; /* Mechanism type */ 208 int mode; /* Mode of operation */ 209 int atomic; /* Boolean */ 210 211 /* Fields for RSA and DSA */ 212 uchar_t *mod; /* RSA modulus */ 213 unsigned modlen; /* RSA modulus length */ 214 unsigned pqfix; /* RSA flag */ 215 216 /* Fields for DES and 3DES */ 217 uint32_t iv[2]; 218 uint32_t key[6]; 219 int residlen; 220 uchar_t resid[DESBLOCK]; 221 int activeresidlen; 222 uchar_t activeresid[DESBLOCK]; 223 crypto_data_t in_dup; /* input data duplicate */ 224 } dca_ctx_t; 225 226 /* 227 * Work structure. One of these per actual job submitted to an MCR. 228 * Contains everything we need to submit the job, and everything we 229 * need to notify caller and release resources when the completion 230 * interrupt comes. 231 */ 232 struct dca_request { 233 dca_listnode_t dr_linkage; 234 uint16_t dr_pkt_length; 235 crypto_req_handle_t dr_kcf_req; 236 dca_t *dr_dca; 237 dca_worklist_t *dr_wlp; 238 /* 239 * Consumer's I/O buffers. 240 */ 241 crypto_data_t *dr_in; 242 crypto_data_t *dr_out; 243 dca_ctx_t dr_ctx; 244 /* 245 * Chains and DMA structures. 246 */ 247 size_t dr_dma_size; 248 uint32_t dr_ctx_paddr; 249 caddr_t dr_ctx_kaddr; 250 ddi_acc_handle_t dr_ctx_acch; 251 ddi_dma_handle_t dr_ctx_dmah; 252 /* 253 * Scratch input buffer. 254 */ 255 ddi_acc_handle_t dr_ibuf_acch; 256 ddi_dma_handle_t dr_ibuf_dmah; 257 caddr_t dr_ibuf_kaddr; 258 uint32_t dr_ibuf_paddr; 259 260 /* 261 * Scratch output buffer. 262 */ 263 ddi_acc_handle_t dr_obuf_acch; 264 ddi_dma_handle_t dr_obuf_dmah; 265 caddr_t dr_obuf_kaddr; 266 uint32_t dr_obuf_paddr; 267 268 /* 269 * Values to program MCR with. 270 */ 271 uint32_t dr_in_paddr; 272 uint32_t dr_out_paddr; 273 uint32_t dr_in_next; 274 uint32_t dr_out_next; 275 uint16_t dr_in_len; 276 uint16_t dr_out_len; 277 /* 278 * Callback. 279 */ 280 void (*dr_callback)(dca_request_t *, int); 281 /* 282 * Other stuff. 283 */ 284 uint32_t dr_flags; 285 /* 286 * Algorithm specific parameters. 287 */ 288 void *dr_context; 289 union dca_parameters dr_param; 290 /* 291 * Statistics. 292 */ 293 int dr_job_stat; 294 int dr_byte_stat; 295 296 /* Pre-mapped input and output data buffer chain support */ 297 dca_chain_t dr_ibuf_head; 298 dca_chain_t dr_obuf_head; 299 300 /* 301 * User buffers are mapped to DMA handles dynamically. The physically 302 * contigous blocks ( >= a page) are built into a data buffer chain. 303 */ 304 dca_chain_t dr_chain_in_head; 305 ddi_dma_handle_t dr_chain_in_dmah; 306 307 dca_chain_t dr_chain_out_head; 308 ddi_dma_handle_t dr_chain_out_dmah; 309 310 /* Offset in the context page for storing dynamic buffer chains */ 311 int dr_offset; 312 313 /* Destroy this request if true */ 314 int destroy; 315 }; 316 317 /* 318 * Request flags (dca_request_t.dr_flags). 319 */ 320 #define DR_INPLACE 0x002 321 #define DR_SCATTER 0x004 322 #define DR_GATHER 0x008 323 #define DR_NOCACHE 0x020 324 #define DR_ENCRYPT 0x040 325 #define DR_DECRYPT 0x080 326 #define DR_TRIPLE 0x100 /* triple DES vs. single DES */ 327 #define DR_ATOMIC 0x200 /* for atomic operation */ 328 329 struct dca_work { 330 dca_listnode_t dw_linkage; 331 dca_worklist_t *dw_wlp; 332 333 /* DMA access to the MCR and context */ 334 ddi_acc_handle_t dw_mcr_acch; 335 ddi_dma_handle_t dw_mcr_dmah; 336 caddr_t dw_mcr_kaddr; 337 uint32_t dw_mcr_paddr; 338 339 dca_request_t *dw_reqs[MAXREQSPERMCR]; 340 clock_t dw_lbolt; 341 }; 342 343 /* 344 * MCRs. 345 */ 346 #define MCR1 0x1 347 #define MCR2 0x2 348 349 struct dca_worklist { 350 dca_t *dwl_dca; 351 crypto_kcf_provider_handle_t dwl_prov; 352 char dwl_name[16]; 353 int dwl_mcr; 354 kmutex_t dwl_lock; 355 kmutex_t dwl_freereqslock; 356 kcondvar_t dwl_cv; 357 dca_listnode_t dwl_freereqs; /* available requests */ 358 dca_listnode_t dwl_waitq; /* requests arrive here */ 359 dca_listnode_t dwl_freework; /* available work structures */ 360 dca_listnode_t dwl_runq; /* work structs sent to chip */ 361 timeout_id_t dwl_schedtid; 362 clock_t dwl_lastsubmit; 363 int dwl_count; 364 int dwl_busy; 365 int dwl_lowater; 366 int dwl_hiwater; 367 int dwl_reqspermcr; 368 int dwl_drain; /* for DR (suspend) */ 369 /* Kstats */ 370 u_longlong_t dwl_submit; 371 u_longlong_t dwl_flowctl; 372 }; 373 374 /* 375 * Operations for MCR1 (bulk stuff). 376 */ 377 #define CMD_IPSEC 0x0 /* IPsec packet processing */ 378 #define CMD_SSLMAC 0x1 /* SSL HMAC processing */ 379 #define CMD_TLSMAC 0x2 /* TLS HMAC processing */ 380 #define CMD_3DES 0x3 /* SSL/TLS/raw 3DES processing */ 381 #define CMD_RC4 0x4 /* ARCFOUR procesing */ 382 #define CMD_PUREHASH 0x5 /* Pure MD5/SHA1 hash processing */ 383 384 /* 385 * Operations for MCR2 (key stuff). 386 */ 387 #define CMD_DHPUBLIC 0x1 /* DH public key generation */ 388 #define CMD_DHSHARED 0x2 /* DH shared secret generation */ 389 #define CMD_RSAPUBLIC 0x3 /* RSA public key operation */ 390 #define CMD_RSAPRIVATE 0x4 /* RSA private key operation (CRT) */ 391 #define CMD_DSASIGN 0x5 /* DSA signing operation */ 392 #define CMD_DSAVERIFY 0x6 /* DSA verification operation */ 393 #define CMD_RNGDIRECT 0x41 /* Direct access to the RNG */ 394 #define CMD_RNGSHA1 0x42 /* RNG output processed by SHA1 */ 395 #define CMD_MODADD 0x43 /* Modular add */ 396 #define CMD_MODSUB 0x44 /* Moduler subtract */ 397 #define CMD_MODMUL 0x45 /* Modular multiply */ 398 #define CMD_MODREM 0x46 /* Modular remainder */ 399 #define CMD_MODEXP 0x47 /* Modular exponentiation */ 400 #define CMD_MODINV 0x48 /* Modular inverse */ 401 402 /* 403 * Kstats. 404 */ 405 #define DS_3DESJOBS 0 406 #define DS_3DESBYTES 1 407 #define DS_RSAPUBLIC 2 408 #define DS_RSAPRIVATE 3 409 #define DS_DSASIGN 4 410 #define DS_DSAVERIFY 5 411 #define DS_RNGJOBS 6 412 #define DS_RNGBYTES 7 413 #define DS_RNGSHA1JOBS 8 414 #define DS_RNGSHA1BYTES 9 415 #define DS_MAX 10 416 417 #if 0 418 /* 419 * note that when reenabling any of these stats, DS_MAX will need to 420 * be adjusted. 421 */ 422 #define DS_RC4JOBS 11 423 #define DS_RC4BYTES 12 424 #define DS_DHPUBLIC 13 425 #define DS_DHSECRET 14 426 #endif 427 428 struct dca_stat { 429 kstat_named_t ds_status; 430 kstat_named_t ds_algs[DS_MAX]; 431 struct { 432 kstat_named_t ds_submit; 433 kstat_named_t ds_flowctl; 434 kstat_named_t ds_lowater; 435 kstat_named_t ds_hiwater; 436 kstat_named_t ds_maxreqs; 437 } ds_mcr[MAXMCR]; 438 }; 439 440 /* 441 * Blocking structure for ioctls. 442 */ 443 struct dca_cookie { 444 kmutex_t dc_mx; 445 kcondvar_t dc_cv; 446 int dc_outstanding; 447 int dc_status; 448 }; 449 450 /* 451 * Per instance structure. 452 */ 453 struct dca { 454 dev_info_t *dca_dip; 455 kmutex_t dca_intrlock; 456 caddr_t dca_regs; 457 ddi_acc_handle_t dca_regs_handle; 458 ddi_iblock_cookie_t dca_icookie; 459 timeout_id_t dca_jobtid; 460 ulong_t dca_pagesize; 461 unsigned dca_flags; /* dev state flags */ 462 463 /* 464 * Work requests. 465 */ 466 dca_worklist_t dca_worklist[MAXMCR]; 467 468 /* 469 * hardware model 470 */ 471 char *dca_model; 472 473 /* 474 * Kstats. There is no standard for what standards 475 * Cryptographic Providers should supply, so we're 476 * making them up for now. 477 */ 478 kstat_t *dca_ksp; 479 kstat_t *dca_intrstats; 480 u_longlong_t dca_stats[DS_MAX]; 481 482 /* For the local random number pool used internally by the dca driver */ 483 char *dca_buf1; 484 char *dca_buf2; 485 char *dca_buf_ptr; 486 int dca_index; 487 uint32_t dca_random_filling; 488 kmutex_t dca_random_lock; 489 490 /* FMA capabilities */ 491 int fm_capabilities; /* FMA capabilities */ 492 493 kmutex_t dca_ctx_list_lock; 494 dca_listnode_t dca_ctx_list; 495 }; 496 497 /* 498 * Device flags (dca_t.dca_flags) 499 */ 500 #define DCA_FAILED 0x1 501 #define DCA_POWERMGMT 0x4 502 #define DCA_RNGSHA1 0x8 503 504 #define KIOIP(dca) KSTAT_INTR_PTR((dca)->dca_intrstats) 505 506 /* 507 * Scatter/gather checks. 508 */ 509 typedef enum dca_sg_param { 510 DCA_SG_CONTIG = 1, 511 DCA_SG_WALIGN, 512 DCA_SG_PALIGN 513 } dca_sg_param_t; 514 515 #define FALSE 0 516 #define TRUE 1 517 518 /* 519 * PCI configuration registers. 520 */ 521 #define PCI_VENID 0x00 /* vendor id, 16 bits */ 522 #define PCI_DEVID 0x02 /* device id, 16 bits */ 523 #define PCI_COMM 0x04 /* command, 16 bits */ 524 #define PCI_STATUS 0x06 /* status, 16 bits */ 525 #define PCI_REVID 0x08 /* revision id, 8 bits */ 526 #define PCI_PROGCLASS 0x09 /* programming class, 8 bits */ 527 #define PCI_SUBCLASS 0x0A /* subclass, 8 bits */ 528 #define PCI_CACHELINESZ 0x0C /* cache line size, 8 bits */ 529 #define PCI_LATTMR 0x0D /* latency timer, 8 bits */ 530 #define PCI_BIST 0x0F /* builtin-self-test, 8 bits */ 531 #define PCI_SUBVENID 0x2C /* subsystem vendor id, 16 bits */ 532 #define PCI_SUBSYSID 0x2E /* subsystem id, 16 bits */ 533 #define PCI_MINGNT 0x3E /* min grant for burst, 8 bits */ 534 #define PCI_MAXLAT 0x3F /* maximum grant for burst, 8 bits */ 535 #define PCI_TRDYTO 0x40 /* TRDY timeout, 8 bits */ 536 #define PCI_RETRIES 0x41 /* retries bus will perform, 8 bits */ 537 538 /* 539 * PCI configuration register bit values. 540 */ 541 #define PCICOMM_FBBE 0x0200 /* fast back-to-back enable */ 542 #define PCICOMM_SEE 0x0100 /* system error enable */ 543 #define PCICOMM_PEE 0x0040 /* parity error enable */ 544 #define PCICOMM_MWIE 0x0010 /* memory write & invalidate enable */ 545 #define PCICOMM_BME 0x0004 /* bus master enable */ 546 #define PCICOMM_MAE 0x0002 /* memory access enable */ 547 548 #define PCISTAT_PERR 0x8000 /* parity error detected */ 549 #define PCISTAT_SERR 0x4000 /* system error detected */ 550 #define PCISTAT_MABRT 0x2000 /* master abort detected */ 551 #define PCISTAT_TABRT 0x1000 /* target abort detected */ 552 #define PCISTAT_TABRTS 0x0800 /* target abort signaled */ 553 #define PCISTAT_PARITY 0x0100 /* data parity error detected */ 554 555 #define PCIREVID_DOMESTIC 0x01 /* domestic version */ 556 #define PCIREVID_EXPORT 0xE1 /* export version */ 557 558 /* Note: 5820 errata: BIST feature does not work */ 559 #define PCIBIST_CAP 0x80 /* BIST capable */ 560 #define PCIBIST_START 0x40 /* start BIST test */ 561 #define PCIBIST_ERRMASK 0x0F /* mask of BIST error codes */ 562 563 /* 564 * Command and Status Registers. 565 */ 566 #define CSR_MCR1 0x00 /* pointer to MCR1 (bulk) */ 567 #define CSR_DMACTL 0x04 /* DMA control */ 568 #define CSR_DMASTAT 0x08 /* DMA status */ 569 #define CSR_DMAEA 0x0C /* DMA error address */ 570 #define CSR_MCR2 0x10 /* pointer to MCR2 (exponentiator) */ 571 572 /* 573 * Command and status register bits. 574 */ 575 #define DMACTL_RESET 0x80000000U /* reset the chip */ 576 #define DMACTL_MCR2IE 0x40000000U /* MCR2 interrupt enable */ 577 #define DMACTL_MCR1IE 0x20000000U /* MCR1 interrupt enable */ 578 #define DMACTL_OFM 0x10000000U /* output fragment mode */ 579 #define DMACTL_BE32 0x08000000U /* 32-bit big endian mode */ 580 #define DMACTL_BE64 0x04000000U /* 64-bit big endian mode */ 581 #define DMACTL_EIE 0x02000000U /* error interrupt enable */ 582 #define DMACTL_RNGMASK 0x01800000U /* RNG mode mask */ 583 #define DMACTL_RNG1 0x00000000U /* 1 RNG bit per cycle */ 584 #define DMACTL_RNG4 0x00800000U /* 1 RNG bit per 4 cycles */ 585 #define DMACTL_RNG8 0x01000000U /* 1 RNG bit per 8 cycles */ 586 #define DMACTL_RNG16 0x01800000U /* 1 RNG bit per 16 cycles */ 587 #define DMACTL_MODNORM 0x00400000U /* s/w modulus normalization */ 588 #define DMACTL_FRAGMASK 0x0000FFFFU /* output fragment size */ 589 590 #define DMASTAT_MAIP 0x80000000U /* master access in progress */ 591 #define DMASTAT_MCR1FULL 0x40000000U /* MCR1 is full */ 592 #define DMASTAT_MCR1INT 0x20000000U /* MCR1 interrupted */ 593 #define DMASTAT_ERRINT 0x10000000U /* error interrupted */ 594 #define DMASTAT_MCR2FULL 0x08000000U /* MCR2 is full */ 595 #define DMASTAT_MCR2INT 0x04000000U /* MCR2 interrupted */ 596 #define DMASTAT_INTERRUPTS 0x34000000U /* all interrupts */ 597 598 /* 599 * Offsets of things relative to an MCR. 600 */ 601 #define MCR_COUNT 0 /* 16 bits */ 602 #define MCR_FLAGS 2 /* 16 bits */ 603 #define MCR_CTXADDR 4 /* 32 bits */ 604 605 /* 606 * Basis for size (should be optimized by constant folding): 607 * 4 bytes for flags and #packets. 608 * for each packet: 609 * 2 descriptors (DESC_SIZE) 610 * 4 bytes for context address 611 * 4 bytes for packet length and reserved 612 */ 613 #define MCR_SIZE (4 + MAXREQSPERMCR * ((2 * DESC_SIZE) + 8)) 614 615 /* 616 * MCR flags. 617 */ 618 #define MCRFLAG_FINISHED 0x0001 /* MCR processing complete */ 619 #define MCRFLAG_ERROR 0x0002 /* set if an error occured */ 620 #define MCRFLAG_ERRORMASK 0xff00 /* error code bits */ 621 622 /* 623 * Fields within a descriptor (data buffer chain). 624 */ 625 #define DESC_BUFADDR 0 /* 32 bits */ 626 #define DESC_NEXT 4 /* 32 bits */ 627 #define DESC_LENGTH 8 /* 16 bits */ 628 #define DESC_RSVD 10 /* 16 bits */ 629 #define DESC_SIZE 16 /* ROUNDUP(12, 16) - descriptor size (bytes) */ 630 631 /* 632 * Offsets of fields within context structures, see Broadcom spec. 633 */ 634 #define CTX_LENGTH 0 /* 16 bits */ 635 #define CTX_CMD 2 /* 16 bits */ 636 #define CTX_MAXLENGTH 768 /* max size of ctx, fits anything */ 637 638 #define CTX_3DESDIRECTION 4 /* 16 bits */ 639 #define CTX_3DESKEY1HI 8 /* 32 bits */ 640 #define CTX_3DESKEY1LO 12 /* 32 bits */ 641 #define CTX_3DESKEY2HI 16 /* 32 bits */ 642 #define CTX_3DESKEY2LO 20 /* 32 bits */ 643 #define CTX_3DESKEY3HI 24 /* 32 bits */ 644 #define CTX_3DESKEY3LO 28 /* 32 bits */ 645 #define CTX_3DESIVHI 32 /* 32 bits */ 646 #define CTX_3DESIVLO 36 /* 32 bits */ 647 648 #define CTX_IPSECFLAGS 4 /* 16 bits */ 649 #define CTX_IPSECOFFSET 6 /* 16 bits */ 650 #define CTX_IPSECKEY1HI 8 /* 32 bits */ 651 #define CTX_IPSECKEY1LO 12 /* 32 bits */ 652 #define CTX_IPSECKEY2HI 16 /* 32 bits */ 653 #define CTX_IPSECKEY2LO 20 /* 32 bits */ 654 #define CTX_IPSECKEY3HI 24 /* 32 bits */ 655 #define CTX_IPSECKEY3LO 28 /* 32 bits */ 656 #define CTX_IPSECIVHI 32 /* 32 bits */ 657 #define CTX_IPSECIVLO 36 /* 32 bits */ 658 #define CTX_IPSECHMACINNER1 40 /* 32 bits */ 659 #define CTX_IPSECHMACINNER2 44 /* 32 bits */ 660 #define CTX_IPSECHMACINNER3 48 /* 32 bits */ 661 #define CTX_IPSECHMACINNER4 52 /* 32 bits */ 662 #define CTX_IPSECHMACINNER5 56 /* 32 bits */ 663 #define CTX_IPSECHMACOUTER1 60 /* 32 bits */ 664 #define CTX_IPSECHMACOUTER2 64 /* 32 bits */ 665 #define CTX_IPSECHMACOUTER3 68 /* 32 bits */ 666 #define CTX_IPSECHMACOUTER4 72 /* 32 bits */ 667 #define CTX_IPSECHMACOUTER5 76 /* 32 bits */ 668 669 #define CTX_RSAEXPLEN 4 /* 16 bits */ 670 #define CTX_RSAMODLEN 6 /* 16 bits */ 671 #define CTX_RSABIGNUMS 8 /* variable length */ 672 #define CTX_RSAQLEN 4 /* 16 bits */ 673 #define CTX_RSAPLEN 6 /* 16 bits */ 674 675 #define CTX_DSAMSGTYPE 4 /* 16 bits */ 676 #define CTX_DSARSVD 6 /* 16 bits */ 677 #define CTX_DSARNG 8 /* 16 bits */ 678 #define CTX_DSAPLEN 10 /* 16 bits */ 679 #define CTX_DSABIGNUMS 12 /* variable length */ 680 681 /* 682 * Values for specific operations. 683 */ 684 #define CTX_RNG_LENGTH 64 /* context length for RNG (64 min) */ 685 #define CTX_3DES_LENGTH 64 /* context length for 3DES (64 min) */ 686 #define CTX_3DES_DECRYPT 0x4000 /* perform decryption */ 687 #define CTX_3DES_ENCRYPT 0x0000 /* perform encryption */ 688 #define CTX_IPSEC_LENGTH 80 /* context length for IPsec */ 689 #define CTX_IPSEC_ENCRYPT 0x8000 /* perform encryption */ 690 #define CTX_IPSEC_DECRYPT 0xc000 /* perform decryption */ 691 #define CTX_IPSEC_HMAC_MD5 0x1000 /* HMAC-MD5 authentication */ 692 #define CTX_IPSEC_HMAC_SHA1 0x2000 /* HMAC-MD5 authentication */ 693 #define CTX_DSAMSGTYPE_SHA1 0 /* Message is SHA1 */ 694 #define CTX_DSAMSGTYPE_TEXT 1 /* Generate SHA1 hash first */ 695 #define CTX_DSARNG_GEN 1 /* Generate random k */ 696 #define CTX_DSARNG_SUPPLY 0 /* Random k is supplied */ 697 698 /* 699 * Macros to access fields within the MCR. Note that this includes the 700 * context fields as well, since the context is just offset from the 701 * base of the MCR. 702 */ 703 704 #define PUTMCR32(work, reg, val) \ 705 ddi_put32(work->dw_mcr_acch, \ 706 (uint32_t *)(work->dw_mcr_kaddr + reg), val) 707 708 #define PUTMCR16(work, reg, val) \ 709 ddi_put16(work->dw_mcr_acch, \ 710 (uint16_t *)(work->dw_mcr_kaddr + reg), val) 711 712 #define GETMCR32(work, reg) \ 713 ddi_get32(work->dw_mcr_acch, (uint32_t *)(work->dw_mcr_kaddr + reg)) 714 715 #define GETMCR16(work, reg) \ 716 ddi_get16(work->dw_mcr_acch, (uint16_t *)(work->dw_mcr_kaddr + reg)) 717 718 #define PUTDESC32(req, dc_desc_kaddr, reg, val) \ 719 ddi_put32(req->dr_ctx_acch, \ 720 (uint32_t *)(dc_desc_kaddr + reg), val) 721 722 #define PUTDESC16(req, dc_desc_kaddr, reg, val) \ 723 ddi_put16(req->dr_ctx_acch, \ 724 (uint16_t *)(dc_desc_kaddr + reg), val) 725 726 /* XXX: define the GET forms for descriptors only if needed */ 727 728 #define PUTCTX32(req, reg, val) \ 729 ddi_put32(req->dr_ctx_acch, \ 730 (uint32_t *)(req->dr_ctx_kaddr + reg), val) 731 732 #define PUTCTX16(req, reg, val) \ 733 ddi_put16(req->dr_ctx_acch, \ 734 (uint16_t *)(req->dr_ctx_kaddr + reg), val) 735 736 #define CTXBCOPY(req, src, dst, count) \ 737 ddi_rep_put8(req->dr_ctx_acch, (uchar_t *)src, (uchar_t *)dst, count, \ 738 DDI_DEV_AUTOINCR) 739 740 /* 741 * Register access. 742 */ 743 #define GETCSR(dca, reg) \ 744 ddi_get32(dca->dca_regs_handle, (uint_t *)(dca->dca_regs + reg)) 745 746 #define PUTCSR(dca, reg, val) \ 747 ddi_put32(dca->dca_regs_handle, (uint_t *)(dca->dca_regs + reg), val) 748 749 #define SETBIT(dca, reg, val) \ 750 PUTCSR(dca, reg, GETCSR(dca, reg) | val) 751 752 #define CLRBIT(dca, reg, val) \ 753 PUTCSR(dca, reg, GETCSR(dca, reg) & ~val) 754 755 /* 756 * Used to guarantee alignment. 757 */ 758 #define ROUNDUP(a, n) (((a) + ((n) - 1)) & ~((n) - 1)) 759 #define ROUNDDOWN(a, n) (((a) & ~((n) - 1))) 760 #define HIDBLWORD(x) (((x) & 0xffffffff00000000ULL) >> 32) 761 #define LODBLWORD(x) ((x) & 0xffffffffULL) 762 763 /* 764 * Driver hardening related. 765 */ 766 #define CHECK_REGS(dca) ddi_check_acc_handle(dca->dca_regs_handle) 767 768 /* 769 * Other utility macros. 770 */ 771 #define QEMPTY(q) ((q)->dl_next == (q)) 772 #define BITS2BYTES(b) ((b) >> 3) 773 #define WORKLIST(dca, mcr) (&((dca)->dca_worklist[mcr - 1])) 774 775 /* 776 * Debug stuff. 777 */ 778 #ifdef DEBUG 779 #define DWARN 0x0001 780 #define DPCI 0x0002 781 #define DINTR 0x0004 782 #define DSTART 0x0008 783 #define DRECLAIM 0x0010 784 #define DCHATTY 0x0020 785 #define DMOD 0x0040 /* _init/_fini/_info/attach/detach */ 786 #define DENTRY 0x0080 /* crypto routine entry/exit points */ 787 788 void dca_dprintf(dca_t *, int, const char *, ...); 789 #define DBG dca_dprintf 790 #else 791 #define DBG(dca, lvl, ...) 792 #endif 793 794 /* 795 * Some pkcs#11 defines as there are no pkcs#11 header files included. 796 */ 797 #define CKO_PUBLIC_KEY 0x00000002 798 #define CKO_PRIVATE_KEY 0x00000003 799 800 #define CKA_CLASS 0x00000000 801 #define CKA_VALUE 0x00000011 802 #define CKA_KEY_TYPE 0x00000100 803 #define CKA_MODULUS 0x00000120 804 #define CKA_PUBLIC_EXPONENT 0x00000122 805 #define CKA_PRIVATE_EXPONENT 0x00000123 806 #define CKA_PRIME_1 0x00000124 807 #define CKA_PRIME_2 0x00000125 808 #define CKA_EXPONENT_1 0x00000126 809 #define CKA_EXPONENT_2 0x00000127 810 #define CKA_COEFFICIENT 0x00000128 811 #define CKA_PRIME 0x00000130 812 #define CKA_SUBPRIME 0x00000131 813 #define CKA_BASE 0x00000132 814 /* 815 * Driver globals. 816 */ 817 extern int dca_mindma; 818 extern int dca_hardening; 819 820 /* 821 * Prototypes. 822 */ 823 824 /* 825 * dca_debug.c 826 */ 827 void dca_error(dca_t *, const char *, ...); 828 void dca_diperror(dev_info_t *, const char *, ...); 829 void dca_dipverror(dev_info_t *, const char *, va_list); 830 /* 831 * dca_3des.c 832 */ 833 int dca_3desctxinit(crypto_ctx_t *, crypto_mechanism_t *, crypto_key_t *, 834 int, int); 835 int dca_3des(crypto_ctx_t *, crypto_data_t *, crypto_data_t *, 836 crypto_req_handle_t, int); 837 int dca_3desupdate(crypto_ctx_t *, crypto_data_t *, crypto_data_t *, 838 crypto_req_handle_t, int); 839 int dca_3desfinal(crypto_ctx_t *, crypto_data_t *, int); 840 int dca_3desatomic(crypto_provider_handle_t, crypto_session_id_t, 841 crypto_mechanism_t *, crypto_key_t *, crypto_data_t *, crypto_data_t *, 842 int, crypto_req_handle_t, int); 843 void dca_3desctxfree(void *); 844 845 /* 846 * dca_rsa.c 847 */ 848 int dca_rsastart(crypto_ctx_t *, crypto_data_t *, crypto_data_t *, 849 crypto_req_handle_t, int); 850 int dca_rsainit(crypto_ctx_t *, crypto_mechanism_t *, crypto_key_t *, int); 851 void dca_rsactxfree(void *); 852 int dca_rsaatomic(crypto_provider_handle_t, crypto_session_id_t, 853 crypto_mechanism_t *, crypto_key_t *, crypto_data_t *, crypto_data_t *, 854 int, crypto_req_handle_t, int); 855 856 /* 857 * dca_dsa.c 858 */ 859 int dca_dsa_sign(crypto_ctx_t *, crypto_data_t *, crypto_data_t *, 860 crypto_req_handle_t); 861 int dca_dsa_verify(crypto_ctx_t *, crypto_data_t *, crypto_data_t *, 862 crypto_req_handle_t); 863 int dca_dsainit(crypto_ctx_t *, crypto_mechanism_t *, crypto_key_t *, int, 864 int); 865 void dca_dsactxfree(void *); 866 int dca_dsaatomic(crypto_provider_handle_t, crypto_session_id_t, 867 crypto_mechanism_t *, crypto_key_t *, crypto_data_t *, crypto_data_t *, 868 int, crypto_req_handle_t, int); 869 870 /* 871 * dca_rng.c 872 */ 873 int dca_rng(dca_t *, uchar_t *, size_t len, crypto_req_handle_t); 874 int dca_random_buffer(dca_t *dca, caddr_t buf, int len); 875 int dca_random_init(); 876 void dca_random_fini(); 877 878 /* 879 * dca_kstat.c 880 */ 881 void dca_ksinit(dca_t *); 882 /* 883 * dca.c 884 */ 885 void dca_rmqueue(dca_listnode_t *); 886 dca_request_t *dca_getreq(dca_t *, int, int); 887 void dca_freereq(dca_request_t *); 888 int dca_bindchains(dca_request_t *, size_t, size_t); 889 int dca_unbindchains(dca_request_t *); 890 int dca_start(dca_t *, dca_request_t *, int, int); 891 void dca_done(dca_request_t *, int); 892 void dca_destroyreq(dca_request_t *); 893 int dca_length(crypto_data_t *); 894 int dca_gather(crypto_data_t *, char *, int, int); 895 int dca_resid_gather(crypto_data_t *, char *, int *, char *, int); 896 int dca_scatter(const char *, crypto_data_t *, int, int); 897 int dca_bcmp_reverse(const void *s1, const void *s2, size_t n); 898 int dca_dupcrypto(crypto_data_t *, crypto_data_t *); 899 int dca_verifyio(crypto_data_t *, crypto_data_t *); 900 int dca_getbufbytes(crypto_data_t *, size_t, int, uchar_t *); 901 int dca_sgcheck(dca_t *, crypto_data_t *, dca_sg_param_t); 902 crypto_object_attribute_t * 903 dca_get_key_attr(crypto_key_t *); 904 int dca_attr_lookup_uint32(crypto_object_attribute_t *, uint_t, uint64_t, 905 uint32_t *); 906 int dca_attr_lookup_uint8_array(crypto_object_attribute_t *, uint_t, 907 uint64_t, void **, unsigned int *); 908 crypto_object_attribute_t * 909 dca_find_attribute(crypto_object_attribute_t *, uint_t, uint64_t); 910 caddr_t dca_bufdaddr(crypto_data_t *); 911 void dca_rcoalesce(dca_request_t *, int); 912 void dca_runcoalesce(dca_request_t *); 913 int dca_bitlen(unsigned char *, int); 914 uint16_t dca_padhalf(int); 915 uint16_t dca_padfull(int); 916 void dca_reverse(void *, void *, int, int); 917 int dca_numcmp(caddr_t, int, caddr_t, int); 918 int dca_check_dma_handle(dca_t *dca, ddi_dma_handle_t handle, 919 dca_fma_eclass_t eclass_index); 920 int dca_free_context(crypto_ctx_t *ctx); 921 922 #endif /* _KERNEL */ 923 924 #ifdef __cplusplus 925 } 926 #endif 927 928 #endif /* _SYS_CRYPTO_DCA_H */ 929