1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_AUXV_386_H 28 #define _SYS_AUXV_386_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Flags used in AT_SUN_HWCAP elements to describe various userland 38 * instruction set extensions available on different processors. 39 * The basic assumption is that of the i386 ABI; that is, i386 plus i387 40 * floating point. 41 * 42 * Note that if a given bit is set; the implication is that the kernel 43 * provides all the underlying architectural support for the correct 44 * functioning of the extended instruction(s). 45 */ 46 #define AV_386_FPU 0x00001 /* x87-style floating point */ 47 #define AV_386_TSC 0x00002 /* rdtsc insn */ 48 #define AV_386_CX8 0x00004 /* cmpxchg8b insn */ 49 #define AV_386_SEP 0x00008 /* sysenter and sysexit */ 50 #define AV_386_AMD_SYSC 0x00010 /* AMD's syscall and sysret */ 51 #define AV_386_CMOV 0x00020 /* conditional move insns */ 52 #define AV_386_MMX 0x00040 /* MMX insns */ 53 #define AV_386_AMD_MMX 0x00080 /* AMD's MMX insns */ 54 #define AV_386_AMD_3DNow 0x00100 /* AMD's 3Dnow! insns */ 55 #define AV_386_AMD_3DNowx 0x00200 /* AMD's 3Dnow! extended insns */ 56 #define AV_386_FXSR 0x00400 /* fxsave and fxrstor */ 57 #define AV_386_SSE 0x00800 /* SSE insns and regs */ 58 #define AV_386_SSE2 0x01000 /* SSE2 insns and regs */ 59 #define AV_386_PAUSE 0x02000 /* use pause insn (in spin loops) */ 60 #define AV_386_SSE3 0x04000 /* SSE3 insns and regs */ 61 #define AV_386_MON 0x08000 /* monitor/mwait insns */ 62 #define AV_386_CX16 0x10000 /* cmpxchg16b insn */ 63 64 #define FMT_AV_386 \ 65 "\20" \ 66 "\21cx16" \ 67 "\20mon\17sse3\16pause\15sse2\14sse\13fxsr\12amd3dx\11amd3d" \ 68 "\10amdmmx\7mmx\6cmov\5amdsysc\4sep\3cx8\2tsc\1fpu" 69 70 #ifdef __cplusplus 71 } 72 #endif 73 74 #endif /* !_SYS_AUXV_386_H */ 75